UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 641

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(b) When LVI Default Start Function Enabled Is Set (Option Byte: LVIOFF = 0)
• When starting operation
• When stopping operation
Caution Even when the LVI default start function is used, if it is set to LVI operation prohibition by
Either of the following procedures must be executed.
Figure 20-6 shows the timing of the internal reset signal generated by the low-voltage detector.
Start in the following initial setting state.
When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
Set the low-voltage detection level selection register (LVIS) to 0EH (default value: V
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
Set bit 0 (LVIF) of LVIM to 0 (“Supply voltage (V
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(V
DD
))
the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
reset release.
normally, however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
CHAPTER 20 LOW-VOLTAGE DETECTOR
There is a period when low-voltage detection cannot be performed
User’s Manual U17854EJ9V0UD
DD
) ≥ detection voltage (V
LVI
)”)
LVI
= 2.07 V ±0.1 V ).
μ
s max.,
639

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