UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 658

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.1.2 On-chip debug option byte (000C3H/ 010C3H)
22.2 Format of User Option Byte
656
Address: 000C0H/010C0H
The format of user option byte is shown below.
Control of on-chip debug operation
• On-chip debug operation is disabled or enabled.
Handling of data of flash memory in case of failure in on-chip debug security ID authentication
• Data of flash memory is erased or not erased in case of failure in on-chip debug security ID
Caution Set the same value as 000C3H to 010C3H when the boot swap operation is used because
authentication.
WINDOW1
WDTINIT
WDTINIT
WDTON
WDCS2
7
0
1
0
0
1
1
0
1
0
0
0
0
1
1
1
1
000C3H is replaced by 010C3H.
Figure 22-1. Format of User Option Byte (000C0H/010C0H) (1/2)
Note 1
Interval interrupt is not used.
Interval interrupt is generated when 75% of the overflow time is reached.
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
WINDOW0
WINDOW1
WDCS1
6
0
1
0
1
0
0
1
1
0
0
1
1
25%
50%
75%
100%
WINDOW0
WDCS0
CHAPTER 22 OPTION BYTE
5
0
1
0
1
0
1
0
1
User’s Manual U17854EJ9V0UD
Operation control of watchdog timer counter
Use of interval interrupt of watchdog timer
2
2
2
2
2
2
2
2
10
11
12
13
15
17
18
20
WDTON
/f
/f
/f
/f
/f
/f
/f
/f
IL
IL
IL
IL
IL
IL
IL
IL
4
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(124.12 ms)
(496.48 ms)
(992.97 ms)
(3971.88 ms)
Watchdog timer window open period
WDCS2
3
Watchdog timer overflow time
WDCS1
2
Note 2
WDCS0
1
WDSTBYON
0

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