UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 659

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: 000C0H/010C0H
Address: 000C1H/010C1H
Notes 1.
Caution The watchdog timer continues its operation during self-programming of the flash memory and
Remarks 1.
Note Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is
Cautions 1. Be sure to set bits 7 to 1 to “1”.
replaced by 010C1H.
2.
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
2.
2. Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
WDSTBYON
Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is
replaced by 010C0H.
The window open period is 100% when WDSTBYON = 0, regardless the value of WINDOW1 and
WINDOW0.
WDTINIT
LVIOFF
software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
f
( ): f
IL
7
0
1
7
1
0
1
reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
: Internal low-speed oscillation clock frequency
IL
= 264 kHz (MAX.)
Figure 22-1. Format of User Option Byte (000C0H/010C0H) (2/2)
Note 1
Note
Counter operation stopped in HALT/STOP mode
Counter operation enabled in HALT/STOP mode
LVI is ON by default (LVI default start function enabled) upon reset release (upon power
application)
LVI is OFF by default (LVI default start function stopped) upon reset release (upon power
application)
WINDOW1
Figure 22-2. Format of Option Byte (000C1H/010C1H)
6
6
1
WINDOW0
Operation control of watchdog timer counter (HALT/STOP mode)
CHAPTER 22 OPTION BYTE
5
5
1
User’s Manual U17854EJ9V0UD
WDTON
Setting of LVI on power application
4
4
1
WDCS2
Note 2
3
3
1
WDCS1
2
2
1
WDCS0
1
1
1
WDSTBYON
LVIOFF
μ
0
0
s max.,
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