UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 684

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
25.3 BCD Correction Circuit Operation
682
The basic operation of the BCD correction circuit is as follows.
(1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a
<1> The BCD code value to which addition is performed is stored in the A register.
<2> By adding the value of the A register and the second operand (value of one more BCD code to be added)
<3> Decimal correction is performed by adding in binary the value of the A register (addition result in binary)
An example is shown below.
Examples 1: 99 + 89 = 188
Examples 2: 85 + 15 = 100
Examples 3: 80 + 80 = 160
as are in binary, the binary operation result is stored in the A register and the correction value is stored in
the BCDADJ register.
and the BCDADJ register (correction value), and the correction result is stored in the A register and CY
flag.
Caution The value read from the BCDADJ register varies depending on the value of the A
MOV A, #99H
ADD A, #89H
ADD A, !BCDADJ
MOV A, #85H
ADD A, #15H
ADD A, !BCDADJ
MOV A, #80H
ADD A, #80H
ADD A, !BCDADJ
BCD code value
register when it is read and those of the CY and AC flags. Therefore, execute the
instruction <3> after the instruction <2> instead of executing any other instructions. To
perform BCD correction in the interrupt enabled state, saving and restoring the A
register is required within the interrupt function. PSW (CY flag and AC flag) is restored
by the RETI instruction.
Instruction
Instruction
Instruction
CHAPTER 25 BCD CORRECTION CIRCUIT
; <1>
; <2>
; <3>
; <1>
; <2>
; <3>
; <1>
; <2>
; <3>
User’s Manual U17854EJ9V0UD
A Register
A Register
A Register
9AH
99H
22H
88H
85H
00H
80H
00H
60H
CY Flag
CY Flag
CY Flag
1
1
0
1
1
1
−
−
−
AC Flag
AC Flag
AC Flag
−
1
0
−
0
1
−
0
0
BCDADJ
BCDADJ
BCDADJ
Register
Register
Register
66H
66H
60H
−
−
−
−
−
−