UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 829

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port
functions
Function
PM0 to PM7,
PM12 to PM14:
Port mode
registers
P16/TI01/TO01/
INTP,
P17/TI02/TO02
P15/RTCDIV/
RTCCL
Port 2
P31/TI03/TO03/
INTP4
P30/RTC1HZ/
INTP3
P40/TOOL0,
P41/TOOL1
P42/TI04/TO04
P60/SCL0,
P61/SDA0
P121 to P124
P140/PCLBUZ0/
INTP6,
P141/PCLBUZ1/
INTP7
ADPC: A/D port
configuration
register
Details of
Function
To use P42/TI04/TO04 as a general-purpose port, set bit 4(TO04) of timer output
register 0 (TO0) and bit 4(TOE04) of timer output enable register 0 (TOE0) to “0”,
which is the same as their default status setting.
To use P16/TI01/TO01/INTP5 or P17/TI02/TO02 as a general-purpose port, set bits 1
and 2 (TO01, TO02) of timer output register 0 (TO0) and bits 1 and 2 (TOE01,
TOE02) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
To use P15/RTCDIV/RTCCL as a general-purpose port, set bit 4 (RCLOE0) of real-
time counter control register 0 (RTCC0) and bit 6 (RCLOE2) of real-time counter
control register 2 (RTCC2) to “0”, which is the same as their default status settings.
See 2.2.12 AV
a digital I/O.
To use P31/TI03/TO03/INTP4 as a general-purpose port, set bit 3 (TO03) of timer
output register 0 (TO0) and bit 3 (TOE03) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting.
To use P30/RTC1HZ/INTP3 as a general-purpose port, set bit 5 (RCLOE1) of real-
time counter control register 0 (RTCC0) to “0”, which is the same as its default status
setting.
When a tool is connected, the P40 pin cannot be used as a port pin.
When the on-chip debug function is used, P41 pin can be used as follows by the
mode setting on the debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
When using P60/SCL0 or P61/SDA0 as a general-purpose port, stop the operation of
serial interface IIC0.
The function setting on P121 to P124 is available only once after the reset release.
The port once set for connection to an oscillator cannot be used as an input port
unless the reset is performed.
To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port,
set bit 7 of clock output select registers 0 and 1 (CKS0, CKS1) to “0”, which is the
same as their default status settings.
Be sure to set bit 7 of PM0, bits 2 to 7 of PM3, bits 4 to 7 of PM4, bits 6 and 7 of
PM5, bits 4 to 7 of PM6, bits 1 to 7 of PM12, and bits 2 to 7 of PM14 to ‘‘1’’.
Set the channel used for A/D conversion to the input mode by using port mode
registers 2 (PM2).
Do not set the pin set by ADPC as digital I/O by analog input channel specification
register (ADS).
When using all ANI0/P20 to ANI7/P27 pins as digital I/O (D), the setting can be done
by ADPC4 to ADPC0 = either 01000 or 10000.
P20/ANI0 to P27/ANI7 are set as analog inputs in the order of P27/ANI7, …,
P20/ANI0 by the A/D port configuration register (ADPC). When using P20/ANI0 to
P27/ANI7 as analog inputs, start designing from P27/ANI7.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
REF
for the voltage to be applied to the AV
Cautions
REF
pin when using port 2 as
p.101
p.101
p.107
p.109
p.109
p.110
p.110
p.117
p.120
p.124
p.127
p.132
p.132
p.132
p.132
827
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