UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 831

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock
generator
Function
OSTS:
Oscillation
stabilization time
select register
CKC: System
clock control
register
PER0: Peripheral
enable registers
0
OSMC:
Operation speed
mode control
register
HIOTRM:
Internal high-
speed oscillator
trimming register
Details of
Function
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than or equal to the count value which is to be checked by the OSTC register.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
• If the STOP mode is entered and then released while the internal high-speed
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
Be sure to set bit 3 to 1.
The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and
peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to
peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer) is also changed at the same time.
peripheral function when changing the CPU/peripheral operating hardware clock.
If the peripheral hardware clock is used as the subsystem clock, the operations of the
A/D converter and IIC0 are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
Be sure to clear bits 1 and 6 of PER0 register to 0.
OSMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing f
• Operating the DMA controller.
The CPU waits when “1” is written to the FSEL flag.
Interrupt requests issued during a wait will be suspended.
The wait time is 16.6
f
while the CPU is waiting.
To increase f
more clocks have elapsed.
Flash memory can be used at a frequency of 10 MHz or lower if FSEL is 1.
The frequency will vary if the temperature and V
adjustment.
Moreover, if the HIOTRM register is set to any value other than the initial value (10H),
the oscillation accuracy of the internal high-speed oscillation clock may exceed 8
MHz±5%, depending on the subsequent temperature and V
HIOTRM register setting. When the temperature and V
adjustment must be executed regularly or before the frequency accuracy is required.
IH
subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
/2. However, counting the oscillation stabilization time of f
well
APPENDIX B LIST OF CAUTIONS
as
User’s Manual U17854EJ9V0UD
CLK
CHAPTER
to 10 MHz or higher, set FSEL to “1”, then change f
μ
s to 18.5
27
μ
s when f
ELECTRICAL
CLK
Cautions
to a clock other than f
CLK
= f
IH
DD
, and 33.3
SPECIFICATIONS
pin voltage change after accuracy
DD
Consequently, stop each
voltage change, accuracy
μ
s to 36.9
IH
DD
.
X
voltage change, or
can continue even
CLK
μ
(STANDARD
s when f
after two or
CLK
=
p.148
p.148
p.150
p.150
p.150
pp.151,
152
p.153
p.153
p.153
p.153
p.153
p.154
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