UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 833

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Controlling
high-speed
system
clock
Controlling
internal
high-speed
oscillation
clock
Subsystem
clock
control
CPU clock
status
transition
Timer
array unit
Function
External main
system clock
High-speed
system clock
Internal high-
speed oscillation
clock
XT1/P123,
XT2/P124
Subsystem clock
TCR0n:
Timer/counter
register 0n
TDR0n: Timer
data register 0n
PER0:
Peripheral
enable register 0
Details of
Function
−
If switching the CPU/peripheral hardware clock from the high-speed system clock to
the internal high-speed oscillation clock after restarting the internal high-speed
oscillation clock, do so after 10
Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 27 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A)
GRADE PRODUCTS)).
Be sure to clear bits 1 and 6 of PER0 register to 0.
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition,
stop peripheral hardware that is operating on the high-speed system clock.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed
for 10
Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition,
stop peripheral hardware that is operating on the internal high-speed oscillation
clock.
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
When the subsystem clock is used as the CPU clock, the subsystem clock is also
supplied to the peripheral hardware (except the real-time counter, clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D
converter and IIC0 are not guaranteed.
peripheral hardware, refer to the chapters describing the various peripheral hardware
as
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time.
procedure when oscillating the X1 clock or 5.6.1 (2) Example of setting procedure
when using the external main system clock.
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
The subsystem clock oscillation cannot be stopped using the STOP instruction.
Set the clock after the supply voltage has reached the operable voltage of the clock
to be set (see CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
The count value is not captured to TDR0n even when TCR0n is read.
TDR0n does not perform a capture operation even if a capture trigger is input, when
it is set to the compare function.
When setting the timer array unit, be sure to set TAU0EN = 1 first. If TAU0EN = 0,
writing to a control register of the timer array unit is ignored, and all read values are
default values (except for timer input select register 0 (TIS0), input switch control
register (ISC), noise filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4
(PM0, PM1, PM3, PM4), and port registers 0, 1, 3, 4 (P0, P1, P3, P4)).
Be sure to clear bit 1, 6 of the PER0 register to 0.
well
μ
APPENDIX B LIST OF CAUTIONS
s.
as
User’s Manual U17854EJ9V0UD
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting
CHAPTER
27
μ
s or more have elapsed.
ELECTRICAL
Cautions
For the operating characteristics of the
SPECIFICATIONS
(STANDARD
pp.173,
174, 176
p.165
p.166
p.167
p.168
p.169
p.169
pp.169,
170
p.169
p.170
p.170
p.185
p.187
p.189
p.189
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