UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 835

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Operation of
timer array
unit as
independent
channel
Operation
of plural
channels of
timer array
unit
Timer
array unit
Function
Channel output
(TO0n pin)
operation
Collective
manipulation of
TO0n bits
Input pulse
interval
measurement
Input signal
high-/low-level
width
measurement
PWM function
One-shot pulse
output function
Details of
Function
When TOE0n = 1, even if the output by timer interrupt of each timer (INTTM0n)
contends with writing to TO0n, output is normally done to TO0n pin.
The timing of loading of TDR0n of the master channel is different from that of TDR0m
of the slave channel. If TDR0n and TDR0m are rewritten during operation, therefore,
an illegal waveform is output. Rewrite the TDR0n after INTTM0n is generated and
the TDR0m after INTTM0m is generated.
(2) Default level of TO0n pin and output level after timer operation start
The following figure shows the TO0n pin output level transition when writing has
been done in the state of TOE0n = 0 before port output is enabled and TOE0n = 1 is
set after changing the default level.
(a) When operation starts with TOM0n = 0 setting (toggle output)
(b) When operation starts with TOM0n = 1 setting (combination operation mode
(3) Operation of TO0n pin in combination operation mode (TOM0n = 1)
(a) When TOL0n setting has been changed during timer operation
(b) Set/reset timing
The TI0k pin input is sampled using the operating clock selected with the CKS0n bit
of the TMR0n register, so an error equal to the number of operating clocks occurs.
The TI0k pin input is sampled using the operating clock selected with the CKS0n bit
of the TMR0n register, so an error equal to the number of operating clocks occurs.
To rewrite both TDR0n of the master channel and TDR0m of the slave channel, a
write access is necessary two times. The timing at which the values of TDR0n and
TDR0m are loaded to TCR0n and TRC0m is upon occurrence of INTTM0n of the
master channel. Thus, when rewriting is performed split before and after occurrence
of INTTM0n of the master channel, the TO0m pin cannot output the expected
waveform. To rewrite both TDR0n of the master and TDR0m of the slave, therefore,
be sure to rewrite both the registers immediately after INTTM0n is generated from
the master channel.
The setting of TOL0n is invalid when TOM0n = 0. When the timer operation
starts after setting the default level, the toggle signal is generated and the output
level of TO0n pin is reversed.
(PWM output))
When TOM0n = 1, the active level is determined by TOL0n setting.
When the TOL0n setting has been changed during timer operation, the setting
becomes valid at the generation timing of TO0n change condition. Rewriting
TOL0n does not change the output level of TO0n. The following figure shows
the operation when the value of TOL0n has been changed during timer operation
(TOM0n = 1).
To realize 0%/100% output at PWM output, the TO0n pin/TO0n set timing at
master channel timer interrupt (INTTM0n) generation is delayed by 1 count clock
by the slave channel.
If the set condition and reset condition are generated at the same time, a higher
priority is given to the latter.
Figure 6-29 shows the set/reset operating statuses where the master/slave
channels are set as follows.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
Cautions
pp.211,
212
pp.212,
213
p.215
p.232
p.236
p.240
p.247
833
Page
(9/33)