UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 836

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

834
Operation
of
channels
of
array unit
Real-time
counter
Function
plural
timer
HOUR: Hour
count register
WEEK: Week
count register
Multiple PWM
output function
PER0: Peripheral
enable register 0
RTCC0: Real-
time counter
control register 0
RTCC1: Real-
time counter
control register 1
RTCC2: Real-
time counter
control register 2
RSUBC: Sub-
count register
ALARMWM:
Alarm minute
register
ALARMWH:
Alarm hour
register
Reading/writing
real-time counter
Details of
Function
To rewrite both TDR0n of the master channel and TDR0p of the slave channel 1, write
access is necessary at least twice. Since the values of TDR0n and TDR0p are loaded
to TCR0n and TCR0p after INTTM0n is generated from the master channel, if
rewriting is performed separately before and after generation of INTTM0n from the
master channel, the TO0p pin cannot output the expected waveform. To rewrite both
TDR0n of the master and TDR0p of the slave, be sure to rewrite both the registers
immediately after INTTM0n is generated from the master channel (This applies also to
TDR0q of the slave channel 2) .
When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (f
time counter is ignored, and, even if the register is read, only the default value is read.
If RCLOE0 and RCLOE1 are changed when RTCE = 1, glitches may occur in the
32.768 kHz and 1 Hz output signals.
The RIFG and WAFG flags may be cleared when the RTCC1 register is written by
using a 1-bit manipulation instruction. Use, therefore, an 8-bit manipulation instruction
in order to write to the RTCC1 register. To prevent the RIFG and WAFG flags from
being cleared during writing, disable writing by setting “1” to the corresponding bit.
When the value may be rewritten because the RIFG and WAFG flags are not being
used, the RTCC1 register may be written by using a 1-bit manipulation instruction.
Change ICT2, ICT1, and ICT0 when RINTE = 0.
When the output from RTCDIV pin is stopped, the output continues after a maximum
of two clocks of f
output is stopped immediately after entering the high level, a pulse of at least one
clock width of f
After the real-time counter starts operating, the output width of the RTCDIV pin may
be shorter than as set during the first interval period.
When a correction is made by using the SUBCUD register, the value may become
8000H or more.
This register is also cleared by reset effected by writing the second count register.
The value read from this register is not guaranteed if it is read during operation,
because a value that is changing is read.
Bit 5 (HOUR20) of HOUR indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
The value corresponding to the month count register or the day count register is not
stored in the week count register automatically.After reset release, set the week count
register as follow.
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the
range is set, the alarm is not detected.
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a
value outside the range is set, the alarm is not detected.
Bit 5 (WH20) of ALARMWH indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within
1 second.
Be sure to clear bit 1, 6 of the PER0 register to 0.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
XT
XT
may be generated.
SUB
and enters the low level. While 512 Hz is output, and when the
) is stable. If RTCEN = 0, writing to a control register of the real-
Cautions
p.254
p.264
p.264
p.265
p.267
p.268
p.268
p.268
p.269
p.269
p.269
p.270
p.273
p.276
p.276
p.276
pp.280,
281
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