UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 838

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

836
Watchdog
timer
Clock
output/
buzzer
output
controller
A/D
converter
Function
Setting interval
interrupt
CKS0, CKS1:
Clock output
select registers
0, 1
PER0:
Peripheral
enable register 0
ADM: A/D
converter mode
register
A/D conversion
time selection
(2.7 V ≤ AV
5.5 V)
A/D conversion
time selection
(2.3 V ≤ AV
5.5 V)
ADCR: 10-bit
A/D conversion
result register
ADCRH: 8-bit
A/D conversion
result register
Details of
Function
REF
REF
≤
≤
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU
starts operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing a
reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
Change the output clock after disabling clock output (PCLOEn = 0).
If the selected clock (f
becomes undefined.
When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0,
writing to a control register of the A/D converter is ignored, and, even if the register is
read, only the default value is read (except for port mode registers 2 (PM2)).
Be sure to clear bits 1, 6 of the PER0 register to 0.
A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to
values other than the identical data.
Set the conversion times with the following conditions.
Conventional-specification products (
• 4.0 V ≤ AV
• 2.7 V ≤ AV
Functionally expanded products (
• 4.0 V ≤ AV
• 2.7 V ≤ AV
Set the conversion times with the following conditions.
• 4.0 V ≤ AV
• 2.7 V ≤ AV
• 2.3 V ≤ AV
When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D
conversion once (ADCS = 0) beforehand.
Change LV1 and LV0 from the default value, when 2.3 V ≤ AV
The above conversion time does not include clock frequency errors. Select
conversion time, taking clock frequency errors into consideration.
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents
of ADCR may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents
of ADCRH may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
REF
REF
REF
REF
REF
REF
REF
≤ 5.5 V: f
< 4.0 V: f
≤ 5.5 V: f
< 4.0 V: f
≤ 5.5 V: f
< 4.0 V: f
< 2.7 V: f
MAIN
AD
AD
AD
AD
AD
AD
AD
or f
= 0.6 to 3.6 MHz
= 0.33 to 3.6 MHz
= 0.6 to 3.6 MHz
= 0.6 to 1.8 MHz
= 0.33 to 1.8 MHz
= 0.6 to 1.8 MHz
= 0.6 to 1.44 MHz
SUB
) stops during clock output (PCLOEn = 1), the output
μ
PD78F114xA)
μ
Cautions
PD78F114x)
REF
< 2.7 V.
p.295
p.298
p.298
p.303
p.303
p.304
p.305
p.306
p.306
p.306
p.306
p.308
p.309
(12/33)
Page