UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 844

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

842
Simplified
I
IIC20)
communi-
cation
Serial
interface
IIC0
2
C (IIC10,
Function
Address field
transmission
Data reception
Calculating
transfer rate
IIC0: IIC shift
register 0
PER0:
Peripheral
enable register 0
IICC0: IIC
control register 0
IICF0: IIC flag
register 0
IICX0: IIC
function
expansion
register 0
Setting transfer
clock
When STCEN =
0
Details of
Function
After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more
clocks have elapsed.
ACK is not output when the last data is received (NACK). Communication is then
completed by setting “1” to the ST02 bit to stop operation and generating a stop
condition.
Setting SDR02[15:9] = 0000000B is prohibited. Setting SDR02[15:9] = 0000001B or
more.
Do not write data to IIC0 during data transfer.
Write or read IIC0 only during the wait period. Accessing IIC0 in a communication
state other than during the wait period is prohibited. When the device serves as the
master, however, IIC0 can be written only once after the communication trigger bit
(STT0) is set to 1.
When setting serial interface IIC0, be sure to set IIC0EN to 1 first. If IIC0EN = 0,
writing to a control register of serial interface IIC0 is ignored, and, even if the register
is read, only the default value is read (except for port mode register 6 (PM6) and port
register 6 (P6)).
Be sure to clear bits 1 and 6 of PER0 register to 0.
The start condition is detected immediately after I
while the SCL0 line is at high level and the SDA0 line is at low level. Immediately
after enabling I
manipulation instruction.
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1
during the ninth clock and wait is canceled, after which TRC0 is cleared and the
SDA0 line is set to high impedance.
Write to STCEN only when the operation is stopped (IICE0 = 0).
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE0 = 0).
Determine the transfer clock frequency of I
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0
(IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
Determine the transfer clock frequency of I
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0
(IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
IImmediately after I
(IICBSY (bit 6 of IICF0) =1) is recognized regardless of the actual bus status. When
changing from a mode in which no stop condition has been detected to a master
device communication mode, first generate a stop condition to release the bus, then
perform master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.Use the following
sequence for generating a stop condition.
<1> Set IIC clock select register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
2
C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory
2
C operation is enabled (IICE0 = 1), the bus communication status
Cautions
2
2
C by using CLX0, SMC0, CL01, and
C by using CLX0, SMC0, CL01, and
2
C is enabled to operate (IICE0 = 1)
p.453
p.462
p.464
p.476
p.476
p.479
p.479
p.480
p.483
p.487
p.487
p.487
p.489
p.495
p.509
(18/33)
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