UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 845

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial
interface
IIC0
DMA
controller
Function
When STCEN =
1
If other I
communications
are already in
progress
Setting transfer
clock frequency
STT0, SPT0:
Bits 1, 0 of IIC
control register 0
(IICC0)
Reserving
transmission
DBCn: DMA
byte count
register n
DRCn: DMA
operation control
register n
Holding DMA
transfer pending
by DWAITn
Forced
Termination of
DMA Transfer
Details of
Function
2
C
Immediately after I
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to
confirm that the bus has been released, so as to not disturb other communications.
IIf I
progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I
recognizes that the SDA0 pin has gone low (detects a start condition). If the value on
the bus at this time can be recognized as an extension code, ACK is returned, but
this interferes with other I
sequence.<1>
interrupt request signal (INTIIC0) when the stop condition is detected.
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after
Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0
of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To
change the transfer clock frequency, clear IICE0 to 0 once.
Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before
they are cleared to 0 is prohibited.
When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IIC0 after the interrupt request is generated. Unless
the interrupt is generated when the stop condition is detected, the device stops in the
wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0)
is detected by software.
Be sure to clear bits 15 to 10 to “0”.
If the general-purpose register is specified or the internal RAM space is exceeded as
a result of continuous transfer, the general-purpose register or SFR space are written
or read, resulting in loss of data in these spaces. Be sure to set the number of times
of transfer that is within the internal RAM space.
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is
terminated without waiting for generation of the interrupt (INTDMAn) of DMAn,
therefore, set DSTn to 0 and then DENn to 0 (for details, refer to 14.5.5 Forcible
termination by software).
When DMA transfer is held pending while using both DMA channels, be sure to hold
the DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1).
If the DMA transfer of one channel is executed while that of the other channel is held
pending, DMA transfer might not be held pending for the latter channel.
In example 3, the system is not required to wait two clock cycles after DWAITn is set
to 1. In addition, the system does not have to wait two clock cycles after clearing
DSTn to 0, because more than two clock cycles elapse from when DSTn is cleared to
0 to when DENn is cleared to 0.
2
C operation is enabled and the device participates in communication already in
setting IICE0 to 1), to forcibly disable detection.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
2
Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an
C operation is enabled (IICE0 = 1), the bus released status
2
C communications. To avoid this, start I
Cautions
2
C.
2
C in the following
2
C
p.509
p.509
p.509
p.509
p.509
p.552
p.552
p.556
p.570
p.572
843
(19/33)
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