UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 860

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UPD78F1146AGB-GAH-AX

Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1146AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
C.1 Major Revisions in This Edition
Remark “Classification” in the above table classifies revisions as follows.
858
Throughout
CHAPTER 1 OUTLINE
p.17
CHAPTER 3 CPU ARCHITECTURE
pp.58 to 62
p.64
CHAPTER 5 CLOCK GENERATOR
pp.141, 142
p.143
p.151
p.153
p.173
p.174
p.176
p.176
p.179
p.179
p.180
CHAPTER 6 TIMER ARRAY UNIT
p.191
p.199
p.200
p.206
CHAPTER 7 REAL-TIME COUNTER
p.261
p.263
p.265
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Addition of f
Change of description of AMPH bit in Figure 5-2. Format of Clock Operation Mode Control
Register (CMC)
Change of description of RTCEN bit in Figure 5-7. Format of Peripheral Enable Register (1/2)
Change of Caution 5 in Figure 5-8. Format of Operation Speed Mode Control Register
(OSMC)
Change of description of AMPH bit in Table 5-4. CPU Clock Transition and SFR Register
Setting Examples (1/4) (2) and addition of Remark
Change of description of AMPH bit in Table 5-4. CPU Clock Transition and SFR Register
Setting Examples (2/4) (4) and addition of Remark
Change of (9) CPU clock changing from subsystem clock (D) to high-speed system clock
(C) in Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
Change of (11) • STOP mode (H) set while CPU is operating with internal high-speed
oscillation clock (B) • STOP mode (I) set while CPU is operating with high-speed system
clock (C) in Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
Change of Table 5-6. Maximum Time Required for Main System Clock Switchover
Change of Table 5-8. Maximum Number of Clocks Required in Type 2
Change of Table 5-9. Maximum Number of Clocks Required in Type 3 and addition of Remark
Change of CKS0n bit in Figure 6-6. Format of Timer Mode Register 0n (TMR0n) (1/3)
Change of Figure 6-13. Start Timing (In One-count Mode)
Change of Figure 6-14. Start Timing (In Capture & One-count Mode)
Change of description of ISC1 and ISC0 bits in Figure 6-21. Format of Input Switch Control
Register (ISC)
Change of Table 7-1. Configuration of Real-Time Counter
Change of 7.3 Registers Controlling Real-Time Counter
Change of description of AMPM bit in Figure 7-3. Format of Real-Time Counter Control
Register 0 (RTCC0)
Change of status of (A) grade products of the expanded-specification products and 64-pin
plastic FBGA (6 × 6) package from under development to mass production
Change of 1.1 Differences Between Conventional-Specification Products (
Expanded-Specification Products (
Change of Figure 3-7 to Figure 3-11 Correspondence Between Data Memory and
Addressing
Addition of Caution to 3.2.1 (3) Stack pointer (SP)
MAINC
to Figure 5-1. Block Diagram of Clock Generator and Remark
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
μ
PD78F114xA)
Description
μ
PD78F114x) and
Classification
(b), (d)
(a)
(a)
(a)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(1/5)

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