UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 861

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark “Classification” in the above table classifies revisions as follows.
CHAPTER 7 REAL-TIME COUNTER (continuation)
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p.275
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CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
p.299
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CHAPTER 10 A/D CONVERTER
p.304
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p.328
p.332
CHAPTER 11 SERIAL ARRAY UNIT
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(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Change of description of (7) Minute count register (MIN)
Change of description of (8) Hour count register (HOUR)
Addition of description of DEV bit to Figure 7-14. Format of Watch Error Correction Register
(SUBCUD)
Addition of 7.3 (17) Port mode register 1, 3 (PM1, PM3)
Change of Figure 7-19. Procedure for Starting Operation of Real-Time Counter and addition of
Note
Addition of Caution to 7.4.5 1 Hz output of real-time counter
Change of 7.4.6 32.768 kHz output of real-time counter
Change of 7.4.7 512 Hz, 16.384 kHz output of real-time counter
Change of Remark in 9.4.1 Operation as output pin
Change of Figure 9-4. Remote Control Output Application Example
Change of Table 10-2. Settings of ADCS and ADCE
Change of Figure 10-5. Timing Chart When A/D voltage Comparator Is Used
Change of 10.7 Cautions for A/D Converter (1) Operating current in STOP mode
Addition of 10.7 (13) Starting the A/D converter
Change of MDmn0 bit in Figure 11-6. Format of Serial Mode Register mn (SMRmn) (2/2)
Addition of Note to Figure 11-7. Format of Serial Communication Operation Setting Register
mn (SCRmn) (2/3)
Addition of Caution to Figure 11-8. Format of Serial Data Register mn (SDRmn)
Change of description of Figure 11-17. Format of Input Switch Control Register (ISC)
Change of interrupt in 11.5.2 Master reception
Change of Figure 11-32. Example of Contents of Registers for Master Reception of 3-Wire
Serial I/O (CSI00, CSI10)
Change of Figure 11-35. Procedure for Resuming Master Reception
Change of Figure 11-37. Flowchart of Master Reception (in Single-Reception Mode)
Addition of Figure 11-38. Timing Chart of Master Reception (in Continuous Reception Mode)
(Type 1: DAP0n = 0, CKP0n = 0)
Addition of Figure 11-39. Flowchart of Master Reception (in Continuous Reception Mode)
Change of Figure 11-51. Procedure for Resuming Slave Transmission
Change of Figure 11-53. Flowchart of Slave Transmission (in Single-Transmission Mode)
Change of Figure 11-55. Flowchart of Slave Transmission (in Continuous Transmission
Mode)
Change of Figure 11-56. Example of Contents of Registers for Slave Reception of 3-Wire
Serial I/O (CSI00, CSI10)
Change of Figure 11-59. Procedure for Resuming Slave Reception
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
Description
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