UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 862

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark “Classification” in the above table classifies revisions as follows.
860
CHAPTER 11 SERIAL ARRAY UNIT (continuation)
p.406
p.408
p.409
p.411
p.413
p.415
p.431
p.434
p.436
p.450
p.451
p.456
p.459
p.464
p.464
p.467
CHAPTER 12 SERIAL INTERFACE IIC0
p.482
CHAPTER 14 DMA CONTROLLER
p.554
p.560
p.561
p.562
p.564
p.570
p.570
p.571
p.573
p.574
p.575
CHAPTER 15 INTERRUPT FUNCTIONS
p.579
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Change of Figure 11-61. Flowchart of Slave Reception (in Single-Reception Mode)
Addition of Caution to Figure 11-62. Example of Contents of Registers for Slave
Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI10)
Addition of Caution to Figure 11-63. Initial Setting Procedure for Slave Transmission/Reception
Change of Figure 11-65. Procedure for Resuming Slave Transmission/Reception and
addition of caution.
Change of Figure 11-67. Flowchart of Slave Transmission/Reception (in Single-
Transmission/Reception Mode) and addition of caution.
Change of Figure 11-69. Flowchart of Slave Transmission/Reception (in Continuous
Transmission/Reception Mode) and addition of caution.
Change of Figure 11-79. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART3) (1/2)
Change of Figure 11-82. Procedure for Resuming UART Reception
Change of Figure 11-84. Flowchart of UART Reception
Change of 11.7 Operation of Simplified I
Change of transfer rate in 11.7.1 Address field transmission
Change of transfer rate in 11.7.2 Data transmission
Change of error detection flag and transfer rate in 11.7.3 Data reception
Addition of Caution to 11.7.5 Calculating transfer rate
Change of Remark in 11.7.5 Calculating transfer rate
Addition of Figure 11-105. Processing Procedure in Case of Parity Error or Overrun Error
Change of description of STT0 bit in Figure 12-6. Format of IIC Control Register 0 (IICC0) (3/4)
Addition of Note to Figure 14-4. Format of DMA Mode Control Register n (DMCn) (1/2)
Change of description in 14.5.1 CSI consecutive transmission
Change of description in Figure 14-7. Setting Example of CSI Consecutive Transmission
Addition of 14.5.2 CSI master reception
Addition of 14.5.3 CSI transmission/reception
Change of description in 14.5.6 Holding DMA transfer pending by DWAITn
Addition of Caution to Figure 14-12. Example of Setting for Holding DMA Transfer Pending
by DWAITn
Change of 14.5.7 Forced termination by software
Change of (1) Priority of DMA in 14.6 Cautions on Using DMA Controller
Change of (2) DMA response time in 14.6 Cautions on Using DMA Controller
Change of description in (4) DMA pending instruction in 14.6 Cautions on Using DMA
Controller
Change of (B) External maskable interrupt (INTPn) in Figure 15-1. Basic Configuration of
Interrupt Function
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
2
C (IIC10) Communication
Description
Classification
(b)
(b)
(b)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(3/5)