UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 869

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5th edition
Edition
Change of Figure 11-15 Format of Serial Output Register m (SOm)
Addition of Note to transfer rate
Change of transfer rate and Note in 11.4.4 Slave transmission
Change of transfer rate in 11.4.5 Slave reception
Change of transfer rate in 11.4.6 Slave transmission/reception
Change of Note in 11.4.7 (2)
Addition of setting and Note to Table 11-2 Operating Clock Selection
Change of transfer rate and addition of Note
Change of Figure 11-66 Example of Contents of Registers for UART
Transmission of UART
(UART0, UART1, UART3)
Change of Figure 11-74 Example of Contents of Registers for UART Reception
of UART (UART0, UART1, UART3)
Change of Figure 11-77 Procedure for Resuming UART Reception
Addition of setting and Note to Table 11-3 Operating Clock Selection
Change of Figure 11-92 Flowchart of Data Transmission
Addition of setting and Note to Table 11-4 Operating Clock Selection
Change of Figure 14-9 Example of Setting for UART Consecutive Reception + ACK
Transmission
Additions of description to 14.6 (4) DMA pending instruction
Change of Figure 17-4 HALT Mode Release by Reset
Change of Figure 17-7 STOP Mode Release by Reset
Change of reset processing in Figure 18-2 Timing of Reset by RESET Input
Change of reset processing in Figure 18-4 Timing of Reset in STOP Mode by
RESET Input
Change of Caution 2 in Figure 18-5 Format of Reset Control Flag Register
(RESF)
Change of Figure 19-2 Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (1/2)
Change of Figure 19-2 Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (2/2) and addition of Note
Change of Figure 19-3 Example of Software Processing After Reset Release
Change of Note 4 in Figure 20-2 Format of Low-Voltage Detection Register
(LVIM) and addition of Caution 3
Change of Caution 2 in Figure 20-3 Format of Low-Voltage Detection Level
Select Register (LVIS)
Change of <5> in 20.4.1 (1) (a)
Change of Note 2 in Figure 20-5 Timing of Low-Voltage Detector Internal Reset
Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Change of description and Caution in 20.4.1 (1) (b)
Change of Figure 20-6 Timing of Low-Voltage Detector Internal Reset Signal
Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 0) and Note
Change of <4> in 20.4.1 (2)
Change of Figure 20-7 Timing of Low-Voltage Detector Internal Reset Signal
Generation (Bit: LVISEL = 1) and Note 2
Change of <5> in 20.4.2 (1)
APPENDIX C REVISION HISTORY
User’s Manual U17854EJ9V0UD
Description
CHAPTER 11 SERIAL
ARRAY UNIT
CHAPTER 14 DMA
CONTROLLER
CHAPTER 17
STANDBY FUNCTION
CHAPTER 18 RESET
FUNCTION
CHAPTER 19 POWER-
ON-CLEAR CIRCUIT
CHAPTER 20 LOW-
VOLTAGE DETECTOR
Chapter
(5/15)
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