UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 872

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

870
6th edition
Edition
Change of Figure 11-64. Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode)
Change of Figure 11-66. Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 11-67. Flowchart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Transfer data length in 11.6.2 UART reception
Change of Figure 11-80. Timing Chart of UART Reception
Change of Transfer data length in 11.6.3 LIN transmission
Change of Transfer data length in 11.6.4 LIN reception
Change of Figure 11-89. Initial Setting Procedure for Address Field
Transmission
Change of Figure 11-90. Timing Chart of Address Field Transmission
Change of Figure 11-91. Flowchart of Address Field Transmission
Change of Figure 11-92. Example of Contents of Registers for Data
Transmission of Simplified I
Change of Figure 11-94. Flowchart of Data Transmission
Change of Figure 11-95. Example of Contents of Registers for Data Reception of
Simplified I
Change of Figure 11-96. Timing Chart of Data Reception
Change of Figure 11-97. Flowchart of Data Reception and addition of Caution
Change of Figure 11-99. Flowchart of Stop Condition Generation
Addition of 11.9 Relationship Between Register Settings and Pins
Addition of Note to Figure 17-3. HALT Mode Release by Interrupt Request
Generation
Addition of Note to Figure 17-5. Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Addition of Note to Figure 17-6. STOP Mode Release by Interrupt Request
Generation
Change of description in (4)
Change of Figure 18-2. Timing of Reset by RESET Input
Change of Figure 18-4. Timing of Reset in STOP Mode by RESET Input
Change of Pin No. in Table 23-1. Wiring Between 78K0R/KE3 and Dedicated
Flash Memory Programmer and addition of Note
Change of 23.4.1 FLMD0 pin
Change of Remark in 23.8 Flash Memory Programming by Self-Programming
Change of Figure 23-10. Flow of Self Programming (Rewriting Flash Memory),
and addition of Remark
Change of Table 15-1. Interrupt Source List
Change of 25.3 BCD Correction Circuit Operation
2
C (IIC10) and addition of Note
APPENDIX C REVISION HISTORY
2
C (IIC10) and addition of Note
User’s Manual U17854EJ9V0UD
Description
CHAPTER 11 SERIAL
ARRAY UNIT
CHAPTER 15
INTERRUPT
FUNCTIONS
CHAPTER 17
STANDBY FUNCTION
CHAPTER 18 RESET
FUNCTION
CHAPTER 23 FLASH
MEMORY
CHAPTER 25 BCD
CORRECTION CIRCUIT
Chapter
(8/15)