UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet
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Preliminary User’s Manual V850ES/JG3-L 32-bit Single-Chip Microcontrollers Hardware μ PD70F3737 μ PD70F3738 Document No. U18953EJ1V0UD00 (1st edition) Date Published December 2007 N 2007 Printed in Japan ...
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Preliminary User’s Manual U18953EJ1V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America. EEPROM is a trademark of ...
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The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/JG3-L and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JG3-L ...
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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG3-L V850ES Architecture User’s Manual V850ES/JG3-L Hardware User’s Manual Documents related to development tools QB-V850ESSX2 In-Circuit ...
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CHAPTER 1 INTRODUCTION .................................................................................................................19 1.1 General .....................................................................................................................................19 1.2 Features....................................................................................................................................21 1.3 Application Fields ...................................................................................................................22 1.4 Ordering Information ..............................................................................................................22 1.5 Pin Configuration (Top View) .................................................................................................23 1.6 Function Block Configuration................................................................................................26 1.6.1 Internal block diagram ............................................................................................................... 26 1.6.2 Internal units .............................................................................................................................. 27 CHAPTER 2 ...
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Port DH ....................................................................................................................................119 4.3.11 Port DL ....................................................................................................................................121 4.4 Block Diagrams..................................................................................................................... 124 4.5 Port Register Settings When Alternate Function Is Used ................................................ 154 4.6 Cautions ................................................................................................................................ 162 4.6.1 Cautions on setting port pins ...................................................................................................162 4.6.2 Cautions on bit manipulation instruction ...
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Overview.................................................................................................................................207 7.2 Functions ...............................................................................................................................207 7.3 Configuration .........................................................................................................................208 7.4 Registers ................................................................................................................................210 7.5 Operation................................................................................................................................222 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............................................................. 223 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001)................................................. 233 7.5.3 External trigger pulse ...
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Functions............................................................................................................................... 412 11.2 Configuration ........................................................................................................................ 413 11.3 Registers ............................................................................................................................... 414 11.4 Operation............................................................................................................................... 416 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 417 12.1 Function................................................................................................................................. 417 12.2 Configuration ........................................................................................................................ 418 12.3 Registers ............................................................................................................................... 420 12.4 Operation............................................................................................................................... 422 12.5 Usage ..................................................................................................................................... 423 12.6 ...
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SBF reception.......................................................................................................................... 483 15.6.5 UART transmission.................................................................................................................. 484 15.6.6 Continuous transmission procedure ........................................................................................ 485 15.6.7 UART reception ....................................................................................................................... 487 15.6.8 Reception errors ...................................................................................................................... 488 15.6.9 Parity types and operations ..................................................................................................... 490 15.6.10 Receive data noise filter .......................................................................................................... 491 15.7 Dedicated ...
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Addresses................................................................................................................................577 17.6.3 Transfer direction specification ................................................................................................578 17.6.4 ACK .........................................................................................................................................579 17.6.5 Stop condition ..........................................................................................................................580 17.6.6 Wait state.................................................................................................................................581 17.6.7 Wait state cancellation method ................................................................................................583 2 17 Interrupt Request Signals (INTIICn) .............................................................................. 584 17.7.1 Master device operation...........................................................................................................584 17.7.2 Slave device ...
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Maskable Interrupts ..............................................................................................................662 19.3.1 Operation................................................................................................................................. 662 19.3.2 Restore.................................................................................................................................... 664 19.3.3 Priorities of maskable interrupts .............................................................................................. 665 19.3.4 Interrupt control register (xxICn) .............................................................................................. 669 19.3.5 Interrupt mask registers (IMR0 to IMR3)........................................................................ 671 19.3.6 In-service priority register (ISPR)............................................................................................. ...
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Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode................................................................... 717 21.8.1 Setting and operation status ....................................................................................................717 21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode ..........................................................720 CHAPTER 22 RESET FUNCTIONS ..................................................................................................... 721 22.1 Overview................................................................................................................................ 721 22.2 Registers to Check Reset Source....................................................................................... 722 22.3 Operation............................................................................................................................... 723 22.3.1 Reset ...
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Flash memory control .............................................................................................................. 764 28.4.4 Selection of communication mode........................................................................................... 765 28.4.5 Communication commands ..................................................................................................... 766 28.4.6 Pin connection ......................................................................................................................... 767 28.5 Rewriting by Self Programming...........................................................................................771 28.5.1 Overview ................................................................................................................................. 771 28.5.2 Features .................................................................................................................................. 772 28.5.3 Standard self programming flow ...
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APPENDIX D INSTRUCTION SET LIST ............................................................................................. 851 D.1 Conventions .......................................................................................................................... 851 D.2 Instruction Set (in Alphabetical Order) .............................................................................. 854 18 Preliminary User’s Manual U18953EJ1V0UD ...
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The V850ES/JG3-L is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 General The V850ES/JG3 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions ...
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Generic Name Part Number Internal Flash memory memory RAM Memory Logical space space External memory area External bus interface Address bus: 18 Address data bus: 16 Multiplexed bus mode output supported 32 bits × 32 registers General-purpose register Clock Main ...
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Features Minimum instruction execution time (operating with main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 × 32 → 64): ...
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Clock generator: During main clock or subclock operation 7-level CPU clock (f Clock-through mode/PLL mode selectable Internal oscillation clock: 220 kHz (TYP.) Power-save functions: HALT/IDLE1/IDLE2/STOP/low-voltage STOP/subclock/sub-IDLE/ low-voltage subclock/low-voltage sub-IDLE mode 100-pin plastic LQFP (14 × 20) Package: 100-pin plastic LQFP ...
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Pin Configuration (Top View) 100-pin plastic LQFP (14 × 20) µ PD70F3737GF-GAS-AX P71/ANI1 P70/ANI0 AV REF0 AV SS P10/ANO0 P11/ANO1 AV REF1 PDH4/A20 PDH5/A21 Note 1 FLMD0 V DD Note 2 REGC RESET XT1 XT2 ...
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LQFP (fine pitch) (14 × 14) µ PD70F3737GC-UEU- REF0 P10/ANO0 P11/ANO1 REF1 PDH4/A20 6 PDH5/A21 7 Note 1 FLMD0 Note 2 REGC ...
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Pin names A0 to A21: Address bus AD0 to AD15: Address/data bus ADTRG: A/D trigger input Analog input ANI0 to ANI11: ANO0, ANO1: Analog output ASCKA0: Asynchronous serial clock ASTB: Address strobe Analog reference voltage REF0 ...
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Function Block Configuration 1.6.1 Internal block diagram NMI INTC INTP0 to INTP7 16-bit timer/ TIQ00 to TIQ03 counter Q: TOQ00 to TOQ03 1 ch TIP00 to TIP50, 16-bit timer/ TIP01 to TIP51 counter P: TOP00 to TOP50 ...
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Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates ...
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Ports The following general-purpose port functions and control pin functions are available. Port I/O P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset P1 2-bit I/O D/A converter analog output P3 10-bit I/O External interrupt, serial interface, ...
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List of Pin Functions The names and functions of the pins in the V850ES/JG3-L are described below. There are three types of pin I/O buffer power supplies: AV power supplies and the pins is described below. Power Supply AV ...
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Port pins Pin Name Pin No. I Port 0 P02 19 17 I/O 5-bit I/O port P03 20 18 Input/output can be specified in 1-bit units. P04 21 19 N-ch open-drain output can be specified in 1-bit ...
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Pin Name Pin No. I P70 2 100 I/O Port 7 12-bit I/O port P71 1 99 Input/output can be specified in 1-bit units. P72 100 98 P73 99 97 P74 98 96 P75 97 95 P76 96 ...
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Pin Name Pin No. I PDH0 89 87 I/O Port DH 6-bit I/O port PDH1 90 88 Input/output can be specified in 1-bit units. PDH2 61 59 PDH3 62 60 PDH4 8 6 PDH5 9 7 PDL0 73 ...
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Non-port pins Pin Name Pin No. I Output Address bus for external memory (when using separate bus N-ch open-drain output selectable tolerant ...
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Pin Name Pin No. I ADTRG 20 18 Input A/D converter external trigger input tolerant. ANI0 2 100 Input Analog voltage input for A/D converter ANI1 1 99 ANI2 100 98 ANI3 99 97 ANI4 98 ...
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Pin Name Pin No. I INTP0 20 18 Input External interrupt request input (maskable, analog noise elimination). INTP1 21 19 Analog noise elimination or digital noise elimination INTP2 22 20 selectable for INTP3 pin. INTP3 ...
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Pin Name Pin No. I SCKB0 26 24 I/O Serial clock I/O (CSIB0 to CSIB4) N-ch open-drain output selectable. SCKB1 tolerant. SCKB2 44 42 SCKB3 57 55 SCKB4 29 27 SCL00 38 36 I/O ...
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Pin Name Pin No. I TIP00 29 27 External event count input/capture trigger input/external Input trigger input (TMP0 tolerant. TIP01 30 28 Capture trigger input (TMP0 tolerant. TIP10 31 29 External event count input/capture ...
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Pin Name Pin No. I TOP00 29 27 Output Timer output (TMP0) N-ch open-drain output selectable tolerant. TOP01 30 28 TOP10 31 29 Timer output (TMP1) N-ch open-drain output selectable tolerant. TOP11 32 30 ...
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Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Pin Name When Power During Reset Is Turned (Except When Note 1 On Power Is Turned On) ...
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Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins Pin Alternate Function P02 NMI P03 INTP0/ADTRG P04 INTP1 P05 INTP2/DRST P06 INTP3 P10, P11 ANO0, ANO1 P30 TXDA0/SOB4 P31 RXDA0/INTP7/SIB4 P32 ASCKA0/SCKB4/TIP00 P33 TIP01/TOP01 P34 ...
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Pin Alternate Function P90 A0/KR6/TXDA1/SDA02 P91 A1/KR7/RXDA1/SCL02 P92 A2/TIP41/TOP41 P93 A3/TIP40/TOP40 P94 A4/TIP31/TOP31 P95 A5/TIP30/TOP30 P96 A6/TIP21/TOP21 P97 A7/SIB1/TIP20/TOP20 P98 A8/SOB1 P99 A9/SCKB1 P910 A10/SIB3 P911 A11/SOB3 P912 A12/SCKB3 P913 A13/INTP4 P914 A14/INTP5/TIP51/TOP51 P915 A15/INTP6/TIP50/TOP50 PCM0 WAIT PCM1 CLKOUT PCM2 ...
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Pin Alternate Function − AV REF0 − AV REF1 − − − − FLMD0 − REGC − RESET − − − X1 − X2 − XT1 − XT2 GF: 100-pin ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5 EV Data Output disable Input enable Type 10-D Data Open drain Output disable Note Input enable Type 10-G Data Open drain Output disable Input enable Note Hysteresis characteristics are not ...
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Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P10/ANO0 pin • P11/ANO1 pin • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin CHAPTER 2 PIN FUNCTIONS Preliminary User’s Manual U18953EJ1V0UD 45 ...
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The CPU of the V850ES/JG3-L is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time (operating with main clock (f Memory space Program (physical ...
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CPU Register Set The registers of the V850ES/JG3-L can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program ...
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Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data variable ...
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System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. ...
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Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to ...
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NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those ...
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Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this ...
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Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a ...
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Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the ...
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Operation Modes The V850ES/JG3-L has the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the ...
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Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) ...
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Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a ...
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Memory map The areas shown below are reserved in the V850ES/JG3-L. Figure 3-2. Data Memory Map (Physical Addresses (64 KB ...
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...
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Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (128 KB) 128 KB are allocated to addresses 00000000H to 0001FFFFH in the Accessing addresses 00020000H to 000FFFFFH is prohibited. ...
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Internal RAM area are reserved as the internal RAM area. (a) Internal RAM (8 KB are allocated to addresses 03FFD000H to 03FFEFFFH of the Accessing addresses 03FF0000H to 03FFCFFFH is prohibited. Figure 3-6. ...
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On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Physical address space ...
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Recommended use of address space The architecture of the V850ES/JG3-L requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ...
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Data space With the V850ES/JG3-L, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25 26-bit address is sign-extended to 32 bits and ...
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Figure 3-9. Recommended Memory Map Program space ...
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Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H FFFFF006H Port DH register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF024H Port DL mode register FFFFF024H ...
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Address Function Register Name FFFFF0D2H DMA addressing control register 1 FFFFF0D4H DMA addressing control register 2 FFFFF0D6H DMA addressing control register 3 FFFFF0E0H DMA channel control register 0 FFFFF0E2H DMA channel control register 1 FFFFF0E4H DMA channel control register 2 ...
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Address Function Register Name FFFFF140H Interrupt control register FFFFF142H Interrupt control register FFFFF144H Interrupt control register FFFFF146H Interrupt control register FFFFF148H Interrupt control register FFFFF14AH Interrupt control register FFFFF14CH Interrupt control register FFFFF14EH Interrupt control register FFFFF150H Interrupt control register ...
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Address Function Register Name FFFFF214H A/D conversion result register 2 FFFFF215H A/D conversion result register 2H FFFFF216H A/D conversion result register 3 FFFFF217H A/D conversion result register 3H FFFFF218H A/D conversion result register 4 FFFFF219H A/D conversion result register 4H ...
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Address Function Register Name FFFFF40AH Port 5 register FFFFF40EH Port 7 register L FFFFF40FH Port 7 register H FFFFF412H Port 9 register FFFFF412H Port 9 register L FFFFF413H Port 9 register H FFFFF420H Port 0 mode register FFFFF422H Port 1 ...
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Address Function Register Name FFFFF543H TMQ0 I/O control register 1 FFFFF544H TMQ0 I/O control register 2 FFFFF545H TMQ0 option register 0 FFFFF546H TMQ0 capture/compare register 0 FFFFF548H TMQ0 capture/compare register 1 FFFFF54AH TMQ0 capture/compare register 2 FFFFF54CH TMQ0 capture/compare register ...
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Address Function Register Name FFFFF5D0H TMP4 control register 0 FFFFF5D1H TMP4 control register 1 FFFFF5D2H TMP4 I/O control register 0 FFFFF5D3H TMP4 I/O control register 1 FFFFF5D4H TMP4 I/O control register 2 FFFFF5D5H TMP4 option register 0 FFFFF5D6H TMP4 capture/compare ...
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Address Function Register Name FFFFF82CH PLL control register FFFFF82EH CPU operation clock status register FFFFF870H Clock monitor mode register FFFFF888H Reset source flag register FFFFF890H Low-voltage detection register FFFFF891H Low-voltage detection level select register FFFFF8B0H Prescaler mode register 0 FFFFF8B1H ...
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Address Function Register Name FFFFFC72H Port 9 function register FFFFFC72H Port 9 function register L FFFFFC73H Port 9 function register H FFFFFD00H CSIB0 control register 0 FFFFFD01H CSIB0 control register 1 FFFFFD02H CSIB0 control register 2 FFFFFD03H CSIB0 status register ...
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Address Function Register Name FFFFFD80H IIC shift register 0 FFFFFD82H IIC control register 0 FFFFFD83H Slave address register 0 FFFFFD84H IIC clock select register 0 FFFFFD85H IIC function expansion register 0 FFFFFD86H IIC status register 0 FFFFFD8AH IIC flag register ...
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Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JG3-L has the following seven special registers. • Power save control register (PSC) • Clock control register (CKC) ...
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Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in ...
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Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first ...
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System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After ...
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Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JG3-L. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After ...
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Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus ...
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Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before ...
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Features I/O ports: 84 • tolerant/N-ch open-drain output selectable: 31 (ports (P90 to P96)) Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JG3-L features a total of 84 I/O ports ...
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Port Configuration Item Control register Port n mode register (PMn CD, CM, CT, DH, DL) Port n mode control register (PMCn CM, CT, ...
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Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be ...
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Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, ...
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Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in ...
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Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate function ...
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Port 0 Port 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-4. Port 0 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port 0 mode register (PM0) After reset: FFH R/W PM0 1 PM06 PM0n 0 Output mode 1 Input mode (3) Port 0 mode control register (PMC0) After reset: 00H R/W PMC0 0 PMC06 PMC06 0 I/O port 1 INTP3 ...
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Port 0 function control register (PFC0) After reset: 00H R/W PFC0 0 0 PFC03 0 INTP0 input 1 ADTRG input (5) Port 0 function register (PF0) After reset: 00H R/W PF0 0 PF06 PF0n Control of normal output or ...
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Port 1 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name GF GC P10 5 3 ANO0 P11 ...
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Port 3 Port 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-6. Port 3 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port 3 register (P3) After reset: 0000H (output latch (P3H) 0 (P3L) P37 P3n 0 Outputs 0 1 Outputs 1 Remarks 1. The P3 register can be read or written in 16-bit units. However, when using the ...
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Port 3 mode control register (PMC3) After reset: 0000H 15 PMC3 (PMC3H) 0 (PMC3L) 0 PMC39 0 I/O port 1 RXDA2 input/SCL00 I/O PMC38 0 I/O port 1 TXDA2 output/SDA00 I/O PMC35 0 I/O port 1 TIP11 input/TOP11 output ...
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Port 3 function control register (PFC3) After reset: 0000H 15 PFC3 (PFC3H) 0 (PFC3L) 0 Remarks 1. For details of alternate function specification, see 4.3.3 (6) specifications. 2. The PFC3 register can be read or written in 16-bit units. ...
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Port 3 alternate function specifications PFC39 0 RXDA2 input 1 SCL00 I/O PFC38 0 TXDA2 output 1 SDA00 I/O PFC35 0 TIP11 input 1 TOP11 output PFC34 0 TIP10 input 1 TOP10 output PFC33 0 TIP01 input 1 TOP01 ...
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Port 3 function register (PF3) After reset: 0000H 15 PF3 (PF3H) 0 (PF3L) PF37 PF3n 0 1 Caution When a pull-up resistor at EV PF3n bit to 1. Remarks 1. The PF3 register can be read or written in ...
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Port 4 Port 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-7. Port 4 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF GC P40 24 22 ...
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Port 4 mode control register (PMC4) After reset: 00H R/W PMC4 0 PMC42 0 I/O port 1 SCKB0 I/O PMC41 0 I/O port 1 SOB0 output/SCL01 I/O PMC40 0 I/O port 1 SIB0 input/SDA01 I/O (4) Port 4 function ...
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Port 5 Port 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-8. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF GC P50 39 37 ...
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Port 5 mode register (PM5) After reset: FFH R/W PM5 1 PM5n 0 Output mode 1 Input mode (3) Port 5 mode control register (PMC5) After reset: 00H R/W PMC5 0 PMC55 0 I/O port 1 SCKB2 I/O/KR5 input/RTP05 ...
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Port 5 function control register (PFC5) After reset: 00H R/W PFC5 0 0 Remark For details of alternate function specification, see 4.3.5 (6) specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H R/W PFCE5 0 0 ...
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PFCE52 PFC52 PFCE51 PFC51 PFCE50 PFC50 Note KRn and TIQ0m are alternate functions. When using the ...
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Port 7 Port 12-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-9. Port 7 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) P7H 0 P77 P76 P7L P7n 0 Outputs 0 1 Outputs 1 Caution Do not read or write the P7H and P7L registers during ...
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Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-10. Port 9 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port 9 register (P9) After reset: 0000H (output latch (P9H) P915 (P9L) P97 P9n 0 Outputs 0 1 Outputs 1 Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the ...
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Port 9 mode control register (PMC9) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC915 0 I/O port 1 A15 output/INTP6 input/TIP50 input/TOP50 output PMC914 0 I/O port 1 A14 output/INTP5 input/TIP51 input/TOP51 ...
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PMC97 0 I/O port 1 A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 0 I/O port 1 A6 output/TIP21 input/TOP21 output PMC95 0 I/O port 1 A5 output/TIP30 input/TOP30 output PMC94 0 I/O port 1 A4 output/TIP31 input/TOP31 output PMC93 0 I/O ...
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Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 and PFCE9 registers to 0000H. After reset: ...
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Port 9 alternate function specifications PFCE915 PFC915 PFCE914 PFC914 PFC913 0 A13 output 1 INTP4 input PFC912 0 A12 output 1 SCKB3 I/O ...
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PFCE96 PFC96 PFCE95 PFC95 PFCE94 PFC94 PFCE93 PFC93 ...
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Port 9 function register (PF9) After reset: 0000H 15 PF9 (PF9H) PF915 (PF9L) PF97 PF9n 0 1 Caution When a pull-up resistor set the PF9n bit to 1. Pull up output pins P97 to P915 at ...
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Port CM Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-11. Port CM Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port CM mode control register (PMCCM) After reset: 00H R/W PMCCM 0 PMCCM3 0 I/O port 1 HLDRQ input PMCCM2 0 I/O port 1 HLDAK output PMCCM1 0 I/O port 1 CLKOUT output PMCCM0 0 I/O port 1 WAIT ...
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Port CT Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-12. Port CT Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port CT mode control register (PMCCT) After reset: 00H R/W PMCCT 0 PMCCT6 PMCCT6 0 I/O port 1 ASTB output PMCCT4 0 I/O port 1 RD output PMCCT1 0 I/O port 1 WR1 output PMCCT0 0 I/O port 1 ...
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Port DH Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-13. Port DH Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port DH mode control register (PMCDH) After reset: 00H R/W PMCDH 0 PMCDHn 0 I/O port 1 Am output (address bus output 21) 120 CHAPTER 4 PORT FUNCTIONS Address: FFFFF046H 0 PMCDH5 PMCDH4 PMCDH3 PMCDH2 ...
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Port DL Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-14. Port DL Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF ...
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Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 (PDLL) PDL7 PDLn 0 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 bits of ...
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Port DL mode control register (PMCDL) After reset: 0000H 15 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Caution When the SMSEL bit of the EXIMC register ...
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Block Diagrams PORT RD 124 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of Type A-1 PMmn Pmn Address P-ch A/D input signal N-ch Preliminary User’s Manual U18953EJ1V0UD Pmn ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A PMmn WR PORT Pmn Address RD D/A output signal Preliminary User’s Manual U18953EJ1V0UD Pmn P-ch N-ch 125 ...
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WR PF PFmn WR PM PMmn WR PORT Pmn Address RD 126 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type C-1 Preliminary User’s Manual U18953EJ1V0UD EV DD P-ch Pmn N- ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D-1 WR PMC PMCmn WR PM PMmn WR PORT Pmn Address Input signal when RD alternate function is used Preliminary User’s Manual U18953EJ1V0UD Pmn 127 ...
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WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn RD 128 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-2 Address Preliminary User’s Manual U18953EJ1V0UD Pmn ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D-3 WR PMC PMCmn Output enable signal of address/data bus Output buffer off signal WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address Input enable ...
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WR PF PFmn Output enable signal when alternate function is used WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are ...
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Figure 4-10. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis ...
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WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR ...
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WR PF PFmn Output enable signal when alternate function is used WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address ...
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Figure 4-14. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal 1 when alternate function is used Input ...
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WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used ...
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Figure 4-16. Block Diagram of Type L PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when Edge detection alternate function is ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used detection Input signal 2 when ...
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Figure 4-18. Block Diagram of Type N PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate ...
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Figure 4-20. Block Diagram of Type U PFmn Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal 1-1 when RD ...
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Figure 4-22. Block Diagram of Type U PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
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WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging WR ...
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Figure 4-24. Block Diagram of Type U PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
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WR PF PFmn WR OCDM0 OCDM0 Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function ...
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Figure 4-26. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal 1 when ...
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Figure 4-28. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when RD alternate ...
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Figure 4-30. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
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Figure 4-32. Block Diagram of Type AA PFmn External reset signal WR OCDM0 OCDM0 WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when ...
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Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each ...
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Table 4-15. Settings When Port Pins Are Used for Alternate Functions (1/7) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Input P02 NMI P02 = Setting not required Input P03 INTP0 P03 = Setting not required ADTRG ...
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Table 4-15. Settings When Port Pins Are Used for Alternate Functions (2/7) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P34 Input P34 = Setting not required TIP10 Output P34 = Setting not required TOP10 Input P35 ...
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Table 4-15. Settings When Port Pins Are Used for Alternate Functions (3/7) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Input P51 TIQ02 P51 = Setting not required Input KR1 P51 = Setting not required Output TOQ02 ...
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Table 4-15. Settings When Port Pins Are Used for Alternate Functions (4/7) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P70 ANI0 Input P70 = Setting not required P71 ANI1 Input P71 = Setting not required P72 ...
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Table 4-15. Settings When Port Pins Are Used for Alternate Functions (5/7) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P92 A2 Output P92 = Setting not required TIP41 Input P92 = Setting not required TOP41 Output ...
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Table 4-15. Settings When Port Pins Are Used for Alternate Functions (6/7) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P910 A10 Output P910 = Setting not required SIB3 Input P910 = Setting not required P911 A11 ...
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Table 4-15. Settings When Port Pins Are Used for Alternate Functions (7/7) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Output PDH0 A16 PDH0 = Setting not required A17 Output PDH1 PDH1 = Setting not required PDH2 ...
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Cautions 4.6.1 Cautions on setting port pins (1) In the V850ES/JG3-L, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function ...
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CHAPTER 4 PORT FUNCTIONS The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order Setting Contents <1> Initial value (PMC41 bit = 0, PFC41 bit = ...
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Figure 4-33. Example of Switching from P02 to NMI (Incorrect) PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Remark [Example 2] Switch from external pin (NMI) to general-purpose ...
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Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is ...
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Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST high ...
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CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JG3-L is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplexed bus output with ...
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Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (Multiplexed Bus) Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 A16 to A21 PDH0 ...
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Memory Block Function The 16 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks ...
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External Bus Interface Mode Control Function The V850ES/JG3-L has the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus interface ...
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Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access Notes ...
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Access by bus size The V850ES/JG3-L accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 ...
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CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) Address Byte data External data bus (b) 8-bit data bus width <1> ...
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Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) Address Halfword data External data bus (b) 8-bit data bus width ...
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CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Address ...
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Access to address ( First access Address Word data External data bus <4> ...
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CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address ...
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Access to address ( First access Second access Address Word ...
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Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/ seven data wait states can be inserted in the bus cycle that is executed for ...
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External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is set ...
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Relationship between programmable wait and external wait Wait cycles are inserted as the result operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT ...
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Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each memory block area (memory blocks 0 to 3). If ...
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Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the memory block in the multiplex ...
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Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested ...
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Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK = ...
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Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), ...
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Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A21 to A16 A1 ASTB WAIT AD15 to AD0 8-bit Access AD15 to AD8 AD7 to AD0 Remark ...
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Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A21 to A16 A1 ASTB WAIT A1 D1 AD15 to AD0 11 00 WR1, WR0 8-bit Access AD15 to AD8 AD7 to AD0 WR1, WR0 ...
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CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT HLDRQ HLDAK A21 to A16 AD15 to AD0 ASTB RD Note This idle state (TI) does not ...
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Figure 5-10. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT WAIT A1 A21 AD15 to AD0 D1 8-bit Access Odd Address AD15 to AD8 Active AD7 to AD0 Hi-Z Remark The broken ...
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CHAPTER 5 BUS CONTROL FUNCTION Figure 5-12. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT WAIT A1 A21 WR1, WR0 AD15 to AD0 D1 8-bit Access Odd Address AD15 to AD8 ...
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Figure 5-14. Separate Bus Hold Timing (Bus Size: 8 Bits, Write CLKOUT HLDRQ HLDAK A21 AD7 to AD0 D1 WR1, WR0 Note This idle state (TI) does not depend on the ...
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CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode MHz ( MHz • In PLL mode f ...
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CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration FRC bit XT1 f Subclock XT oscillator XT2 MCK MFRC PLLON bit bit bit X1 f Main clock X PLL oscillator X2 Main clock oscillator stop control STOP mode SELPLL bit CLKOUT Port ...
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CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator connects the ceramic/crystal resonator to X1 and X2 pins and oscillates the following frequencies ( • In clock-through mode MHz ...
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CHAPTER 6 CLOCK GENERATION FUNCTION 6.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.7 Special registers). This register can ...
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CHAPTER 6 CLOCK GENERATION FUNCTION After reset: 03H R/W < > PCC FRC MCK FRC 0 Used 1 Not used MCK 0 Oscillation enabled 1 Oscillation stopped • Even if the MCK bit is set (1) while the system is ...
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CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the <3> MCK bit ...
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CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main ...
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CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset ...