LM3S2601-IBZ50-A2T

Manufacturer Part NumberLM3S2601-IBZ50-A2T
DescriptionIC ARM CORTEX MCU 128KB 108NFBGA
ManufacturerTexas Instruments
SeriesStellaris® 2000
LM3S2601-IBZ50-A2T datasheet
 


Specifications of LM3S2601-IBZ50-A2T

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed50MHzConnectivityCAN, I²C, IrDA, Microwire, SPI, SSI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o60
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size32K x 8Voltage - Supply (vcc/vdd)2.25 V ~ 2.75 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case108-NFBGAProcessor SeriesStellaris 2000
CoreARM Cortex M3Data Bus Width32 bit
Data Ram Size32 KBInterface TypeI2C, SPI, SSI, UART
Maximum Clock Frequency50 MHzNumber Of Programmable I/os60
Number Of Timers6Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsJTAGjet-CortexM3, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature- 40 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
Page 1/619

Download datasheet (6Mb)Embed
Next
TE X A S I NS T RUM E NT S -P RO DUCT IO N D ATA
Stellaris® LM3S2601 Microcontroller
D ATA S H E E T
D S -L M3 S2 60 1- 91 02
Co pyri gh t © 20 07 -2 011
Texa s Instrument s I nco rp orat ed

LM3S2601-IBZ50-A2T Summary of contents

  • Page 1

    ... Stellaris® LM3S2601 Microcontroller RUM DUCT ATA D ATA pyri gh t © 011 Texa s Instrument s I nco rp orat ed ...

  • Page 2

    ... Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ...

  • Page 3

    ... Memory System Ordering of Memory Accesses .............................................................. 64 2.4.3 Behavior of Memory Accesses ....................................................................................... 64 2.4.4 Software Ordering of Memory Accesses ......................................................................... 65 2.4.5 Bit-Banding ................................................................................................................... 66 2.4.6 Data Storage ................................................................................................................ 68 2.4.7 Synchronization Primitives ............................................................................................. 69 2.5 Exception Model ........................................................................................................... 70 2.5.1 Exception States ........................................................................................................... 70 2.5.2 Exception Types ............................................................................................................ 71 2.5.3 Exception Handlers ....................................................................................................... 74 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 3 ...

  • Page 4

    ... Reset Control .............................................................................................................. 161 5.1.3 Power Control ............................................................................................................. 165 5.1.4 Clock Control .............................................................................................................. 166 5.1.5 System Control ........................................................................................................... 171 5.2 Initialization and Configuration ..................................................................................... 172 5.3 Register Map .............................................................................................................. 172 5.4 Register Descriptions .................................................................................................. 174 6 Hibernation Module .............................................................................................. 225 6.1 Block Diagram ............................................................................................................ 226 4 Texas Instruments-Production Data January 09, 2011 ...

  • Page 5

    ... GPTM Reset Conditions .............................................................................................. 314 9.2.2 32-Bit Timer Operating Modes ...................................................................................... 314 9.2.3 16-Bit Timer Operating Modes ...................................................................................... 315 9.3 Initialization and Configuration ..................................................................................... 319 9.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 319 9.3.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 320 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 5 ...

  • Page 6

    ... C Bus Functional Overview ........................................................................................ 451 13.2.2 Available Speed Modes ............................................................................................... 453 13.2.3 Interrupts .................................................................................................................... 454 13.2.4 Loopback Operation .................................................................................................... 455 13.2.5 Command Sequence Flow Charts ................................................................................ 455 13.3 Initialization and Configuration ..................................................................................... 462 13.4 Register Map .............................................................................................................. 463 13.5 Register Descriptions ( Interface ................................................................ 450 2 C Master) ............................................................................... 464 Texas Instruments-Production Data January 09, 2011 ...

  • Page 7

    ... On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 572 19.1.4 GPIO Module Characteristics ....................................................................................... 572 19.1.5 Power Specifications ................................................................................................... 572 19.1.6 Flash Memory Characteristics ...................................................................................... 574 19.1.7 Hibernation ................................................................................................................. 574 19.2 AC Characteristics ....................................................................................................... 574 19.2.1 Load Conditions .......................................................................................................... 574 19.2.2 Clocks ........................................................................................................................ 574 January 09, 2011 2 C Slave) ................................................................................. 477 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 7 ...

  • Page 8

    ... LQFP Package ............................................................................................... 611 D.1.1 Package Dimensions ................................................................................................... 611 D.1.2 Tray Dimensions ......................................................................................................... 613 D.1.3 Tape and Reel Dimensions .......................................................................................... 613 D.2 108-Ball BGA Package ................................................................................................ 615 D.2.1 Package Dimensions ................................................................................................... 615 D.2.2 Tray Dimensions ......................................................................................................... 617 D.2.3 Tape and Reel Dimensions .......................................................................................... 618 Interface ........................................................................... 582 Texas Instruments-Production Data January 09, 2011 ...

  • Page 9

    ... List of Figures Figure 1-1. Stellaris LM3S2601 Microcontroller High-Level Block Diagram .............................. 36 Figure 2-1. CPU Block Diagram ............................................................................................. 45 Figure 2-2. TPIU Block Diagram ............................................................................................ 46 Figure 2-3. Cortex-M3 Register Set ........................................................................................ 48 Figure 2-4. Bit-Band Mapping ................................................................................................ 68 Figure 2-5. Data Storage ....................................................................................................... 69 Figure 2-6. Vector table ......................................................................................................... 75 Figure 2-7. Exception Stack Frame ........................................................................................ 77 Figure 3-1 ...

  • Page 10

    ... LQFP Tray Dimensions .......................................................................... 613 Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 614 Figure D-4. 108-Ball BGA Package Dimensions .................................................................... 615 Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 617 Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 618 Bus ................................................... 453 Texas Instruments-Production Data January 09, 2011 ...

  • Page 11

    ... Timers Register Map .......................................................................................... 322 Table 10-1. Watchdog Timer Register Map ............................................................................ 350 Table 11-1. UART Register Map ........................................................................................... 379 Table 12-1. SSI Register Map .............................................................................................. 424 Table 13-1. Examples of I January 09, 2011 2 C Master Timer Period versus Speed Mode ................................... 454 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 11 ...

  • Page 12

    ... Table 19-16. GPIO Characteristics ......................................................................................... 580 Table 19-17. SSI Characteristics ............................................................................................ 580 2 Table 19-18 Characteristics ............................................................................................. 582 Table 19-19. Analog Comparator Characteristics ..................................................................... 583 Table 19-20. Analog Comparator Voltage Reference Characteristics ........................................ 583 Table C-1. Part Ordering Information ................................................................................... 609 Interface Register Map ............................................. 463 Texas Instruments-Production Data January 09, 2011 ...

  • Page 13

    ... Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 110 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 110 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 110 Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 110 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 13 ...

  • Page 14

    ... Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 197 Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 199 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 201 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 202 14 Texas Instruments-Production Data January 09, 2011 ...

  • Page 15

    ... GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 280 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 281 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 282 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 283 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 15 ...

  • Page 16

    ... GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 345 Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 346 Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 347 Watchdog Timer ........................................................................................................................... 348 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 352 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 353 16 Texas Instruments-Production Data January 09, 2011 ...

  • Page 17

    ... UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 412 Synchronous Serial Interface (SSI) ............................................................................................ 413 Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 425 Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 427 Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 429 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 17 ...

  • Page 18

    ... Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 516 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 516 Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 517 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 517 18 Texas Instruments-Production Data January 09, 2011 ...

  • Page 19

    ... Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 538 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 538 Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 539 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 539 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 19 ...

  • Page 20

    ... Revision History Revision History The revision history table notes changes made between the indicated revisions of the LM3S2601 data sheet. Table 1. Revision History Date Revision Description January 2011 9102 ■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ to SYSRESREQ. ■ ...

  • Page 21

    ... Operating Conditions table. SIH SIL Added table showing actual PLL frequency depending on input crystal. Changed the name of the t parameter to t HIB_REG_WRITE Changed SSI set up and hold times to be expressed in system clocks, not ns. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller . HIB_REG_ACCESS 21 ...

  • Page 22

    ... August 2008 3447 ■ Added note on clearing interrupts to Interrupts chapter. ■ Added Power Architecture diagram to System Control chapter. ■ Additional minor data sheet clarifications and corrections. July 2008 3108 ■ Additional minor data sheet clarifications and corrections. 22 Texas Instruments-Production Data IR January 09, 2011 ...

  • Page 23

    ... Battery voltage is not measured while in Hibernate mode. System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ) in the "Maximum Ratings" table in the "Electrical 23 ...

  • Page 24

    ... March 2008 2550 Started tracking revision history. 24 The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins. The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams. Texas Instruments-Production Data January 09, 2011 ...

  • Page 25

    ... About This Document This data sheet provides reference information for the LM3S2601 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers ...

  • Page 26

    ... Bit cleared chip reset. 1 Bit set chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. 26 Texas Instruments-Production Data January 09, 2011 ...

  • Page 27

    ... Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 27 ...

  • Page 28

    ... For applications requiring extreme conservation of power, the LM3S2601 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S2601 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S2601 microcontroller perfectly for battery applications ...

  • Page 29

    ... Optimized for single-cycle flash usage – Three sleep modes with clock gating for low power – Single-cycle multiply instruction and hardware divide – Atomic operations – ARM Thumb2 mixed 16-/32-bit instruction set January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 29 ...

  • Page 30

    ... User-managed flash data programming • User-defined and managed flash-protection block – single-cycle SRAM ■ GPIOs – 21-60 GPIOs, depending on configuration – 5-V-tolerant in input configuration – Programmable control for GPIO interrupts • Interrupt generation masking • Edge-triggered on rising, falling, or both 30 Texas Instruments-Production Data January 09, 2011 ...

  • Page 31

    ... Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug – 16-bit Input Capture modes • Input edge count capture • Input edge time capture January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 31 ...

  • Page 32

    ... Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations • Programmable internal clock generator enabling division of reference clock 256 for low-power mode bit duration ■ Synchronous Serial Interface (SSI) – Two SSI modules, each with the following features: 32 Texas Instruments-Production Data January 09, 2011 ...

  • Page 33

    ... Bit rates Mbps – 32 message objects with individual identifier masks – Maskable interrupt – Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications January 09, 2011 2 C bus can be designated as either a master or a slave Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 33 ...

  • Page 34

    ... Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package ■ Industrial-range 108-ball RoHS-compliant BGA package 34 Texas Instruments-Production Data January 09, 2011 ...

  • Page 35

    ... Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 36 depicts the features on the Stellaris LM3S2601 microcontroller. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 35 ...

  • Page 36

    ... Architectural Overview Figure 1-1. Stellaris LM3S2601 Microcontroller High-Level Block Diagram LM3S2601 36 JTAG/SWD ARM® Cortex -M3 (50 MHz) System Control and Clocks NVIC Bus Matrix Hibernation Module GPIOs (21-60) I2C (2) CAN Controller (1) Texas Instruments-Production Data Flash DCode bus (128 KB) MPU ICode bus ...

  • Page 37

    ... Memory Map (see page 62) A memory map lists the location of instructions and data in memory. The memory map for the LM3S2601 controller can be found in Table 2-4 on page 62. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. ...

  • Page 38

    ... The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S2601 controller features Pulse Width Modulation (PWM) outputs. 1.4.2.1 PWM Pulse width modulation (PWM powerful technique for digitally encoding analog signal levels. ...

  • Page 39

    ... Synchronous Serial Interface (SSI four-wire bi-directional full and low-speed communications interface. The LM3S2601 controller includes two SSI modules that provide the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive ...

  • Page 40

    ... A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from bytes of user information. The LM3S2601 includes one CAN unit. 1.4.5 System Peripherals 1 ...

  • Page 41

    ... Flash (see page 246) The LM3S2601 Flash controller supports 128 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected ...

  • Page 42

    ... Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 541 ■ “Signal Tables” on page 543 ■ “Operating Characteristics” on page 570 ■ “Electrical Characteristics” on page 571 ■ “Package Information” on page 611 42 Texas Instruments-Production Data January 09, 2011 ...

  • Page 43

    ... The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 43 ...

  • Page 44

    ... ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 44 Texas Instruments-Production Data January 09, 2011 ...

  • Page 45

    ... Unit Data Watchpoint Flash and Trace Patch and Breakpoint Private Peripheral Bus (internal) Bus Matrix Debug Access Port Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Serial ARM Wire Cortex-M3 Output Trace Port Trace (SWO) Port Interface Unit Instrumentation Trace Macrocell ROM Table Adv ...

  • Page 46

    ... Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 86). ■ System Control Block (SCB) 46 Asynchronous FIFO Texas Instruments-Production Data Serial Wire Trace Out Trace Port (serializer) (SWO) ...

  • Page 47

    ... The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 47 ...

  • Page 48

    ... R11 R12 ‡ SP (R13) PSP LR (R14) PC (R15) PSR Program status register PRIMASK FAULTMASK Exception mask registers BASEPRI CONTROL CONTROL register Texas Instruments-Production Data Stack Used a Main stack or process stack Main stack ‡ ‡ MSP Banked version of SP Special registers January 09, 2011 a ...

  • Page 49

    ... Cortex General-Purpose Register 11 - Cortex General-Purpose Register 12 - Stack Pointer 0xFFFF.FFFF Link Register - Program Counter 0x0100.0000 Program Status Register 0x0000.0000 Priority Mask Register 0x0000.0000 Fault Mask Register 0x0000.0000 Base Priority Mask Register 0x0000.0000 Control Register Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller See page ...

  • Page 50

    ... R/W R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31:0 DATA DATA R/W R/W R/W R/W R DATA R/W R/W R/W R/W R Type Reset Description R/W - Register data. Texas Instruments-Production Data R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R January 09, 2011 - 0 - ...

  • Page 51

    ... Bit/Field Name 31:0 SP January 09, 2011 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the address of the stack pointer. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 52

    ... R/W Reset Bit/Field Name 31:0 LINK LINK R/W R/W R/W R/W R LINK R/W R/W R/W R/W R Type Reset Description R/W 0xFFFF.FFFF This field is the return address. Texas Instruments-Production Data R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R January 09, 2011 ...

  • Page 53

    ... Bit/Field Name 31:0 PC January 09, 2011 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the current program address. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 54

    ... Type R/W, reset 0x0100.0000 Type R/W R/W R/W R/W R/W Reset ICI / IT Type Reset Type Combination R/W APSR, EPSR, and IPSR RO EPSR and IPSR a R/W APSR and IPSR b R/W APSR and EPSR ICI / IT THUMB reserved Texas Instruments-Production Data reserved ISRNUM January 09, 2011 ...

  • Page 55

    ... DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 55 ...

  • Page 56

    ... The value of this field is only meaningful when accessing PSR or EPSR. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data January 09, 2011 ...

  • Page 57

    ... Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3B Interrupt Vector 43 0x3C-0x3F Reserved See “Exception Types” on page 71 for more information. The value of this field is only meaningful when accessing PSR or IPSR. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 57 ...

  • Page 58

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority effect. Texas Instruments-Production Data ...

  • Page 59

    ... R/W 0 Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 60

    ... All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 61

    ... In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 62

    ... The processor has a fixed memory map that provides addressable memory. The memory map for the LM3S2601 controller is provided in Table 2-4 on page 62. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. ...

  • Page 63

    ... Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) Reserved Trace Port Interface Unit (TPIU) Reserved Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller For details, see page ... 424 - 379 379 379 - ...

  • Page 64

    ... Peripheral Device XN External RAM Normal - Texas Instruments-Production Data Description This executable region is for program code. Data can also be stored here. This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 66). ...

  • Page 65

    ... January 09, 2011 Memory Region Memory Type Execute Never (XN) External device Device XN Private peripheral Strongly XN bus Ordered Reserved - - Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Description This region is for external device memory. This region includes the NVIC, system timer, and system control block ...

  • Page 66

    ... Table 2-6. SRAM Memory Bit-Banding Regions Address Range 0x2000.0000 - 0x200F.FFFF 66 Memory Region Instruction and Data Accesses SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. Texas Instruments-Production Data January 09, 2011 ...

  • Page 67

    ... Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 67 ...

  • Page 68

    ... Figure 2-5 on page 69 illustrates how data is stored. 68 32-MB Alias Region 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 1-MB SRAM Bit-Band Region 0x200F.FFFE 0x200F.FFFD 0x2000.0002 0x2000.0001 Texas Instruments-Production Data 0x23FF.FFE4 0x23FF.FFE0 0x2200.0004 0x2200.0000 0x200F.FFFC 0x2000.0000 January 09, 2011 ...

  • Page 69

    ... The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. January 09, 2011 Register Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 69 ...

  • Page 70

    ... See “Nested Vectored Interrupt Controller (NVIC)” on page 86 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: 70 Texas Instruments-Production Data January 09, 2011 ...

  • Page 71

    ... Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 71 ...

  • Page 72

    ... NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 73 lists the interrupts on the LM3S2601 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler ...

  • Page 73

    ... Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Activation b Offset Asynchronous Asynchronous Description Processor exceptions GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 Reserved Watchdog Timer 0 Timer 0A ...

  • Page 74

    ... Table 2-8 on page 72. Figure 2-6 on page 75 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code 74 Vector Address or Description Offset 38 - Reserved 39 0x0000.00DC CAN0 40-42 - Reserved 43 0x0000.00EC Hibernation Module Texas Instruments-Production Data January 09, 2011 ...

  • Page 75

    ... IRQ0 0x0040 Systick 0x003C PendSV 0x0038 Reserved Reserved for Debug SVCall 0x002C Reserved Usage fault 0x0018 Bus fault 0x0014 Memory management fault 0x0010 Hard fault 0x000C NMI 0x0008 Reset 0x0004 Initial SP value 0x0000 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 75 ...

  • Page 76

    ... Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor Texas Instruments-Production Data January 09, 2011 ...

  • Page 77

    ... If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. January 09, 2011 Pre-IRQ top of stack IRQ top of stack Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 77 ...

  • Page 78

    ... Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses state from MSP. Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. Reserved Texas Instruments-Production Data January 09, 2011 ...

  • Page 79

    ... Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Bit Name VECT FORCED a IERR DERR MSTKE MUSTKE BSTKE ...

  • Page 80

    ... Sleep mode and Deep-sleep mode. 80 Address Register Name - Memory Management Fault Address (MMADDR) Bus Fault Address (FAULTADDR) - Texas Instruments-Production Data Register Description page 137 page 131 page 138 page 131 page 139 page 131 January 09, 2011 ...

  • Page 81

    ... In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 120. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 81 ...

  • Page 82

    ... Compare negative Rn , Op2 Compare Rn , Op2 Change processor state, disable iflags interrupts Change processor state, enable iflags interrupts Data memory barrier - Data synchronization barrier - Exclusive OR { Op2 Instruction synchronization barrier - - If-Then condition block Texas Instruments-Production Data Flags N,Z,C,V N,Z,C,V N,Z,C,V - N,Z,C N,Z N,Z ...

  • Page 83

    ... Reverse byte order in bottom halfword and sign extend Rotate right <Rs|#n> Rotate right with extend Reverse subtract {Rd Op2 Subtract with carry {Rd Op2 Signed bit field extract #lsb , #width Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Flags - - - - - - - - - - - - ...

  • Page 84

    ... Unsigned multiply with accumulate RdLo, RdHi, Rn, Rm (32x32+32+32), 64-bit result Unsigned multiply (32x 2), 64-bit result RdLo, RdHi, Rn, Rm Unsigned saturate Rd, #n, Rm {,shift #s} Zero extend a byte {Rd,} Rm {,ROR #n} Zero extend a halfword {Rd,} Rm {,ROR #n} - Wait for event - Wait for interrupt Texas Instruments-Production Data Flags - - - - ...

  • Page 85

    ... A high-speed alarm timer using the system clock. January 09, 2011 ® implementation of the Cortex-M3 processor Core Peripheral System Timer Nested Vectored Interrupt Controller System Control Block Memory Protection Unit Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Description (see page ...) ...

  • Page 86

    ... Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). 86 Texas Instruments-Production Data January 09, 2011 ...

  • Page 87

    ... Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 87 ...

  • Page 88

    ... Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. 88 Description All accesses to Strongly Ordered memory occur in program order. Memory-mapped peripherals Normal memory Texas Instruments-Production Data January 09, 2011 ...

  • Page 89

    ... MPU region number register ; Region Number ; Region Base Address ; Region Size and Enable ; Region Attribute ; 0xE000ED98, MPU region number register ; Region Number ; Disable ; Region Size and Enable ; Region Base Address ; Region Attribute ; Enable ; Region Size and Enable Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 89 ...

  • Page 90

    ... MPU Region Base register ; Region base address and region number combined ; with VALID (bit 4) set ; Region Attribute, Size and Enable ; 0xE000ED9C, MPU Region Base register ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Texas Instruments-Production Data January 09, 2011 ...

  • Page 91

    ... Normal Not shareable 0 Normal Shareable 1 Reserved encoding - 0 Reserved encoding - 1 Normal Not shareable 1 Normal Shareable Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB 64KB 0 Other Attributes - - Outer and inner write-through. No write allocate. ...

  • Page 92

    ... Reads by privileged software only. RO Read-only, by privileged or unprivileged software. RO Read-only, by privileged or unprivileged software. TEX 000b 000b Texas Instruments-Production Data Shareability Other Attributes Not shareable Nonshared Device Not shareable Cached memory (BB = outer policy inner Shareable policy). See Table 3-4 for the encoding of the AA and BB bits. ...

  • Page 93

    ... Interrupt 32-43 Clear Pending 0x0000.0000 Interrupt 0-31 Active Bit 0x0000.0000 Interrupt 32-43 Active Bit 0x0000.0000 Interrupt 0-3 Priority Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Memory Type and Attributes Normal memory, shareable, write-back, write-allocate Device memory, shareable See page 96 98 ...

  • Page 94

    ... Memory Management Fault Address - Bus Fault Address 0x0000.0800 MPU Type 0x0000.0000 MPU Control 0x0000.0000 MPU Region Number 0x0000.0000 MPU Region Base Address 0x0000.0000 MPU Region Attribute and Size Texas Instruments-Production Data See page 110 110 110 110 110 110 110 110 110 110 ...

  • Page 95

    ... MPU Region Base Address Alias 2 0x0000.0000 MPU Region Attribute and Size Alias 2 0x0000.0000 MPU Region Base Address Alias 3 0x0000.0000 MPU Region Attribute and Size Alias 3 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller See page 144 146 144 146 144 146 ...

  • Page 96

    ... R/W 0 Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. Texas Instruments-Production Data COUNT ...

  • Page 97

    ... Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 97 ...

  • Page 98

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. Texas Instruments-Production Data RELOAD ...

  • Page 99

    ... This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 100

    ... Interrupt Enable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. Texas Instruments-Production Data R/W R/W R/W R/W R/W ...

  • Page 101

    ... R/W 0x000 Interrupt Enable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 102

    ... Type Reset Description R/W 0x0000.0000 Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. Texas Instruments-Production Data R/W R/W R/W R/W R/W R ...

  • Page 103

    ... R/W 0x000 Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 104

    ... On a write, no effect read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. Texas Instruments-Production Data R/W R/W ...

  • Page 105

    ... On a read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 106

    ... On a read, indicates that the interrupt is not pending write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Production Data R/W ...

  • Page 107

    ... On a read, indicates that the interrupt is not pending write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 108

    ... Offset 0x300 Type RO, reset 0x0000.0000 Type Reset Type Reset Bit/Field Name 31:0 INT 108 INT INT Type Reset Description RO 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Production Data January 09, 2011 ...

  • Page 109

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0x000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 110

    ... Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type R/W, reset 0x0000.0000 INTD Type R/W R/W R Reset INTB Type R/W R/W R Reset 110 Interrupt Interrupt [4n+3] Interrupt [4n+2] Interrupt [4n+1] Interrupt [4n reserved INTC R/W R reserved INTA R/W R Texas Instruments-Production Data reserved R reserved R January 09, 2011 ...

  • Page 111

    ... PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 111 ...

  • Page 112

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WO 0x00 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. Texas Instruments-Production Data ...

  • Page 113

    ... Constant Value Description 0xF Always reads as 0xF. RO 0xC23 Part Number Value Description 0xC23 Cortex-M3 processor. RO 0x1 Revision Number Value Description 0x1 The pn value in the rnpn product revision identifier, for example, the 1 in r1p1. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller CON ...

  • Page 114

    ... On a read, indicates a PendSV exception is not pending write, no effect read, indicates a PendSV exception is pending write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing the UNPENDSV bit. Texas Instruments-Production Data ...

  • Page 115

    ... This bit provides status for all interrupts excluding NMI and Faults. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 115 ...

  • Page 116

    ... ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 54). Texas Instruments-Production Data January 09, 2011 ...

  • Page 117

    ... Because there are 43 interrupts, the minimum alignment is 64 words. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller R/W ...

  • Page 118

    ... Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Group Subpriorities Priorities ...

  • Page 119

    ... This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable System Reset This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 119 ...

  • Page 120

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. Texas Instruments-Production Data ...

  • Page 121

    ... Setting this bit enables an interrupt-driven application to avoid returning to an empty main application Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 121 ...

  • Page 122

    ... The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 123

    ... The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 78 for more information). Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 123 ...

  • Page 124

    ... Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 125

    ... RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 126

    ... This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 127

    ... Usage Fault Enable Value Description 0 Disables the usage fault exception. 1 Enables the usage fault exception. R/W 0 Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller USAGE BUS R/W R ...

  • Page 128

    ... This bit can be modified to change the pending status of the usage fault exception. R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. Texas Instruments-Production Data January 09, 2011 ...

  • Page 129

    ... Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 129 ...

  • Page 130

    ... Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. Texas Instruments-Production Data January 09, 2011 ...

  • Page 131

    ... Type Reset Description RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller NOCP INVPC INVSTAT UNDEF RO RO R/W1C ...

  • Page 132

    ... The processor has attempted an illegal load of EXC_RETURN to the result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing it. Texas Instruments-Production Data January 09, 2011 ...

  • Page 133

    ... Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 133 ...

  • Page 134

    ... An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Production Data January 09, 2011 ...

  • Page 135

    ... MMADDR register. This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 135 ...

  • Page 136

    ... This fault occurs on any access region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing it. Texas Instruments-Production Data January 09, 2011 ...

  • Page 137

    ... This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 138

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. Texas Instruments-Production Data R/W R/W R/W R/W R/W R R/W R/W R/W ...

  • Page 139

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller R/W R/W R/W R/W R/W R ...

  • Page 140

    ... Indicates there are eight supported MPU data regions. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation Separate or Unified MPU Value Description 0 Indicates the MPU is unified. Texas Instruments-Production Data IREGION ...

  • Page 141

    ... reserved Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller PRIVDEFEN HFNMIENA ENABLE R/W R/W ...

  • Page 142

    ... When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. Texas Instruments-Production Data January 09, 2011 ...

  • Page 143

    ... R/W 0x0 MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 144

    ... Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 145

    ... R/W 0x0 Region Number On a write, contains the value to be written to the MPUNUMBER register read, returns the current region number in the MPUNUMBER register. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 145 ...

  • Page 146

    ... GB No valid ADDR field in MPUBASE; the region occupies the complete memory map reserved R/W R/W R reserved R/W R/W R Texas Instruments-Production Data Note Minimum permitted size - - - Maximum possible size TEX S C R/W R/W R/W R/W R/W R SIZE ENABLE R/W R/W R/W R/W R/W ...

  • Page 147

    ... R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 146 for more information. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 147 ...

  • Page 148

    ... Cortex-M3 Peripherals Bit/Field Name 0 ENABLE 148 Type Reset Description R/W 0 Region Enable Value Description 0 The region is disabled. 1 The region is enabled. Texas Instruments-Production Data January 09, 2011 ...

  • Page 149

    ... IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 149 ...

  • Page 150

    ... JTAG Interface Pins The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 4-1 on page 151. Detailed information on each pin follows. 150 Texas Instruments-Production Data TDO Cortex-M3 Debug Port ...

  • Page 151

    ... Internal Pull-Up Internal Pull-Down Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Enabled Disabled Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Drive Strength Drive Value N/A N/A N/A N/A N/A N/A N/A N/A 2-mA driver High-Z 151 ...

  • Page 152

    ... TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. 152 Texas Instruments-Production Data January 09, 2011 ...

  • Page 153

    ... In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. January 09, 2011 Select DR Scan 1 0 Capture Shift Exit Pause Exit Update Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller Select IR Scan 1 0 Capture Shift Exit Pause Exit Update 153 ...

  • Page 154

    ... Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. 154 Texas Instruments-Production Data January 09, 2011 ...

  • Page 155

    ... LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 155 ...

  • Page 156

    ... Instruction Description EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. Texas Instruments-Production Data January 09, 2011 ...

  • Page 157

    ... Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. BYPASS Connects TDI to TDO through a single Shift Register chain. Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 157 ...

  • Page 158

    ... BYPASS instruction. Please see “BYPASS Data Register” on page 159 for more information. 4.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 158 Texas Instruments-Production Data January 09, 2011 ...

  • Page 159

    ... EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. January 09, 2011 12 11 Part Number Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 1 0 TDO Manufacturer ID 1 159 ...

  • Page 160

    ... The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 160 ... GPIO m RST GPIO m+1 Texas Instruments-Production Data ... O O TDO GPIO n January 09, 2011 ...

  • Page 161

    ... Table 5-1 provides a summary of results of the various reset operations. Table 5-1. Reset Sources Reset Source Power-On Reset RST Brown-Out Reset January 09, 2011 Core Reset? JTAG Reset? Yes Yes Yes Pin Config Only Yes Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller On-Chip Peripherals Reset? Yes Yes No Yes 161 ...

  • Page 162

    ... If the application only uses the internal POR circuit, the RST input must be connected to the power supply (V ) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 163. DD 162 Core Reset? JTAG Reset? Yes No Yes crossing 2 guarantee proper operation. For applications DD Texas Instruments-Production Data On-Chip Peripherals Reset? No Yes b No Yes No Yes ) and generates DD January 09, 2011 ...

  • Page 163

    ... VDD Stellaris® RST kΩ to 100 kΩ µ the application requires the use of an external reset switch, Figure 5-3 on page 164 shows the proper circuitry to use. January 09, 2011 VDD Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller and then de-asserted MIN 163 ...

  • Page 164

    ... Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 164 VDD brown-out condition is detected, the system may BTH level is restored. The RESC register can be examined in the reset interrupt DD Texas Instruments-Production Data ) drops DD January 09, 2011 ...

  • Page 165

    ... See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 572. VDDA must be supplied with 3 the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the LDO and the clock circuitry. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 165 ...

  • Page 166

    ... OSC0 input pin external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being 166 Internal Logic and PLL Low-noise LDO Analog circuits I/O Buffers Texas Instruments-Production Data GND GND GND GND GNDA GNDA GND GND ...

  • Page 167

    ... January 09, 2011 Drive PLL? Used as SysClk? No BYPASS = 1 Yes No BYPASS = 1 Yes Yes BYPASS = 0, OSCSRC = Yes 0x0 No BYPASS = 1 Yes No BYPASS = 1 Yes Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller BYPASS = 1, OSCSRC = 0x1 BYPASS = 1, OSCSRC = 0x2 BYPASS = 1, OSCSRC = 0x0 BYPASS = 1, OSCSRC = 0x3 BYPASS = 1, OSCSRC2 = 0x7 167 ...

  • Page 168

    ... The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-2 on page 167. 168 PWMDW a XTAL b PLL ÷ 2 SYSDIV b,d BYPASS b,d ÷ 25 ÷ 50 Texas Instruments-Production Data a USEPWMDIV a PWM Clock a,d USESYSDIV System Clock b,d PWRDN ADC Clock CAN Clock January 09, 2011 ...

  • Page 169

    ... MHz Clock source frequency/6 28.57 MHz Clock source frequency/7 25 MHz Clock source frequency/8 22.22 MHz Clock source frequency/9 20 MHz Clock source frequency/10 ... ... Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller a StellarisWare Parameter b SYSCTL_SYSDIV_1 SYSCTL_SYSDIV_2 SYSCTL_SYSDIV_3 SYSCTL_SYSDIV_4 SYSCTL_SYSDIV_5 SYSCTL_SYSDIV_6 SYSCTL_SYSDIV_7 SYSCTL_SYSDIV_8 SYSCTL_SYSDIV_9 ...

  • Page 170

    ... The time between the configuration change and relock is T 19-8 on page 574). During the relock time, the affected PLL is not usable as a clock reference. 170 Frequency Frequency (BYPASS2=1) (BYPASS2=0) 3.125 MHz Clock source frequency/64 Texas Instruments-Production Data a StellarisWare Parameter SYSCTL_SYSDIV_64 (see Table READY January 09, 2011 ...

  • Page 171

    ... If the PLL is running at the time of the January 09, 2011 requirement. The counter is clocked by the main READY READY time met), after which it changes to the PLL. Software READY Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller condition is met after one of the two 171 ...

  • Page 172

    ... Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 5.3 Register Map Table 5-5 on page 173 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. 172 Texas Instruments-Production Data January 09, 2011 ...

  • Page 173

    ... Deep Sleep Mode Clock Gating Control Register 0 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 0x0780.0000 Deep Sleep Clock Configuration Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller See page 175 190 192 193 195 ...

  • Page 174

    ... System Control 5.4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. 174 Texas Instruments-Production Data January 09, 2011 ...

  • Page 175

    ... MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x1 Stellaris® Fury-class devices. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller CLASS ...

  • Page 176

    ... The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. Texas Instruments-Production Data January 09, 2011 ...

  • Page 177

    ... This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 178

    ... VADJ field are provided below. Value V (V) OUT 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 Texas Instruments-Production Data ). OUT VADJ R/W R/W R/W ...

  • Page 179

    ... IMC register is set and the BORIOR bit in the PBORCTL register is cleared Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 180

    ... This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 181

    ... The BORMIS is simply the BORRIS ANDed with the mask value, BORIM Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 182

    ... When set, indicates a brown-out reset is the cause of the reset event. R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. Texas Instruments-Production Data ...

  • Page 183

    ... RCC2 register is used as the system clock divider rather than the SYSDIV field in this register Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller reserved ...

  • Page 184

    ... Texas Instruments-Production Data Crystal Frequency (MHz) Using the PLL 1.000 reserved reserved 2.000 reserved reserved 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz 5.12 MHz 6 MHz (reset value) 6 ...

  • Page 185

    ... R/W 0 Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. R/W 1 Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 185 ...

  • Page 186

    ... RO - PLL F Value This field specifies the value supplied to the PLL’s F input PLL R Value This field specifies the value supplied to the PLL’s R input. Texas Instruments-Production Data ...

  • Page 187

    ... Power-Down PLL When set, powers down the PLL Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller reserved RO RO ...

  • Page 188

    ... Reserved 0x5 Reserved 0x6 Reserved 0x7 32 kHz 32.768-kHz external oscillator RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data January 09, 2011 ...

  • Page 189

    ... Use 32.768-kHz external oscillator as source. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller reserved RO RO ...

  • Page 190

    ... This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0xE1 LM3S2601 RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): ...

  • Page 191

    ... RoHS-compliant Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller 191 ...

  • Page 192

    ... SRAMSZ FLASHSZ Type Reset Description RO 0x007F SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x007F SRAM RO 0x003F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x003F 128 KB of Flash Texas Instruments-Production Data January 09, 2011 ...

  • Page 193

    ... When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter in the Stellaris Data Sheet for details on the MPU Hibernation Module Present When set, indicates that the Hibernation module is present. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller reserved RO ...

  • Page 194

    ... SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present JTAG Present When set, indicates that the JTAG debugger interface is present. Texas Instruments-Production Data January 09, 2011 ...

  • Page 195

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation I2C Module 1 Present When set, indicates that I2C module 1 is present. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller TIMER3 ...

  • Page 196

    ... RO 1 UART2 Present When set, indicates that UART module 2 is present UART1 Present When set, indicates that UART module 1 is present UART0 Present When set, indicates that UART module 0 is present. Texas Instruments-Production Data January 09, 2011 ...

  • Page 197

    ... RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller reserved ...

  • Page 198

    ... C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data January 09, 2011 ...

  • Page 199

    ... RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present GPIO Port C Present When set, indicates that GPIO Port C is present GPIO Port B Present When set, indicates that GPIO Port B is present. Texas Instruments-Production Data Stellaris® LM3S2601 Microcontroller ...

  • Page 200

    ... System Control Bit/Field Name 0 GPIOA 200 Type Reset Description RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. Texas Instruments-Production Data January 09, 2011 ...