UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet

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UPD70F3713GC-8BS-A

Manufacturer Part Number
UPD70F3713GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3713GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3713GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website: http://www.renesas.com
Old Company Name in Catalogs and Other Documents
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for UPD70F3713GC-8BS-A

UPD70F3713GC-8BS-A Summary of contents

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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User’s Manual V850ES/IE2 32-bit Single-Chip Microcontrollers Hardware μ PD70F3713 μ PD70F3714 Document No. U17716EJ2V0UD00 (2nd edition) Date Published February 2008 N 2005 Printed in Japan ...

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User’s Manual U17716EJ2V0UD ...

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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...

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The information in this document is current as of January, 2008. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most ...

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Readers This manual is intended for users who wish to understand the functions of the V850ES/IE2 to design application systems using the V850ES/IE2. Purpose This manual is intended to give users an understanding of the hardware functions. Organization The V850ES/IE2 ...

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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Data type: 6 Higher digits on the left and lower digits on the right xxx (overscore over ...

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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/IE2 V850ES Architecture User’s Manual V850ES/IE2 Hardware User’s Manual Documents related to development tools (user’s manuals) ...

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CHAPTER 1 INTRODUCTION................................................................................................................. 14 1.1 General .......................................................................................................................................14 1.2 Features .....................................................................................................................................15 1.3 Applications...............................................................................................................................16 1.4 Ordering Information ................................................................................................................16 1.5 Pin Configuration ......................................................................................................................17 1.6 Function Blocks ........................................................................................................................19 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 22 2.1 List of Pin Functions.................................................................................................................22 2.2 Pin I/O Circuits and ...

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Cautions on bit manipulation instruction for port n register (Pn) ................................................. 120 CHAPTER 5 CLOCK GENERATOR .....................................................................................................121 5.1 Overview ..................................................................................................................................121 5.2 Configuration ..........................................................................................................................122 5.3 Control Registers....................................................................................................................124 5.4 PLL Function ...........................................................................................................................130 5.4.1 Overview..................................................................................................................................... 130 5.4.2 PLL mode ................................................................................................................................... 130 5.4.3 ...

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Configuration.......................................................................................................................... 352 8.3 Control Register ..................................................................................................................... 353 8.4 Operation ................................................................................................................................ 354 8.4.1 Interval timer mode .....................................................................................................................354 8.5 Cautions .................................................................................................................................. 358 CHAPTER 9 MOTOR CONTROL FUNCTION .................................................................................... 359 9.1 Functional Overview .............................................................................................................. 359 9.2 Configuration.......................................................................................................................... 360 9.3 Control Registers ................................................................................................................... ...

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Timer interrupt request signal in timer trigger mode ................................................................... 468 11.9.5 Re-conversion start trigger input during stabilization time .......................................................... 468 11.9.6 Variation of A/D conversion results............................................................................................. 468 11.9.7 A/D conversion result hysteresis characteristics......................................................................... 468 11.9.8 Restrictions on setting one-shot ...

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Restore .......................................................................................................................................550 14.2.3 Non-maskable interrupt status flag (NP) .....................................................................................551 14.3 Maskable Interrupts ............................................................................................................... 552 14.3.1 Operation ....................................................................................................................................552 14.3.2 Restore .......................................................................................................................................554 14.3.3 Priorities of maskable interrupts..................................................................................................555 14.3.4 Interrupt control registers (xxICn) ...............................................................................................559 14.3.5 Interrupt mask registers (IMR0 ...

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CHAPTER 17 REGULATOR ..................................................................................................................605 17.1 Overview ..................................................................................................................................605 17.2 Operation .................................................................................................................................606 CHAPTER 18 FLASH MEMORY...........................................................................................................607 18.1 Features ...................................................................................................................................607 18.2 Memory Configuration............................................................................................................608 18.3 Functional Overview...............................................................................................................609 18.4 Rewriting by Dedicated Flash Memory Programmer ..........................................................613 18.4.1 Programming environment ......................................................................................................... 613 18.4.2 Communication mode................................................................................................................. 614 ...

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The V850ES/IE2 is one of the low-power operation products in the NEC Electronics V850 Series of single-chip microcontrollers designed for real-time control applications. 1.1 General The V850ES/IE2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral ...

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Features Minimum instruction execution time (at internal 20 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 × 32 → 64): 1 ...

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Clock generator: 2.5 MHz resonator connectable (external clock input prohibited) Multiplication function by PLL clock synthesizer (fixed to multiplication by eight MHz) CPU clock division function (f Power-save function: HALT/IDLE/ STOP mode Power-on-clear function Low-voltage detection function Self ...

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Pin Configuration • 64-pin plastic LQFP (14 × 14) μ PD70F3713GC-8BS-A μ PD70F3714GC-8BS-A P25/TOQ1B3 49 P24/TOQ1T3 50 P23/TOQ1B2 51 P22/TOQ1T2 52 P21/TOQ1B1 53 P20/TOQ1T1 54 ANI13 55 ANI12 56 ANI11 57 ANI10 REF1 AV 60 DD1 ...

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Pin Identification ADTRG0, ADTRG1: A/D trigger input ANI00 to ANI03, ANI10 to ANI13: Analog input Analog power supply DD0 DD1 Analog reference voltage REF0 REF1 Analog ground SS0 ...

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Function Blocks (1) Internal block diagram INTP0 to INTP6 TIQ00 to TIQ03, EVTQ0, TOQ1OFF, TOQH0OFF TOQ00 to TOQ03, TOQ10, TOQH01 to TOQH03, TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3 TIP00, TIP01, TIP20,TIP21, TOP2OFF, TOP3OFF TOP00, TOP01, TOP21,TOP31 TXDA0, TXDA1 RXDA0, ...

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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...

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Serial interface The V850ES/IE2 includes two asynchronous serial interface A (UARTA) channels and one 3-wire variable length serial I/O (CSIB) channel as the serial interface. For UARTA, data is transferred via the TXDAn and RXDAn pins ( ...

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List of Pin Functions The names and functions of the pins in the V850ES/IE2 are listed below. These pins can be divided into port pins and non-port pins according to their function. There are two power supplies for the ...

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Pin Name Pin No. P20 54 P21 53 P22 52 P23 51 P24 50 P25 49 P26 46 P27 45 P30 44 P31 43 P32 42 P33 41 P40 40 P41 39 P42 38 P43 37 <R> P44 36 PDL0 ...

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Non-port pins Pin Name Pin No. I/O ADTRG0 13 Input ADTRG1 12 Input 1 ANI00 Input 2 ANI01 Input 3 ANI02 Input 4 ANI03 Input 58 ANI10 Input ANI11 57 Input ANI12 56 Input 55 ANI13 Input − 63 ...

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Pin Name Pin No. I/O TIP00 37 Input TIP01 36 TIP20 19 TIP21 18 TIQ00 21 Input TIQ01 24 TIQ02 23 TIQ03 22 TOP00 37 Output TOP01 36 TOP21 18 TOP2OFF 15 Input TOP31 45 Output TOP3OFF 14 Input Note ...

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Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name Alternate-Function Pin Name P00 INTP0/TOQH0OFF P01 INTP1/TOQ1OFF P02 INTP2/TOP2OFF P03 INTP3/TOP3OFF P04 INTP4/ADTRG0 P05 INTP5/ADTRG1 P06 INTP6 P10 TOQH01/TIQ01/TOQ01 P11 TIQ02/TOQ02 P12 TOQH02/TIQ03/TOQ03 P13 TIQ00 P14 TOQH03/EVTQ0 Note ...

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Pin Name Alternate-Function Pin Name − PDL0 − PDL1 − PDL2 − PDL3 − PDL4 PDL5 FLMD1 − PDL6 − PDL7 − ANI00 − ANI01 − ANI02 − ANI03 − ANI10 − ANI11 − ANI12 − ANI13 − RESET − ...

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Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-AG Pull-up enable EV Data Output disable Input enable 28 CHAPTER 2 PIN FUNCTIONS Type 7 P- SS0 Type 8 ...

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The CPU of the V850ES/IE2 is based on the RISC architecture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 Features Minimum instruction execution time Memory space Program (physical address) space ...

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CPU Register Set The CPU registers of the V850ES/IE2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture ...

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Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. All of these registers can be used as a data variable ...

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System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, ...

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Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the ...

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NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the ...

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Program status word (PSW) The program status word (PSW collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the ...

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Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation ...

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Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and ...

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Operating Modes The V850ES/IE2 has the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to ...

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Address Space 3.4.1 CPU address space For instruction addressing, an internal ROM area MB, and an internal RAM area are supported in a linear address space (program space MB. For operand ...

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Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow ...

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Memory map The V850ES/IE2 has reserved areas as shown below. Figure 3-2. Data Memory Map (Physical Addresses) 3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH Access-prohibited area 0200000H 01FFFFFH (2 MB) 0000000H CHAPTER 3 CPU FUNCTION On-chip peripheral I/O area (4 KB) ...

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CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map Access-prohibited area (program fetch disabled area) Internal RAM area (60 KB) 3FF0000H 3FEFFFFH Access-prohibited area (program fetch disabled area) Internal ROM area (1 MB) ...

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Areas (1) Internal ROM area An area from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in the Addresses ...

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Internal RAM area An area maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area area from 3FFD800H to 3FFEFFFH is provided as physical internal RAM for the V850ES/IE2. Addresses 3FF0000H ...

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CHAPTER 3 CPU FUNCTION (c) Internal memory size setting register (IMS) The IMS register is used to set the internal RAM size of the V850ES/IE2. This register is write-only, in 8-bit units. Reset sets this register to 00H. Cautions 1. ...

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On-chip peripheral I/O area area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Physical address space 3FFFFFFH 3FFF000H On-chip peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode ...

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Recommended use of address space The architecture of the V850ES/IE2 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The ±32 KB area of addresses ...

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Application example of wraparound (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can ...

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Figure 3-8. Recommended Memory Map Program space FFFFFFFFH FFFFF000H FFFFEFFFH FFFF0000H FFFEFFFFH 03FFFFFFH On-chip peripheral I/O 03FFF000H 03FFEFFFH Internal RAM 03FFD800H 03FFD7FFH 03FF0000H 03FEFFFFH Program space 64 MB Access-prohibited 0 0 ...

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On-chip peripheral I/O registers Address Function Register Name FFFFF004H Port DL register L FFFFF024H Port DL mode register L FFFFF06EH System wait control register FFFFF100H Internal mask register 0 FFFFF100H Interrupt mask register 0L FFFFF101H Interrupt mask register 0H ...

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Address Function Register Name FFFFF158H Interrupt control register FFFFF15AH Interrupt control register FFFFF15CH Interrupt control register FFFFF15EH Interrupt control register FFFFF168H Interrupt control register FFFFF16AH Interrupt control register FFFFF16CH Interrupt control register FFFFF16EH Interrupt control register FFFFF170H Interrupt control register ...

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Address Function Register Name FFFFF310H External interrupt noise elimination control register FFFFF400H Port 0 register FFFFF402H Port 1 register FFFFF404H Port 2 register FFFFF406H Port 3 register FFFFF408H Port 4 register FFFFF420H Port 0 mode register FFFFF422H Port 1 mode ...

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Address Function Register Name FFFFF60CH TMQ1 capture/compare register 3 FFFFF60EH TMQ1 counter read buffer register FFFFF620H TMQ1 option register 1 FFFFF621H TMQ1 option register 2 FFFFF622H TMQ1 I/O control register 3 FFFFF623H TMQ1 option register 3 FFFFF624H TMQ1 dead-time compare ...

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Address Function Register Name FFFFF802H System status register FFFFF820H Power save mode register FFFFF822H Clock control register FFFFF828H Processor clock control register FFFFF82CH PLL control register FFFFF870H Clock monitor mode register FFFFF888H Reset source flag register FFFFF890H Low-voltage detection register ...

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Address Function Register Name FFFFFD04H CSIB0 receive data register FFFFFD04H CSIB0 receive data register L FFFFFD06H CSIB0 transmit data register FFFFFD06H CSIB0 transmit data register L FFFFFF44H Pull-up resistor option register DLL CHAPTER 3 CPU FUNCTION Symbol R/W Bit Units ...

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Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/IE2 has the following seven special registers divided into two types. [Special registers subject to error report by ...

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Setting data to special registers Set data to the special registers in the following sequence. <1> Prepare data to be set to the special register in a general-purpose register. <2> Write the data prepared in <1> to the command ...

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Command register PRCMD is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. This register can be used ...

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System status register Status flags that indicate the operation status of the overall system are allocated to this register. This register can be used as SYS or SYS2 via a special register setting. (a) System status register (SYS) If ...

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The operating conditions of the PRERR flag are shown below. For the operating conditions of the PRERR2 flag, read PRCMD and SYS as PRCMD2 and SYS2 in the following explanation. (i) Set condition (PRERR flag = 1) • When data ...

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System wait control register (VSWC) The VSWC register is a register that controls the bus access wait for the on-chip peripheral I/O registers. Access to on-chip peripheral I/O registers of the V850ES CPU core is basically made in 3 ...

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Features I/O ports: 39 Input data read/output data write is enabled in 1-bit units. On-chip pull-up resistor can be connected in 1-bit units (ports and DL only) However, the on-chip pull-up resistor can be connected when ...

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Port Configuration Item Control registers Port n register (Pn DLL) Port n mode register (PMn DLL) Port n mode control register (PMCn Port n ...

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Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be ...

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Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. Each bit of this register corresponds to one pin ...

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Port settings Set the ports as follows. Figure 4-2. Register Settings and Pin Functions Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate function (when three or ...

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Port 0 Port 0 can be set to the input or output mode in 1-bit units. Port 0 has an alternate function as the following pins. Table 4-4. Alternate-Function Pins of Port 0 Pin Name Pin No. Note 2 ...

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A noise elimination function is included as an alternate function of port 0. P0n PMC0n bit P0m PMC0m bit P06 (specified by INTPNRC register) PMC06 bit Caution To control high-impedance output of the external interrupt function and motor output control ...

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Registers (a) Port 0 register (P0) After reset: Undefined P0 0 P06 P0n 0 Output 0. 1 Output 1. (b) Port 0 mode register (PM0) After reset: FFH R/W PM0 1 PM06 PM0n 0 Output mode 1 Input mode ...

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Port 0 mode control register (PMC0) After reset: 00H R/W PMC0 0 PMC06 PMC06 0 I/O port 1 INTP6 input PMC05 0 I/O port 1 INTP5 input/ADTRG1 input PMC04 0 I/O port 1 INTP4 input/ADTRG0 input PMC03 0 I/O ...

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Block diagrams Figure 4-3. Block Diagram of P00 to P05 Pins WR PU PU0 PU0n WR INTR INTR0 INTR0n WR INTF INTF0 INTF0n WR PMC PMC0 PMC0n WR PM PM0 PM0n WR PORT P0 P0n Address RD Noise elimination ...

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WR PU PU0 PU06 WR INTR INTR0 INTR06 WR INTF INTF0 INTF06 WR PMC PMC0 PMC06 WR PM PM0 PM06 WR PORT P0 P06 Address RD Noise elimination INTP6 input Edge detection 72 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block ...

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Port 1 Port 1 can be set to the input or output mode in 1-bit units. Port 1 has an alternate function as the following pins. Table 4-5. Alternate-Function Pins of Port 1 Pin Name Pin No. Note 2 ...

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Registers (a) Port 1 register (P1) After reset: Undefined P1 P17 P16 P1n 0 Output 0. 1 Output 1. (b) Port 1 mode register (PM1) After reset: FFH R/W PM1 PM17 PM16 PM1n 0 Output mode 1 Input mode ...

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CHAPTER 4 PORT FUNCTIONS (c) Port 1 mode control register (PMC1) After reset: 00H R/W PMC1 PMC17 PMC16 PMC17 0 I/O port 1 TOP21 output/TIP21 input PMC16 0 I/O port 1 TOQ00 (CLMER) output/TIP20 input PMC14 0 I/O port 1 ...

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Port 1 function control register (PFC1) After reset: 00H R/W PFC1 PFC17 PFC16 Remark For the specification of alternate function, see 4.3.2 (1) (f) Setting of alternate function of port 1. (e) Port 1 function control expansion register (PFCE1) ...

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CHAPTER 4 PORT FUNCTIONS (f) Setting of alternate function of port 1 PFC17 Specification of alternate function of P17 pin 0 TOP21 output 1 TIP21 input PFC16 Specification of alternate function of P16 pin 0 TOQ00 (CLMER) output 1 TIP20 ...

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Pull-up resistor option register 1 (PU1) After reset: 00H R/W PU1 PU17 PU16 PU1n 0 Do not connect 1 Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port ...

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Block diagrams Figure 4-5. Block Diagram of P10 and P12 Pins WR PU PU1 PU1n Note 1 Note 2 WR PFCE PFCE1 PFCE1n WR PFC PFC1 PFC1n WR PMC PMC1 PMC1n WR PM PM1 PM1n TOQH01, TOQH02 outputs TOQ01, ...

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WR PU PU1 PU11 WR PFCE PFCE1 PFCE11 WR PFC PFC1 PFC11 WR PMC PMC1 PMC11 WR PM PM1 PM11 Setting prohibited TOQ02 output WR PORT P1 P11 Address RD TIQ02 input 80 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 Pin WR PU PU1 PU13 WR PFC PFC1 PFC13 WR PMC PMC1 PMC13 WR PM PM1 PM13 Setting prohibited WR PORT P1 P13 Address RD TIQ00 input User’s Manual U17716EJ2V0UD ...

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WR PU PU1 PU14 Note 1 Note 2 WR PFC PFC1 PFC14 WR PMC PMC1 PMC14 WR PM PM1 PM14 TOQH03 output WR PORT P1 P14 Address RD EVTQ0 input Notes 1. Output of high impedance setting signal from high ...

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Figure 4-9. Block Diagram of P16 Pin WR PU PU1 PU16 WR PFC PFC1 PFC16 WR PMC PMC1 PMC16 WR PM PM1 PM16 Note 1 WR PORT Note 2 TOQ00 (CLMER) output P1 P16 Address RD TIP20 input Notes 1. ...

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WR PU PU1 PU17 Note 1 Note 2 WR PFC PFC1 PFC17 WR PMC PMC1 PMC17 WR PM PM1 PM17 TOP21 output WR PORT P1 P17 Address RD TIP21 input Notes 1. Output of high impedance setting signal from high ...

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Port 2 Port 2 can be set to the input or output mode in 1-bit units. Port 2 has an alternate function as the following pins. Table 4-6. Alternate-Function Pins of Port 2 Pin Name Pin No. P20 54 ...

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Registers (a) Port 2 register (P2) After reset: Undefined P2 P27 P26 P2n 0 Output 0. 1 Output 1. (b) Port 2 mode register (PM2) After reset: FFH R/W PM2 PM27 PM26 PM2n 0 Output mode 1 Input mode ...

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CHAPTER 4 PORT FUNCTIONS (c) Port 2 mode control register (PMC2) After reset: 00H R/W PMC2 PMC27 PMC26 PMC27 0 I/O port 1 TOP31 output PMC26 0 I/O port 1 TOQ10 output PMC25 0 I/O port 1 TOQ1B3 output PMC24 ...

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Pull-up resistor option register 2 (PU2) After reset: 00H R/W PU2 PU27 PU26 PU2n 0 Do not connect 1 Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port ...

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Block diagram Figure 4-11. Block Diagram of P20 to P25 and P27 Pins WR PU PU2 PU2n Note 1 Note 2 WR PMC PMC2 PMC2n WR PM PM2 PM2n TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3, TOP31 output WR PORT ...

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WR PU PU2 PU26 WR PMC PMC2 PMC26 WR PM PM2 PM26 TOQ10 output WR PORT P2 P26 Address RD 90 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P26 Pin User’s Manual U17716EJ2V0UD P-ch P26/TOQ10 ...

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Port 3 Port 3 can be set to the input or output mode in 1-bit units. Port 3 has an alternate function as the following pins. Table 4-7. Alternate-Function Pins of Port 3 Pin Name Pin No. Note 2 ...

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Port 3 mode control register (PMC3) After reset: 00H R/W PMC3 0 PMC33 0 I/O port 1 TXDA1 output PMC32 0 I/O port 1 RXDA1 input PMC31 0 I/O port 1 TXDA0 output PMC30 0 I/O port 1 RXDA0 ...

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Pull-up resistor option register 3 (PU3) After reset: 00H R/W PU3 0 0 PU3n 0 Do not connect 1 Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port ...

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Block diagram WR PU PU3 PU30 WR PMC PMC3 PMC30 WR PM PM3 PM30 WR PORT P3 P30 Address RD RXDA0 input 94 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P30 Pin User’s Manual U17716EJ2V0UD P-ch P30/RXDA0 ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P31 Pin WR PU PU3 PU31 WR PMC PMC3 PMC31 WR PM PM3 PM31 TXDA0 output WR PORT P3 P31 Address RD User’s Manual U17716EJ2V0UD P-ch P31/TXDA0 95 ...

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WR PU PU3 PU32 WR PFC PFC3 PFC32 WR PMC PMC3 PMC32 WR PM PM3 PM32 WR PORT P3 P32 Address RD Setting prohibited RXDA1 input 96 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P32 Pin User’s Manual ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P33 Pin WR PU PU3 PU33 WR PFC PFC3 PFC33 WR PMC PMC3 PMC33 WR PM PM3 PM33 Setting prohibited TXDA1 output WR PORT P3 P33 Address RD User’s Manual U17716EJ2V0UD ...

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Port 4 Port 4 can be set to the input or output mode in 1-bit units. Port 4 has an alternate function as the following pins. Table 4-8. Alternate-Function Pins of Port 4 Pin Name Pin No. Note 2 ...

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CHAPTER 4 PORT FUNCTIONS (c) Port 4 mode control register (PMC4) After reset: 00H R/W PMC4 0 0 PMC44 0 I/O port 1 TOP01 output/TIP01 input PMC43 0 I/O port 1 TOP00 output/TIP00 input PMC42 0 I/O port 1 SCKB0 ...

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Pull-up resistor option register 4 (PU4) After reset: 00H PU4 0 PU4n 0 Do not connect 1 Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or ...

Page 103

Block diagram Figure 4-17. Block Diagram of P40 Pin WR PU PU4 PU40 WR PMC PMC4 PMC40 WR PM PM4 PM40 WR PORT P4 P40 Address RD SIB0 input CHAPTER 4 PORT FUNCTIONS User’s Manual U17716EJ2V0UD P-ch P40/SIB0 RESET ...

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WR PU PU4 PU41 WR PMC PMC4 PMC41 WR PM PM4 PM41 SOB0 output WR PORT P4 P41 Address RD 102 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P41 Pin User’s Manual U17716EJ2V0UD P-ch P41/SOB0 ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P42 Pin WR PU PU4 PU42 SCKB0 master mode WR PMC PMC4 PMC42 WR PM PM4 PM42 SCKB0 output WR PORT P4 P42 Address RD SCKB0 input User’s Manual U17716EJ2V0UD P-ch ...

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Figure 4-20. Block Diagram of P43 and P44 Pins WR PU PU4 PU4n WR PFC PFC4 PFC4n WR PMC PMC4 PMC4n WR PM PM4 PM4n TOP00, TOP01 outputs WR PORT P4 P4n Address RD TIP00, TIP01 inputs Remark n = ...

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Port DL Port DL can be set to the input or output mode in 1-bit units. Port DL has an alternate function as the following pins. Table 4-9. Alternate-Function Pins of Port DL Pin Name Pin No. PDL0 35 ...

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Registers (a) Port DL register L (PDLL) After reset: Undefined 7 PDLL PDL7 PDL6 PDLn 0 Output 0. 1 Output 1. (b) Port DL mode register L (PMDLL) After reset: FFH 7 PMDLL PMDL7 PMDL6 PMDLn 0 Output mode ...

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Block diagram Figure 4-21. Block Diagram of PDL0 to PDL7 Pins WR PU PUDLL PUDLn WR PM PMDLL PMDLn WR PORT PDLL PDLn Address RD Note This pin is used in the flash programming mode and does not have ...

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Output Data and Read Value of Port for Each Setting The following shows the values used to select the alternate function of the respective pins, output data and read value of each port for each setting. In addition to ...

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Table 4-10. Output Data and Port Read Value for Each Setting (1/4) Port Name Function PMCmn P00 to P06 Output port 0 Input port Note INTP0 to INTP5 , 1 INTP6 P10, P12 Output port 0 Input port TOQH01, TOQH02 ...

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Table 4-10. Output Data and Port Read Value for Each Setting (2/4) Port Name Function PMCmn P14 Output port 0 Input port TOQH03 1 EVTQ0 1 Note Note P16 (CLMER) , Output port 0 P17 Input port Note TOQ00 (CLMER) ...

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Table 4-10. Output Data and Port Read Value for Each Setting (3/4) Port Name Function PMCmn P32 Output port 0 Input port RXDA1 1 P33 Output port 0 Input port TXDA1 1 P40 Output port 0 Input port SIB0 1 ...

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Table 4-10. Output Data and Port Read Value for Each Setting (4/4) Port Name Function PMCmn P43, P44 Output port 0 Input port TOP00, TOP01 1 TIP00, TIP01 1 PDL0 to PDL4, Output port None Note PDL5 , PDL6, Input ...

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Port Register Settings When Alternate Function Is Used The following shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each ...

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Table 4-11. Using Port Pin as Alternate-Function Pin (1/3) Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P00 INTP0 Input P00 = Setting not required TOQH0OFF Input P00 = Setting not required P01 INTP1 Input P01 = ...

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Table 4-11. Using Port Pin as Alternate-Function Pin (2/3) Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P16 TOQ00 Output P16 = Setting not required Note Note (CLMER) (CLMER) TIP20 Input P16 = Setting not required P17 ...

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Table 4-11. Using Port Pin as Alternate-Function Pin (3/3) Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P43 TOP00 Output P43 = Setting not required TIP00 Input P43 = Setting not required P44 TOP01 Output P44 = ...

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Noise Eliminator A timing controller used to secure the noise elimination time is provided for the following pins. Input signals that change within the noise elimination time are not internally acknowledged. <R> Unit Reset RESET Mode pin FLMD0 • ...

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The following shows an example of digital noise elimination timing of the INTP6 pin. <R> Noise elimination clock Input signal Internal signal INTP6 rising edge detection INTP6 falling edge detection Caution If there are four or less noise elimination clocks ...

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External interrupt noise elimination control register (INTPNRC) The INTPNRC register is used to select the sampling clock that is used to eliminate digital noise on the INTP6 pin. If the same level is not detected five times in ...

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Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is ...

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Overview The features of clock generator are as follows. Oscillator • In PLL mode 2.5 MHz (f X • In clock-through mode 2.5 MHz (f X Multiply (×8 fixed) function by PLL (Phase Locked Loop) ...

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Configuration SELPLL bit Oscillator PLL X2 Oscillator stop control STOP mode Oscillation stabilization time wait control (OST) Caution Because f and f CPU CLK prescaler 2.5 MHz Remark f : ...

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Oscillator The main resonator oscillates the following frequencies (f • In PLL mode (×8 fixed 2.5 MHz (f X • In clock-through mode 2.5 MHz (f X (2) IDLE control All functions other than the ...

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Control Registers The clock generator is controlled by the following seven registers. • PLL control register (PLLCTL) • Clock control register (CKC) • Processor clock control register (PCC) • Power save control register (PSC) • Power save mode register ...

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Clock control register (CKC) The CKC register is used to control the PLL mode. Before using the PLL mode (PLLCTL.SELPLL bit = 1), be sure to set the CKC register to 0BH. Unless the CKC register has been set, ...

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Power save control register (PSC) The PSC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit ...

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Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation in the software standby mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ...

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Oscillation stabilization time select register (OSTS) The OSTS register selects the oscillation stabilization time until the oscillation stabilizes after the STOP mode is released by interrupt request. This register can be read or written in 8-bit units. Reset sets ...

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Clock monitor mode register (CLM) The CLM register sets the clock monitor operation mode. It can be written only in a combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or ...

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PLL Function 5.4.1 Overview The CPU and the operating clock of the peripheral macro can be switched between output of the oscillation frequency multiplied by 8, and clock-through mode. When PLL function is used: Input clock (f Clock-through mode: ...

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Operation 5.5.1 Operation of each clock The following table shows the operation status of each clock. Table 5-2. Operation Status of Each Clock Power Save Mode Normal operation During RESET pin input During oscillation stabilization time count HALT mode ...

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Operation timing (1) Power on (power-on reset RESET (input) <1> OST counter 00H (initialization) PLL output clock CPU reset signal X1 f CPU <1> The oscillator is activated by RESET release power application. PLL stops during the ...

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Reset input with power Note <1> Reset OST counter 00H (initialization) PLL output clock CPU reset signal X1 f CPU <1> PLL stops during the reset period and the oscillation stabilization time set using the ...

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When releasing STOP mode by interrupt request <1> STOP status In STOP mode OST counter 00H (initialization) PLL output clock X1 f CPU <1> When the STOP mode is set, both the oscillator and PLL stop. ...

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Clock Monitor (1) Function The clock monitor samples the clock generated by the oscillator (f When it detects an error (stop of oscillation), the output of the motor control timer goes into a high-impedance state. The CLMER signal (low ...

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Operation when oscillator is stopped (CLM.CLME bit = 1) If the oscillator is stopped when the CLME bit = 1, the CLMER signal is output from P16. Figure 5-2. When Oscillation of Main Clock Is Stopped Oscillator (f ) ...

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Timer P (TMP 16-bit timer/event counter. The V850ES/IE2 incorporates TMP0 to TMP3. 6.1 Overview The TMPn of channels are outlined below ( 3). Clock selection Capture trigger input pin External event count input pin External ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.3 Configuration TMPn includes the following hardware. Item 16-bit counter × 1 Timer register Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0 and CCR1 buffer registers ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP / / / /128 XX TIP00 TIP01 Remark f : Peripheral clock ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP / / / /128 XX TIP20 TIP21 TOP2OFF Remarks Peripheral clock XX ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP / / / /128 XX TOP3OFF Remarks Peripheral clock XX 2. For ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR1 register is used as a compare register, the value written to ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.4 Registers (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the TMPn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this ...

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TPnMD2 Note The settings that can be realized differ from one channel to another. For details, see Tables 6-8 to 6-11. Cautions 1. The TPmEST bit is valid only in the external trigger pulse output mode or one-shot pulse output ...

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TMPm I/O control register 0 (TPmIOC0) The TPmIOC0 register is an 8-bit register that controls the timer output (TOP00, TOPm1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ...

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Cautions 1. If the setting of the TPmIOC0 register is changed when TOP00 and TOPm1 are set in the output mode, the output of the pins change. Set the port in the input mode and make the port go ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPk I/O control register 1 (TPkIOC1) The TPkIOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIPk0, TIPk1 pins). This register can be read ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPk I/O control register 2 (TPkIOC2) The TPkIOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (TIPk0 pin) and external trigger input signal ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow. This register can be read or written in 8-bit or 1-bit units. ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TP0CCR0 and TP2CCR0 registers are 16-bit registers that can be used as capture registers or compare registers depending on the mode. The TP1CCR0 and TP3CCR0 registers ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TP0CCR1 and TP2CCR1 registers are 16-bit registers that can be used as capture registers or compare registers depending on the mode. The TP1CCR1 and TP3CCR1 registers ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5 Timer Output Operations The following table shows the operations and output levels of the TOP00 and TOPm1 pins. Table 6-6. Timer Output Control in Each Mode Operation Mode Interval timer mode External ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6 Operation The functions of TMPn that can be realized differ from one channel to another. The functions of each channel are shown below. Table 6-8. TMP0 Specifications in Each Mode Operation TP0CTL1.TP0EST ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Table 6-10. TMP2 Specifications in Each Mode Operation TP2CTL1.TP2EST Bit (Software Trigger Bit) Interval timer mode Invalid Note 1 External event count mode Invalid External trigger pulse output Valid Note 2 mode Note ...

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Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark <R> (a) Counting start ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Interrupt operation TMPn generates the following three types of interrupt request signals. • INTTPnCC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-6. Timing of Anytime Write TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register 0000H TPnCCR1 register CCR1 buffer register 0000H INTTPnCC0 signal INTTPnCC1 signal Remarks 1. D ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Batch write In this mode, data is transferred all at once from the TPmCCR0 and TPmCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-7. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TPmCCRa register • Timer operation enable (TPmCE bit = 1) → Transfer values of TPmCCRa register to ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) TPmCE bit = 1 FFFFH 16-bit counter 0000H TPmCCR0 register CCR0 buffer register 0000H TPmCCR1 register CCR1 buffer register 0000H INTTPmCC0 signal INTTPmCC1 signal TOP00 pin output TOP01 pin output Notes 1. Because ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the interval set by the TPnCCR0 register if the TPnCTL0.TPnCE ...

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When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. Additionally, the set value of the TPnCCR0 register is ...

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Figure 6-11. Register Setting for Interval Timer Mode Operation (2/3) (c) TMPm I/O control register 0 (TPmIOC0) TPmIOC0 0 <R> (d) TMPk I/O control register 2 (TPkIOC2) TPkIOC2 0 Note Enable setting of the TPkEES1 and TPkEES0 bits only when ...

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Figure 6-11. Register Setting for Interval Timer Mode Operation (3/3) (g) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is not used in the interval timer mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 ...

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Interval timer mode operation flow Figure 6-12. Software Processing Flow in Interval Timer Mode (1/2) 16-bit counter TPnCE bit TPnCCR0 register TOP00 pin output INTTPnCC0 signal <1> Count operation start flow Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-12. Software Processing Flow in Interval Timer Mode (2/2) <2> Count operation stop flow TPnCE bit = 0 STOP Remark (2) Interval ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register Figure 6-13. Configuration of TPnCCR1 Register Count clock selection TPnCE bit Remark TPnCCR1 register Output CCR1 buffer register ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCCR1 register is set to the same value as the TPnCCR0 register, the INTTPnCC1 signal is generated at the same timing as the INTTPnCC0 signal and the TOPm1 pin output is ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 ...

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Operation by external event count input (TIPk0) (a) Operation To count the 16-bit counter at the valid edge of external event count input (TIPk0) in the interval timer mode, clear the 16-bit counter from FFFFH to 0000H at ...

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External event count mode (TPkMD2 to TPkMD0 bits = 001) This mode is valid only in TMP0 and TMP2. In the external event count mode, the valid edge of the external event count input (TIPk0) is counted when the ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-17. Basic Timing in External Event Count Mode FFFFH D 0 16-bit counter 0000H TPkCE bit TPkCCR0 register INTTPkCC0 signal External event count Note ( Note In the external event ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPkCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input ...

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Figure 6-18. Register Setting for Operation in External Event Count Mode (2/2) (f) TMPk capture/compare register 1 (TPkCCR1) The TPkCCR1 register is not used in the external event count mode. However, the set value of the TPkCCR1 register is transferred ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 6-19. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPkCE bit TPkCCR0 register INTTPkCC0 signal <1> Count operation start flow ...

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Operation timing in external event count mode Cautions 1. In the external event count mode, the TPkCCR0 and TPkCCR1 registers must not be cleared to 0000H. <R> the external event count mode, use of the timer output ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPkCCR0 register If the value of the TPkCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When the overflow may occur, stop ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPkCCR1 register Figure 6-20. Configuration of TPkCCR1 Register TIPk0 pin Edge (external event detector count input) TPkCE bit Remark the set value of the TPkCCR1 ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPkCCR1 register is greater than the set value of the TPkCCR0 register, the INTTPkCC1 signal is not generated because the count value of the 16-bit counter and ...

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External trigger pulse output mode (TPmMD2 to TPmMD0 bits = 010) This mode is valid only in TMP0, TMP2, and TMP3 (software trigger only for TMP3). In the external trigger pulse output mode, 16-bit timer/event counter P waits for ...

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FFFFH 16-bit counter 0000H TPmCE bit External trigger input (TIPk0 pin input) TPmCCR0 register INTTPmCC0 signal TOP00 pin output <R> (only when using software trigger) TPmCCR1 register INTTPmCC1 signal TOPm1 pin output 16-bit timer/event counter P waits for a trigger ...

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Figure 6-25. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPm control register 0 (TPmCTL0) TPmCE TPmCTL0 0/1 0 <R> (b) TMPm control register 1 (TPmCTL1) TPmEST <R> TPmCTL1 0 0/1 (c) TMPm I/O control register 0 ...

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Figure 6-25. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMPk I/O control register 2 (TPkIOC2) <R> TPkIOC2 0 (e) TMPm counter read buffer register (TPmCNT) The value of the 16-bit counter can be read by reading ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 6-26. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter D 0000H TPmCE bit External trigger input (TIPk0 pin ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-26. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow START Initial setting of these Register initial setting registers is performed TPmCTL0 register before setting the ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPmCCR1 register last. Rewrite the ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPmCCRa register to the CCRa buffer register, the TPmCCR1 register must be written. To change both the cycle and active level width of the PWM waveform ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPmCCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTPmCC0 and INTTPmCC1 signals are generated at ...

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To output a 100% waveform, set a value of (set value of TPmCCR0 register + 1) to the TPmCCR1 register. If the set value of the TPmCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TPmCE ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the INTTPmCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTPmCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPmCC1) The timing of generation of the INTTPmCC1 signal in the external trigger pulse output mode differs from the timing of INTTPmCC1 signals in ...

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