LM3S2730-IBZ50-A2T

Manufacturer Part NumberLM3S2730-IBZ50-A2T
DescriptionIC ARM CORTEX MCU 128KB 108NFBGA
ManufacturerTexas Instruments
SeriesStellaris® 2000
LM3S2730-IBZ50-A2T datasheets
 


Specifications of LM3S2730-IBZ50-A2T

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed50MHzConnectivityCAN, IrDA, Microwire, SPI, SSI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o60
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size64K x 8Voltage - Supply (vcc/vdd)2.25 V ~ 2.75 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case108-NFBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
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S T E L L A R I S E R R A T A
®
Stellaris
LM3S2730 RevA2 Errata
This document contains known errata at the time of publication for the Stellaris
microcontroller. The table below summarizes the errata and lists the affected revisions. See the
data sheet for more details.
See also the ARM® Cortex™-M3 errata, ARM publication number PR326-PRDC-009450 v2.0.
Date
Revision
Description
September 2010
2.10
Minor edits and clarifications.
July 2010
2.9
Added issue “The RTRIS bit in the UARTRIS register is only set when the interrupt is
enabled” on page 10.
June 2010
2.8
Added issue “External reset does not reset the XTAL to PLL Translation (PLLCFG)
register” on page 4.
May 2010
2.7
Minor edits and clarifications.
April 2010
2.6
Minor edits and clarifications.
April 2010
2.5
Minor edits and clarifications.
February 2010
2.4
Added issue “The General-Purpose Timer match register does not function correctly in 32-bit
mode” on page 9.
Jan 2010
2.3
"Hard Fault possible when waking from Sleep or Deep-Sleep modes and Cortex-M3 Debug Access
Port (DAP) is enabled" has been removed and the content added to the LM3S2730 data sheet.
Dec 2009
2.2
Started tracking revision history.
Erratum
Number
1.1
JTAG pins do not have internal pull-ups enabled at power-on reset
1.2
JTAG INTEST instruction does not work
2.1
Clock source incorrect when waking up from Deep-Sleep mode in some configurations
2.2
PLL may not function properly at default LDO setting
2.3
I/O buffer 5-V tolerance issue
2.4
PLL Runs Fast When Using a 3.6864-MHz Crystal
2.5
External reset does not reset the XTAL to PLL Translation (PLLCFG) register
3.1
Hibernation module WAKE input pin does not work as specified
3.2
Hibernation module low VBAT detection does not work as expected
3.3
Performing a system-wide reset also resets the Hibernation module and all of its registers
Hibernation module may have higher current draw than specified in data sheet under
3.4
certain conditions
September 05, 2010/Rev. 2.10
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
Erratum Title
®
LM3S2730
Revision(s) Affected
A1, A2
A1, A2
A1, A2
A1, A2
A1, A2
A1, A2
A1, A2
A1
A1, A2
A1, A2
A1, A2
1
Texas Instruments

LM3S2730-IBZ50-A2T Summary of contents

  • Page 1

    ... Jan 2010 2.3 ■ "Hard Fault possible when waking from Sleep or Deep-Sleep modes and Cortex-M3 Debug Access Port (DAP) is enabled" has been removed and the content added to the LM3S2730 data sheet. Dec 2009 2.2 Started tracking revision history. Erratum Number 1 ...

  • Page 2

    ... Stellaris LM3S2730 A2 Errata Erratum Number Hibernation module returns from the Hibernation state to the Wake state regardless of 3.5 the status of the VDD supply to the microcontroller 3.6 Certain Hibernation module register writes cause RTC Counter register inaccuracy 3.7 Hibernation module state retention registers may corrupt after Wake sequence 4 ...

  • Page 3

    ... In designs that enable and use the PLL module, unstable device behavior may occur with the LDO set at its default of 2.5 volts or below (minimum of 2.25 volts). Designs that do not use the PLL module are not affected. September 05, 2010/Rev. 2.10 http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm ® Stellaris LM3S2730 A2 Errata 3 Texas Instruments ...

  • Page 4

    ... Stellaris LM3S2730 A2 Errata Workaround: Prior to enabling the PLL module recommended that the default LDO voltage setting of 2 adjusted to 2.75 V using the LDO Power Control (LDOPCTL) register. Silicon Revision Affected: A1, A2 2.3 I/O buffer 5-V tolerance issue Description: GPIO buffers are not 5-V tolerant when used in open-drain mode. Pulling up the open-drain pin above 4 V results in high current draw ...

  • Page 5

    ... SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register also incorrectly causes the Hibernation module to be reset. All of the Hibernation module September 05, 2010/Rev. 2.10 http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm Stellaris condition. This feature is enabled by setting BAT condition at 3.15 V. This is supposed to trigger a low V BAT ® LM3S2730 A2 Errata BAT BAT 5 Texas Instruments ...

  • Page 6

    ... Stellaris LM3S2730 A2 Errata registers are reset, including the non-volatile Hibernation Data (HIBDATA) and the Hibernation RTC Counter (HIBRTCC) registers. Workaround: None. Silicon Revision Affected: A1, A2 3.4 Hibernation module may have higher current draw than specified in data sheet under certain conditions ...

  • Page 7

    ... Hibernation sequence. Immediately upon returning from the Hibernation state to the Wake-up state, software should write the data mirrored from the HIBDATA registers back into the HIBCTL and HIBIM registers. Silicon Revision Affected: A1, A2 September 05, 2010/Rev. 2.10 http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm ® Stellaris LM3S2730 A2 Errata 7 Texas Instruments ...

  • Page 8

    ... Stellaris LM3S2730 A2 Errata 4 GPIO 4.1 GPIO input pin latches in the Low state if pad type is open drain Description: GPIO pins function normally if configured as inputs and the open-drain configuration is disabled. If open drain is enabled while the pin is configured as an input using the GPIO Alternate Function ...

  • Page 9

    ... Description: The GPTM Timer A Match (GPTMTAMATCHR) register triggers a match interrupt when the lower 16 bits match, regardless of the value of the upper 16 bits. Workaround: None. Silicon Revision Affected: A1, A2 September 05, 2010/Rev. 2.10 http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm ® Stellaris LM3S2730 A2 Errata 9 Texas Instruments ...

  • Page 10

    ... Stellaris LM3S2730 A2 Errata 6 UART 6.1 The RTRIS bit in the UARTRIS register is only set when the interrupt is enabled Description: The RTRIS (UART Receive Time-Out Raw Interrupt Status) bit in the UART Raw Interrupt Status (UARTRIS) register should be set when a receive time-out occurs, regardless of the state of the enable RTIM bit in the UART Interrupt Mask (UARTIM) register ...

  • Page 11

    ... CAN controller that is being accessed during read accesses. Whatever method is used, it must be sure to protect against any asynchronous code that accesses the same CAN controller as the code that it interrupts. September 05, 2010/Rev. 2.10 http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm ® Stellaris LM3S2730 A2 Errata ® 11 Texas Instruments ...

  • Page 12

    ... Stellaris LM3S2730 A2 Errata Silicon Revision Affected: A1, A2 Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. ...

  • Page 13

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...