UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet
UPD70F3736GK-GAK-AX
Specifications of UPD70F3736GK-GAK-AX
Available stocks
Related parts for UPD70F3736GK-GAK-AX
UPD70F3736GK-GAK-AX Summary of contents
Page 1
Preliminary User’s Manual V850ES/JF3-L 32-bit Single-Chip Microcontrollers Hardware μ PD70F3735 μ PD70F3736 Document No. U18952EJ1V0UD00 (1st edition) Date Published February 2008 N 2008 Printed in Japan ...
Page 2
Preliminary User’s Manual U18952EJ1V0UD ...
Page 3
NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
Page 4
IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America. EEPROM is a trademark of ...
Page 5
The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the ...
Page 6
Readers This manual is intended for users who wish to understand the functions of the V850ES/JF3-L and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JF3-L ...
Page 7
Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...
Page 8
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JF3-L V850ES Architecture User’s Manual V850ES/JF3-L Hardware User’s Manual Documents related to development tools QB-V850ESSX2 In-Circuit ...
Page 9
CHAPTER 1 INTRODUCTION .................................................................................................................18 1.1 General .....................................................................................................................................18 1.2 Features....................................................................................................................................20 1.3 Application Fields ...................................................................................................................21 1.4 Ordering Information ..............................................................................................................21 1.5 Pin Configuration (Top View) .................................................................................................22 1.6 Function Block Configuration................................................................................................24 1.6.1 Internal block diagram ............................................................................................................... 24 1.6.2 Internal units .............................................................................................................................. 25 CHAPTER 2 ...
Page 10
Port DH ....................................................................................................................................109 4.3.11 Port DL ....................................................................................................................................110 4.4 Block Diagrams..................................................................................................................... 113 4.5 Port Register Settings When Alternate Function Is Used ................................................ 141 4.6 Cautions ................................................................................................................................ 148 4.6.1 Cautions on setting port pins ...................................................................................................148 4.6.2 Cautions on bit manipulation instruction ...
Page 11
Functions ...............................................................................................................................189 7.3 Configuration .........................................................................................................................190 7.4 Registers ................................................................................................................................192 7.5 Operation................................................................................................................................204 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............................................................. 205 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001)................................................. 215 7.5.3 External trigger pulse output mode ...
Page 12
Functions............................................................................................................................... 394 11.2 Configuration ........................................................................................................................ 395 11.3 Registers ............................................................................................................................... 396 11.4 Operation............................................................................................................................... 398 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 399 12.1 Function................................................................................................................................. 399 12.2 Configuration ........................................................................................................................ 400 12.3 Registers ............................................................................................................................... 402 12.4 Operation............................................................................................................................... 404 12.5 Usage ..................................................................................................................................... 405 12.6 ...
Page 13
UART reception ....................................................................................................................... 467 15.6.8 Reception errors ...................................................................................................................... 468 15.6.9 Parity types and operations ..................................................................................................... 470 15.6.10 Receive data noise filter .......................................................................................................... 471 15.7 Dedicated Baud Rate Generator ..........................................................................................472 15.8 Cautions .................................................................................................................................480 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ...
Page 14
I C Interrupt Request Signals (INTIICn) .............................................................................. 562 17.7.1 Master device operation...........................................................................................................562 17.7.2 Slave device operation (when receiving slave address data (address match))........................565 17.7.3 Slave device operation (when receiving extension code) ........................................................569 17.7.4 Operation without communication............................................................................................573 17.7.5 Arbitration ...
Page 15
In-service priority register (ISPR)............................................................................................. 651 19.3.7 ID flag ...................................................................................................................................... 652 19.3.8 Watchdog timer mode register 2 (WDTM2) ............................................................................. 652 19.4 Software Exception ...............................................................................................................653 19.4.1 Operation................................................................................................................................. 653 19.4.2 Restore.................................................................................................................................... 654 19.4.3 EP flag..................................................................................................................................... 655 19.5 Exception Trap ......................................................................................................................656 19.5.1 Illegal ...
Page 16
Overview................................................................................................................................ 699 22.2 Registers to Check Reset Source....................................................................................... 700 22.3 Operation............................................................................................................................... 701 22.3.1 Reset operation via RESET pin ...............................................................................................701 22.3.2 Reset operation by watchdog timer 2.......................................................................................704 22.3.3 Reset operation by low-voltage detector..................................................................................706 22.3.4 Operation after reset release ...................................................................................................707 22.3.5 ...
Page 17
Overview ................................................................................................................................. 747 28.5.2 Features .................................................................................................................................. 748 28.5.3 Standard self programming flow .............................................................................................. 749 28.5.4 Flash functions ........................................................................................................................ 750 28.5.5 Pin processing ......................................................................................................................... 750 28.5.6 Internal resources used ........................................................................................................... 751 CHAPTER 29 ON-CHIP DEBUG FUNCTION......................................................................................752 29.1 Debugging with DCU.............................................................................................................753 ...
Page 18
The V850ES/JF3-L is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 General The V850ES/JF3 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions ...
Page 19
Generic Name Part Number Internal Flash memory memory RAM Memory Logical space space External memory area External bus interface Address bus: 18 Address data bus: 16 Multiplexed bus mode output supported 32 bits × 32 registers General-purpose register Clock Main ...
Page 20
Features Minimum instruction execution time (operating with main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 × 32 → 64): ...
Page 21
Internal oscillation clock: 220 kHz (TYP.) Power-save functions: HALT/IDLE1/IDLE2/STOP/low-voltage STOP mode/subclock/sub-IDLE/ low-voltage subclock/low-voltage sub-IDLE mode 80-pin plastic LQFP (fine pitch) (12 × 12) Package: 80-pin plastic LQFP (14 × 14) 1.3 Application Fields Digital cameras, power meters, mobile terminals, digital ...
Page 22
Pin Configuration (Top View) 80-pin plastic LQFP (fine pitch) (12 × 12) 80-pin plastic LQFP (14 × 14) μ PD70F3735GK-GAK-AX μ PD70F3736GK-GAK- ...
Page 23
Pin names A16, A17: Address bus AD0 to AD15: Address/data bus ADTRG: A/D trigger input Analog input ANI0 to ANI7: ANO0: Analog output ASCKA0: Asynchronous serial clock ASTB: Address strobe Analog reference voltage REF0 REF1 Analog ...
Page 24
Function Block Configuration 1.6.1 Internal block diagram NMI INTC INTP to INTP7 16-bit timer/ TIQ00 to TIQ03 counter Q: TOQ00 to TOQ03 1 ch TIP00 to TIP20, TIP50 16-bit timer/ TIP01 to TIP21, TIP51 counter P: TOP00 to TOP20, ...
Page 25
Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
Page 26
Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates ...
Page 27
Ports The following general-purpose port functions and control pin functions are available. Port I/O P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset P1 1-bit I/O D/A converter analog output P3 8-bit I/O External interrupt, serial interface, ...
Page 28
List of Pin Functions The names and functions of the pins in the V850ES/JF3-L are described below. There are three types of pin I/O buffer power supplies: AV power supplies and the pins is described below. Power Supply AV ...
Page 29
Port pins Pin Name Pin No. I/O P02 17 I/O Port 0 5-bit I/O port P03 5 Input/output can be specified in 1-bit units. P04 6 N-ch open-drain output can be specified in 1-bit units. Note P05 18 5 ...
Page 30
Pin Name Pin No. I/O P90 38 I/O Port 9 9-bit I/O port P91 39 Input/output can be specified in 1-bit units. P96 40 N-ch open-drain output can be specified in 1-bit units. P97 tolerant. (only P90, ...
Page 31
Non-port pins Pin Name Pin No. I/O A16 89 Output Address bus for external memory A17 90 AD0 55 I/O Address bus/data bus for external memory AD1 56 AD2 57 AD3 58 AD4 59 AD5 60 AD6 61 AD7 ...
Page 32
Pin Name Pin No. I/O DRST 18 Input Debug reset input tolerant. − Positive power supply for external (same potential − Ground potential for external (same potential FLMD0 ...
Page 33
Pin Name Pin No. I/O SCKB0 21 I/O Serial clock I/O (CSIB0 to CSIB2) N-ch open-drain output selectable. SCKB1 tolerant (SCKB0, SCKB2 only). SCKB2 37 SCL00 29 I/O Serial clock I/O (I N-ch open-drain output selectable. SCL01 ...
Page 34
Pin Name Pin No. I/O TOQ00 35 Output Timer output (TMQ0) N-ch open-drain output selectable tolerant. TOQ01 32 TOQ02 33 TOQ03 34 TXDA0 22 Output Serial transmit data output (UARTA0 to UARTA2) N-ch open-drain output selectable. TXDA1 38 ...
Page 35
Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Pin Name When Power During Reset Is Turned (Except When Note 1 On Power Is Turned On) ...
Page 36
Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins Pin Alternate Function P02 NMI P03 INTP0/ADTRG P04 INTP1 P05 INTP2/DRST P06 INTP3 P10 ANO0 P30 TXDA0 P31 RXDA0/INTP7 P32 ASCKA0/TIP00 P33 TIP01/TOP01 P34 TIP10/TOP10 P35 ...
Page 37
Pin Alternate Function P90 KR6/TXDA1 P91 KR7/RXDA1 P96 TIP21/TOP21 P97 SIB1/TIP20/TOP20 P98 SOB1 P99 SCKB1 P913 INTP4 P914 INTP5/TIP51/TOP51 P915 INTP6/TIP50/TOP50 PCM0 WAIT PCM1 CLKOUT PCM2 HLDAK PCM3 HLDRQ PCT0, PCT1 WR0, WR1 PCT4 RD PCT6 ASTB PDH0, PDH1 A16, ...
Page 38
Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5 EV Data Output disable Input enable Type 10-D Data Open drain Output disable Note Input enable Type 10-G Data Open drain Output disable Input enable Note Hysteresis characteristics are not ...
Page 39
Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P10/ANO0 pin • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin CHAPTER 2 PIN FUNCTIONS Preliminary User’s Manual U18952EJ1V0UD 39 ...
Page 40
The CPU of the V850ES/JF3-L is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time (operating with main clock (f Memory space Program (physical ...
Page 41
CPU Register Set The registers of the V850ES/JF3-L can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program ...
Page 42
Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data variable ...
Page 43
System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. ...
Page 44
Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to ...
Page 45
NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those ...
Page 46
Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this ...
Page 47
Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a ...
Page 48
Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the ...
Page 49
Operation Modes The V850ES/JF3-L has the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the ...
Page 50
Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) ...
Page 51
Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a ...
Page 52
Memory map The areas shown below are reserved in the V850ES/JF3-L. Figure 3-2. Data Memory Map (Physical Addresses (64 KB ...
Page 53
...
Page 54
Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (128 KB) 128 KB are allocated to addresses 00000000H to 0001FFFFH in the Accessing addresses 00020000H to 000FFFFFH is prohibited. ...
Page 55
Internal RAM area are reserved as the internal RAM area. (a) Internal RAM (8 KB are allocated to addresses 03FFD000H to 03FFEFFFH of the Accessing addresses 03FF0000H to 03FFCFFFH is prohibited. Figure 3-6. ...
Page 56
On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Physical address space ...
Page 57
Recommended use of address space The architecture of the V850ES/JF3-L requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ...
Page 58
Data space With the V850ES/JF3-L, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25 26-bit address is sign-extended to 32 bits and ...
Page 59
Figure 3-9. Recommended Memory Map Program space ...
Page 60
Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H FFFFF006H Port DH register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF024H Port DL mode register FFFFF024H ...
Page 61
Address Function Register Name FFFFF0D2H DMA addressing control register 1 FFFFF0D4H DMA addressing control register 2 FFFFF0D6H DMA addressing control register 3 FFFFF0E0H DMA channel control register 0 FFFFF0E2H DMA channel control register 1 FFFFF0E4H DMA channel control register 2 ...
Page 62
Address Function Register Name FFFFF14CH Interrupt control register FFFFF14EH Interrupt control register FFFFF150H Interrupt control register FFFFF1 H Interrupt control register 52 FFFFF1 H Interrupt control register 54 FFFFF156H Interrupt control register FFFFF158H Interrupt control register FFFFF15AH Interrupt control register ...
Page 63
Address Function Register Name FFFFF21CH A/D conversion result register 6 FFFFF21DH A/D conversion result register 6H FFFFF21EH A/D conversion result register 7 FFFFF21FH A/D conversion result register 7H FFFFF280H D/A conversion value setting register 0 FFFFF282H D/A converter mode register ...
Page 64
Address Function Register Name FFFFF446H Port 3 mode control register FFFFF446H Port 3 mode control register L FFFFF447H Port 3 mode control register H FFFFF448H Port 4 mode control register FFFFF44AH Port 5 mode control register FFFFF452H Port 9 mode ...
Page 65
Address Function Register Name FFFFF5A2H TMP1 I/O control register 0 FFFFF5A3H TMP1 I/O control register 1 FFFFF5A4H TMP1 I/O control register 2 FFFFF5A5H TMP1 option register 0 FFFFF5A6H TMP1 capture/compare register 0 FFFFF5A8H TMP1 capture/compare register 1 FFFFF5AAH TMP1 counter ...
Page 66
Address Function Register Name FFFFF810H DMA trigger factor register 0 FFFFF812H DMA trigger factor register 1 FFFFF814H DMA trigger factor register 2 FFFFF816H DMA trigger factor register 3 FFFFF820H Power save mode register FFFFF822H Clock control register FFFFF824H Lock register ...
Page 67
Address Function Register Name FFFFFC33H External interrupt rising edge specification register 9H INTR9H FFFFFC60H Port 0 function register FFFFFC66H Port 3 function register FFFFFC66H Port 3 function register L FFFFFC67H Port 3 function register H FFFFFC68H Port 4 function register ...
Page 68
Address Function Register Name FFFFFD90H IIC shift register 1 FFFFFD92H IIC control register 1 FFFFFD93H Slave address register 1 FFFFFD94H IIC clock select register 1 FFFFFD95H IIC function expansion register 1 FFFFFD96H IIC status register 1 FFFFFD9AH IIC flag register ...
Page 69
Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JF3-L has the following seven special registers. • Power save control register (PSC) • Clock control register (CKC) ...
Page 70
Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in ...
Page 71
Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first ...
Page 72
System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After ...
Page 73
Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JF3-L. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After ...
Page 74
Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus ...
Page 75
Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before ...
Page 76
Features I/O ports: 66 • tolerant/N-ch open-drain output selectable: 25 (ports (P90, P91, P96)) Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JF3-L features a total of 66 I/O ports ...
Page 77
Port Configuration Item Control register Port n mode register (PMn CM, CT, DH, DL) Port n mode control register (PMCn CM, CT, DH, ...
Page 78
Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be ...
Page 79
Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, ...
Page 80
Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in ...
Page 81
Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode “0” Input mode “1” Alternate function (when two alternate functions are available) Alternate function 1 “0” Alternate function ...
Page 82
Port 0 Port 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P02 17 NMI P03 5 INTP0/ADTRG P04 ...
Page 83
Port 0 mode register (PM0) After reset: FFH R/W PM0 1 PM06 PM0n 0 Output mode 1 Input mode (3) Port 0 mode control register (PMC0) After reset: 00H R/W PMC0 0 PMC06 PMC06 0 I/O port 1 INTP3 ...
Page 84
Port 0 function control register (PFC0) After reset: 00H R/W PFC0 0 PFC03 0 INTP0 input 1 ADTRG input (5) Port 0 function register (PF0) After reset: 00H R/W PF0 0 PF06 PF0n 0 Normal output (CMOS output) 1 ...
Page 85
Port 1 Port 1-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pin. Pin Name Pin No. Alternate-Function Pin Name P10 3 ANO0 Caution When the power ...
Page 86
Port 3 Port 8-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P30 22 TXDA0 P31 23 RXDA0/INTP7 P32 ...
Page 87
Port 3 register (P3) After reset: 0000H (output latch (P3H (P3L P3n 0 Outputs 0 1 Outputs 1 Caution Be sure to set bits 15 to 10, 7, and 6 to “0”. ...
Page 88
Port 3 mode control register (PMC3) After reset: 0000H 15 PMC3 (PMC3H) 0 (PMC3L) 0 PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 PMC30 0 1 ...
Page 89
Port 3 function control register (PFC3) After reset: 0000H 15 PFC3 (PFC3H) 0 (PFC3L) 0 Caution Be sure to set bits and 0 to “0”. Remarks 1. For details of alternate function specification, ...
Page 90
Port 3 alternate function specifications PFC39 0 RXDA2 input 1 SCL00 I/O PFC38 0 TXDA2 output 1 SDA00 I/O PFC35 0 TIP11 input 1 TOP11 output PFC34 0 TIP10 input 1 TOP10 output PFC33 0 TIP01 input 1 TOP01 ...
Page 91
Port 3 function register (PF3) After reset: 0000H 15 PF3 (PF3H) 0 (PF3L) 0 PF3n 0 Normal output (CMOS output) 1 N-ch open-drain output Cautions 1. When a pull-up resistor at EV PF3n bit sure ...
Page 92
Port 4 Port 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P40 19 SIB0/SDA01 P41 20 SOB0/SCL01 P42 21 SCKB0 Caution The ...
Page 93
Port 4 mode control register (PMC4) After reset: 00H R/W PMC4 0 0 PMC42 0 I/O port 1 SCKB0 I/O PMC41 0 I/O port 1 SOB0 output/SCL01 I/O PMC40 0 I/O port 1 SIB0 input/SDA01 I/O (4) Port 4 ...
Page 94
Port 5 Port 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P50 32 TIQ01/KR0/TOQ01/RTP00 P51 33 TIQ02/KR1/TOQ02/RTP01 P52 34 TIQ03/KR2/TOQ03/RTP02/DDI P53 35 ...
Page 95
Port 5 mode register (PM5) After reset: FFH R/W PM5 1 1 PM5n 0 Output mode 1 Input mode (3) Port 5 mode control register (PMC5) After reset: 00H R/W PMC5 0 0 PMC55 0 I/O port 1 SCKB2 ...
Page 96
Port 5 function control register (PFC5) After reset: 00H R/W PFC5 0 Remark For details of alternate function specification, see 4.3.5 (6) specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H R/W PFCE5 0 Remark For ...
Page 97
PFCE52 PFC52 PFCE51 PFC51 PFCE50 PFC50 Note KRn and TIQ0m are alternate functions. When using the ...
Page 98
Port 7 Port 8-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P70 80 ANI0 P71 79 ANI1 P72 ...
Page 99
Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-10. Port 9 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name P90 ...
Page 100
Port 9 mode register (PM9) After reset: FFFFH 15 PM9 (PM9H) PM915 (PM9L) PM97 PM9n 0 1 Caution Be sure to set bits and “1”. Remarks 1. The PM9 register can be ...
Page 101
Port 9 mode control register (PMC9) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 (PMC9L) PMC97 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC99 0 1 PMC98 0 1 PMC97 0 1 PMC96 0 1 PMC91 ...
Page 102
Port 9 function control register (PFC9) After reset: 0000H 15 PFC9 (PFC9H) PFC915 PFC914 (PFC9L) PFC97 Caution Be sure to set bits and “0”. Remarks 1. For details of alternate function specification, ...
Page 103
Port 9 alternate function specifications Caution When port 9 is specified as an alternate function by the PMC9.PMC9n bit with the PFC9 and PFCE9 registers maintaining the initial value, the output becomes undefined. Therefore, to specify port 9 as ...
Page 104
PFCE91 PFC91 PFCE90 PFC90 Note The RXDA1 and KR7 pins must not be used at the same time. When using the RXDA1 pin, do ...
Page 105
Port CM Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-11. Port CM Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PCM0 ...
Page 106
Port CM mode control register (PMCCM) After reset: 00H R/W PMCCM 0 PMCCM3 0 I/O port 1 HLDRQ input PMCCM2 0 I/O port 1 HLDAK output PMCCM1 0 I/O port 1 CLKOUT output PMCCM0 0 I/O port 1 WAIT ...
Page 107
Port CT Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-12. Port CT Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PCT0 ...
Page 108
Port CT mode control register (PMCCT) After reset: 00H R/W PMCCT 0 PMCCT6 PMCCT6 0 I/O port 1 ASTB output PMCCT4 0 I/O port 1 RD output PMCCT1 0 I/O port 1 WR1 output PMCCT0 0 I/O port 1 ...
Page 109
Port DH Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-13. Port DH Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name PDH0 ...
Page 110
Port DH mode control register (PMCDH) After reset: 00H R/W PMCDH 0 PMCDHn 0 I/O port 1 Am output (address bus output 16, 17) Caution Be sure to set bits “0”. 4.3.11 Port ...
Page 111
Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 PDL14 (PDLL) PDL7 PDL6 PDLn 0 Outputs 0 1 Outputs 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when ...
Page 112
Port DL mode control register (PMCDL) After reset: 0000H 15 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Remarks 1. The PMCDL register can be read or ...
Page 113
Block Diagrams PORT RD CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of Type A-1 PMmn Pmn Address P-ch A/D input signal N-ch Preliminary User’s Manual U18952EJ1V0UD Pmn 113 ...
Page 114
PORT RD 114 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A-2 PMmn Pmn Address P-ch D/A output signal N-ch Preliminary User’s Manual U18952EJ1V0UD Pmn ...
Page 115
CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type D-1 WR PMC PMCmn WR PM PMmn WR PORT Pmn Address Input signal when RD alternate function is used Preliminary User’s Manual U18952EJ1V0UD Pmn 115 ...
Page 116
WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn RD 116 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D-2 Address Preliminary User’s Manual U18952EJ1V0UD Pmn ...
Page 117
CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-3 WR PMC PMCmn Output enable signal of address/data bus Output buffer off signal WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address Input enable ...
Page 118
WR PF PFmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD 118 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type E-2 Preliminary User’s Manual U18952EJ1V0UD EV DD P-ch ...
Page 119
Figure 4-9. Block Diagram of Type E PFmn Output enable signal when alternate function is used WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate ...
Page 120
WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. ...
Page 121
CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR ...
Page 122
WR PF PFmn Output enable signal when alternate function is used WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address ...
Page 123
Figure 4-13. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal 1 when alternate function is used Input ...
Page 124
WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used ...
Page 125
Figure 4-15. Block Diagram of Type L PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when Edge detection alternate function is ...
Page 126
WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used detection Input signal 2 when ...
Page 127
Figure 4-17. Block Diagram of Type N PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address ...
Page 128
WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when detection alternate function is used Input signal 1-2 when alternate function is ...
Page 129
Figure 4-19. Block Diagram of Type U- PFmn Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT ...
Page 130
WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal 1-1 when RD ...
Page 131
Figure 4-21. Block Diagram of Type U PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
Page 132
WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging WR ...
Page 133
Figure 4-23. Block Diagram of Type U PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
Page 134
WR PF PFmn WR OCDM0 OCDM0 Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function ...
Page 135
Figure 4-25. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address RD Input signal 1 when Noise ...
Page 136
WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address RD KR7 RXDA1 Note Hysteresis characteristics are not available in port mode. 136 ...
Page 137
Figure 4-27. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address Input signal when RD alternate function ...
Page 138
WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address RD Input signal 1 when alternate function is used Input signal 2 when ...
Page 139
Figure 4-29. Block Diagram of Type U- PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used ...
Page 140
WR PF PFmn External reset signal WR OCDM0 OCDM0 WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when on-chip debugging Input signal when alternate function ...
Page 141
Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each ...
Page 142
Table 4-15. Settings When Port Pins Are Used for Alternate Functions (1/6) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O NMI Input P02 P02 = Setting not required INTP0 Input P03 P03 = Setting not required ADTRG ...
Page 143
Table 4-15. Settings When Port Pins Are Used for Alternate Functions (2/6) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Input P39 = Setting not required P39 RXDA2 I/O SCL00 P39 = Setting not required Input P40 ...
Page 144
Table 4-15. Settings When Port Pins Are Used for Alternate Functions (3/6) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Input P53 SIB2 P53 = Setting not required Input TIQ00 P53 = Setting not required Input KR3 ...
Page 145
Table 4-15. Settings When Port Pins Are Used for Alternate Functions (4/6) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P90 KR6 Input P90 = Setting not required TXDA1 Output P90 = Setting not required P91 KR7 ...
Page 146
Table 4-15. Settings When Port Pins Are Used for Alternate Functions (5/6) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PCM0 WAIT Input PCM0 = Setting not required PCM1 CLKOUT Output PCM1 = Setting not required PCM2 ...
Page 147
Table 4-15. Settings When Port Pins Are Used for Alternate Functions (6/6) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O I/O PDL8 AD8 PDL8 = Setting not required I/O PDL9 AD9 PDL9 = Setting not required PDL10 ...
Page 148
Cautions 4.6.1 Cautions on setting port pins (1) In the V850ES/JF3-L, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function ...
Page 149
CHAPTER 4 PORT FUNCTIONS The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order Setting Contents <1> Initial value (PMC41 bit = 0, PFC41 bit = ...
Page 150
Figure 4-31. Example of Switching from P02 to NMI (Incorrect) PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Remark [Example 2] Switch from external pin (NMI) to general-purpose ...
Page 151
Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is ...
Page 152
Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST high ...
Page 153
CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JF3-L is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features A multiplexed bus output with a minimum of 3 ...
Page 154
Bus Control Pins The pins used to connect an external device are listed in the table below. Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 A16, A17 PDH0, PDH1 WAIT PCM0 CLKOUT PCM1 WR0, WR1 PCT0, ...
Page 155
Memory Block Function The 16 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks ...
Page 156
Bus Access 5.4.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access Note ...
Page 157
Access by bus size The V850ES/JF3-L accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 ...
Page 158
Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) Address Byte data External data bus (b) 8-bit data bus width <1> Access to even address (2n) ...
Page 159
CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) Address Halfword data External data bus ...
Page 160
Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External data bus ...
Page 161
CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address ( First access Address Word ...
Page 162
Access to address (4n) First access Second access Address Word data External data Word ...
Page 163
CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address ( First access Second access Address ...
Page 164
Wait Function 5.5.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/ seven data wait states can be inserted in the bus cycle that is executed for ...
Page 165
External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is set ...
Page 166
Relationship between programmable wait and external wait Wait cycles are inserted as the result operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT ...
Page 167
Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each memory block area (memory blocks 0 to 3). If ...
Page 168
Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the memory block. By inserting an ...
Page 169
Bus Hold Function 5.7.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested ...
Page 170
Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK = ...
Page 171
Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), ...
Page 172
Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A17, A16 A1 ASTB WAIT AD15 to AD0 8-bit Access AD15 to AD8 AD7 to AD0 Remark The ...
Page 173
CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A17, A16 A1 ASTB WAIT A1 D1 AD15 to AD0 11 00 WR1, WR0 8-bit Access AD15 to AD8 AD7 ...
Page 174
Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT HLDRQ HLDAK A17, A16 AD15 to AD0 ASTB RD Note This idle state (TI) does not depend on the BCC register settings. ...
Page 175
CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode MHz ( MHz • In PLL mode f ...
Page 176
CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration FRC bit XT1 f Subclock XT oscillator XT2 MCK MFRC PLLON bit bit bit X1 f Main clock X PLL oscillator X2 Main clock oscillator stop control STOP mode SELPLL bit CLKOUT Port ...
Page 177
CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator Connecting the ceramic/crystal resonator to the X1 and X2 pins, the main clock oscillator oscillates to generates the following frequencies (f • In clock-through mode MHz ...
Page 178
CHAPTER 6 CLOCK GENERATION FUNCTION 6.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.7 Special registers). This register can ...
Page 179
CHAPTER 6 CLOCK GENERATION FUNCTION After reset: 03H R/W < > PCC FRC MCK FRC 0 Used 1 Not used MCK 0 Oscillation enabled 1 Oscillation stopped • Even if the MCK bit is set (1) while the system is ...
Page 180
CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the <3> MCK bit ...
Page 181
CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main ...
Page 182
CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset ...
Page 183
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock Register Setting and Operation Status During Reset Target Clock × Main ...
Page 184
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 PLL Function 6.5.1 Overview In the V850ES/JF3-L, an operating clock that is 4 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating ...
Page 185
CHAPTER 6 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.7 Special registers). The CKC register controls the ...
Page 186
CHAPTER 6 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). ...
Page 187
CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from This register can be ...
Page 188
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.3 Usage (1) When PLL is used • After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), ...
Page 189
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP 16-bit timer/event counter. The V850ES/JF3-L has eight timer/event counter channels, TMP0 to TMP2 and TMP5. 7.1 Overview An outline of TMPn is shown below. • Clock selection: • ...
Page 190
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.3 Configuration TMPn includes the following hardware. Item Timer register 16-bit counter Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0, CCR1 buffer registers Timer inputs 2 ...
Page 191
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, ...
Page 192
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.4 Registers The registers that control TMPn are as follows. • TMPn control register 0 (TPnCTL0) • TMPn control register 1 (TPnCTL1) • TMPn I/O control register 0 (TPnIOC0) • TMPn I/O control ...
Page 193
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets ...
Page 194
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) After reset: 00H 7 TPnCTL1 TPnEST 0 1 TPnEEE 0 1 The TPnEEE bit selects whether counting is performed with the internal count clock or the ...
Page 195
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit ...
Page 196
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). This register can be read ...
Page 197
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal ...
Page 198
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or ...
Page 199
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register ...
Page 200
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When ...