UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet
UPD70F3201YGC-YEU-A
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UPD70F3201YGC-YEU-A Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual V850ES/SA2, V850ES/SA3 32-Bit Single-Chip Microcontrollers Hardware V850ES/SA2: µ PD703200 µ PD703200Y µ PD703201 µ PD703201Y µ PD70F3201 µ PD70F3201Y Document No. U15905EJ2V1UD00 (2nd edition) Date Published August 2005 N CP(K) © Printed in Japan V850ES/SA3: µ PD703204 µ ...
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User’s Manual U15905EJ2V1UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of July, ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/SA2 ( V850ES/SA3 ( systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/SA2 ...
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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are ...
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CHAPTER 1 INTRODUCTION..................................................................................................................16 1.1 Overview....................................................................................................................................16 1.2 Features.....................................................................................................................................17 1.3 Application Fields.....................................................................................................................18 1.4 Ordering Information................................................................................................................19 1.4.1 V850ES/SA2 ...............................................................................................................................19 1.4.2 V850ES/SA3 ...............................................................................................................................19 1.5 Pin Configuration......................................................................................................................20 1.6 Function Block Configuration .................................................................................................24 1.6.1 Internal block diagram .................................................................................................................24 1.6.2 Internal units................................................................................................................................26 CHAPTER 2 PIN FUNCTIONS ................................................................................................................29 ...
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V850ES/SA2 ............................................................................................................................... 89 4.2.2 V850ES/SA3 ............................................................................................................................... 90 4.3 Port Configuration....................................................................................................................91 4.3.1 Port 0 .......................................................................................................................................... 92 4.3.2 Port 2 .......................................................................................................................................... 99 4.3.3 Port 3 ........................................................................................................................................ 106 4.3.4 Port 4 ........................................................................................................................................ 113 4.3.5 Port 7 ........................................................................................................................................ 123 4.3.6 Port 8 ........................................................................................................................................ ...
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Program space ..........................................................................................................................195 5.10.2 Data space ................................................................................................................................195 5.11 Bus Timing ............................................................................................................................. 196 CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 202 6.1 Overview................................................................................................................................. 202 6.2 Configuration ......................................................................................................................... 203 6.3 Control Registers................................................................................................................... 205 6.4 Operation................................................................................................................................ 208 6.4.1 Operation of each clock.............................................................................................................208 6.4.2 ...
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Controlling interrupt request signal output................................................................................. 267 9.3.4 Notes......................................................................................................................................... 267 CHAPTER 10 WATCHDOG TIMER FUNCTIONS...............................................................................269 10.1 Functions ................................................................................................................................269 10.2 Configuration ..........................................................................................................................271 10.3 Control Registers ...................................................................................................................271 10.4 Operation.................................................................................................................................274 10.4.1 Operation as watchdog timer .................................................................................................... 274 10.4.2 Operation as interval timer ........................................................................................................ ...
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Switching modes between CSI0 and I 14.1.2 Switching modes between CSI1 and UART0 ............................................................................334 14.2 Configuration ......................................................................................................................... 334 14.3 Control Registers................................................................................................................... 336 14.4 Operation................................................................................................................................ 342 14.5 Output Pins ............................................................................................................................ 345 14.6 System Configuration Example ........................................................................................... 346 2 CHAPTER 15 ...
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Transfer Object.......................................................................................................................420 16.7.1 Transfer type and transfer object .............................................................................................. 420 16.7.2 External bus cycles during DMA transfer (two-cycle transfer) ................................................... 420 16.8 DMA Channel Priorities .........................................................................................................421 16.9 DMA Transfer Start Factors ..................................................................................................421 16.10 DMA Transfer End ..................................................................................................................421 16.10.1 DMA ...
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Setting and operation status......................................................................................................462 18.3.2 Releasing IDLE mode................................................................................................................462 18.4 Software STOP Mode ............................................................................................................ 464 18.4.1 Setting and operation status......................................................................................................464 18.4.2 Releasing software STOP mode ...............................................................................................464 18.5 Securing Oscillation Stabilization Time .............................................................................. 466 18.6 Subclock Operation Mode .................................................................................................... 467 18.6.1 ...
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Communication command......................................................................................................... 497 21.7 Rewriting by Self Programming............................................................................................499 21.7.1 Overview ................................................................................................................................... 499 21.7.2 Features .................................................................................................................................... 500 CHAPTER 22 ELECTRICAL SPECIFICATIONS..................................................................................503 CHAPTER 23 PACKAGE DRAWINGS.................................................................................................532 CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS ...........................................................534 APPENDIX A REGISTER INDEX..........................................................................................................536 APPENDIX B INSTRUCTION SET LIST..............................................................................................543 ...
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The V850ES/SA2 and V850ES/SA3 are low-power models of the NEC Electronics V850 Series of single-chip microcontrollers for real-time control. 1.1 Overview The V850ES/SA2 and V850ES/SA3 are 32-bit single-chip microcontrollers that employ the V850ES CPU core and integrate peripheral functions such ...
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Features Number of instructions Minimum instruction execution time General-purpose registers Instruction set Memory space External bus interface Internal memory CHAPTER 1 INTRODUCTION 83 50 ns: Main clock = 20 MHz µ ( PD703200, 703201, 703204, 70F3201, 70F3204) 59 ns: ...
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Interrupts/exceptions I/O lines Timer/counter Real-time counter (for watch) Watchdog timer: Serial interface A/D converter D/A converter DMA controller: ROM correction: Clock generator Power save function Package 1.3 Application Fields Mobile devices requiring low power consumption Example DVC and portable audio ...
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Ordering Information 1.4.1 V850ES/SA2 Part Number µ 100-pin plastic TQFP (fine pitch) (14 × 14) PD703200GC-×××-YEU-A µ 100-pin plastic TQFP (fine pitch) (14 × 14) PD703200YGC-×××-YEU-A µ 100-pin plastic TQFP (fine pitch) (14 × 14) PD703201GC-×××-YEU-A µ 100-pin plastic ...
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Pin Configuration V850ES/SA2 100-pin plastic TQFP (fine pitch) (14 × 14) µ • PD703200GC-×××-YEU-A µ • PD703200YGC-×××-YEU-A Top view AV 1 REF0 P80/ANO0 4 P81/ANO1 REF1 P00/NMI 7 P30/SI1/RXD0 8 ...
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V850ES/SA3 121-pin plastic FGBA (12 × 12) µ PD703204F1-×××-EA6-A µ PD703204YF1-×××-EA6-A Top View Pin No. Name A1 P70/ANI0 A2 P71/ANI1 A3 P73/ANI3 A4 P713/ANI13 A5 P76/ANI6 A6 ...
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Pin No. Name G11 EV SS G12 PDL10/AD10 G13 XT2 H11 PDL8/AD8 Notes 1, 2 H12 IC/FLMD0 H13 PDL9/AD9 J1 P20/SI4 J2 P91/A1 J3 P90/A0 Note 1 J11 PDL5/AD5/FLMD1 J12 PDL7/AD7 ...
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Pin Identification A0 to A23: Address bus AD0 to AD15: Address/data bus ANI0 to ANI15: Analog input ANO0, ANO1: Analog output ASTB: Address strobe AV : Analog Analog reference voltage REF0 REF1 AV ...
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Function Block Configuration 1.6.1 Internal block diagram • V850ES/SA2 NMI INTC INTP0 to INTP6 INTP00, INTP01, INTP10, INTP11 Timer/counter TCLR0, TCLR1 16-bit timer TI0, TI1 TO0, TO1 Timer/counter TI2 to TI5 8-bit timer: TO2 to TO5 4 ...
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V850ES/SA3 NMI INTC INTP0 to INTP6 INTP00, INTP01, INTP10, INTP11 Timer/counter TCLR0, TCLR1 16-bit timer: TI0, TI1 2 ch TO0, TO1 Timer/counter TI2 to TI5 8-bit timer TO2 to TO5 SO0 to SO4 CSI: SI0 to SI4 ...
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Internal units (1) CPU The CPU can execute almost all instruction processing, such as address calculation, arithmetic logic operations, and data transfer, with 1 clock, using a 5-stage pipeline. The CPU has dedicated hardware units such as a multiplier ...
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Serial interface (SIO) The V850ES/SA2 and V850ES/SA3 have asynchronous serial interfaces (UART0 and UART1), clocked serial interfaces (V850ES/SA2: CSI0 to CSI3, V850ES/SA3: CSI0 to CSI4), and an I serial interfaces. The V850ES/SA2 can use up to four channels, and ...
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Ports Some port pins have a control function as well as a general-purpose port function, as shown below. Port I/O P0 6-bit I/O Note P2 3-bit I/O P3 3-bit I/O P4 7-bit I/O P7 12-bit input (V850ES/SA2) 16-bit input ...
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Pin Function List This chapter explains the names and functions of the pins in the V850ES/SA2 and V850ES/SA3, classified into port pins and non-port pins. Two power supplies are available for the pin I/O buffers: AV supplies and pins ...
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Port pins Pin Name I/O On-Chip Pull-up Resistor P00 I/O Provided P01 P02 P03 P04 P05 [P20] I/O Provided [P21] [P22] P30 I/O Provided P31 P32 P40 I/O Provided P41 P42 P43 P44 P45 P46 P70 Input None P71 ...
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Pin Name I/O On-Chip Pull-up Resistor P80 Input None P81 P90 I/O Provided P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 [PCD1] I/O None [PCD2] [PCD3] PCM0 I/O None PCM1 PCM2 PCM3 [PCM4] ...
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Pin Name I/O On-Chip Pull-up Resistor PDH0 I/O None PDH1 PDH2 PDH3 PDH4 PDH5 [PDH6] [PDH7] PDL0 I/O None PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 µ Note PD70F3201, 70F3201Y, 70F3204, and ...
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Non-port pins Pin Name I/O On-Chip Pull-up Resistor A0 Output Provided A10 A11 A12 A13 A14 A15 A16 to A21, Output None [A22, A23] AD0 to AD4 I/O None AD5 ...
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Pin Name I/O On-Chip Pull-up Resistor − − − AV Input REF0 AV REF1 − − CLKOUT Output None CS0 to CS3 Output None − − − − Note 1 FLMD0 Input ...
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Pin Name I/O On-Chip Pull-up Resistor SO0 Output Provided SO1 SO2 SO3 [SO4] TCLR0 Input Provided TCLR1 TI0 Input Provided TI1 TI2 TI3 TI4 TI5 TO0 Output Provided TO1 TO2 TO3 TO4 TO5 TXD0 Output Provided TXD1 − − V ...
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Pin Status The operating status of each pin in each operation mode is shown below. Table 2-3. Operating Status of Each Pin in Each Operation Mode Bus Control Pins Reset Note 1 AD0 to AD15 Hi-Z A16 to A23 ...
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Description of Pin Functions (1) P00 to P05 (Port 0) … 3-state I/O Port 6-bit I/O port that can be set to the input or output in 1-bit units. Besides functioning as I/O port pins, P00 ...
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P30 to P32 (Port 3) … 3-state I/O Port 3-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, P30 to P32 also operate ...
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SI0 (serial input 0) … Input This pin inputs the serial receive data of CSI0. (v) SO0 (serial output 0) … Output This pin outputs the serial transmit data of CSI0. (vi) SCK0 (serial clock 0) … 3-state I/O ...
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Port 16-bit input port with all its bits fixed to the input mode. Besides functioning as input port pins, P70 to P715 also operate as the analog input pins of the A/D converter in the control ...
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P90 to P915 (Port 9) … 3-state I/O Port 16-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, P90 to P915 also operate ...
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PCM0 to PCM3 (Port CM) (V850ES/SA2) … 3-state I/O PCM0 to PCM5 (Port CM) (V850ES/SA3) … 3 state I/O [V850ES/SA2] Port 4-bit I/O port that can be set to the input or output mode in 1-bit ...
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CHAPTER 2 PIN FUNCTIONS [V850ES/SA3] Port 6-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, in the control mode PCM0 to PCM5 also operate ...
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PCS0 to PSC3 (Port CS) (V850ES/SA2) … 3-state I/O PCS0 to PCS5 (Port CS) (V850ES/SA3) … 3-state I/O [V850ES/SA2] Port 4-bit I/O port that can be set to the input or output mode in 1-bit units. ...
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PCT0, PCT1, PCT4 to PCT7 (Port CT) (V850ES/SA2) … 3-state I/O PCT0 to PCT7 (Port CT) (V850ES/SA3) … 3-state I/O [V850ES/SA2] Port 6-bit port that can be set to the input or output mode in 1-bit ...
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RD (read strobe) … Output This is the read strobe signal output pin for the external 16-bit data bus. (iv) ASTB (address strobe) … Output This is the latch strobe signal output pin of the external address bus. The ...
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PDL0 to PDL15 (Port DL) … 3-state I/O Port 16-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, PDL0 to PDL15 also operate ...
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EV (Power supply for port) DD This pin supplies positive power for the I/O ports and pins with alternate functions. (22) EV (Ground for port) SS This is a ground pin for the I/O ports and pins with alternate ...
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Types of Pin I/O Circuits, I/O Buffer Power Supplies, and Connection of Unused Pins Pin Alternate Function P00 NMI P01 to P04 INTP0/TI2 to INTP3/TI5 P05 INTP4 [P20] [SI4] [P21] [SO4] [P22] [SCK4] P30 SI1/RXD0 P31 SO1/TXD0 P32 SCK1 ...
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Pin Alternate Function PCS0 to PCS3 CS0 to CS3 − [PCS4 to PCS7] PCT0, PCT1 WR0, WR1 − [PCT2, PCT3] PCT4 RD − PCT5 PCT6 ASTB − PCT7 PDH0 to PDH5, A16 to A21, [A22, A23] [PDH6, PDH7] PDL0 to ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics. Type Data P-ch Output N-ch disable Input enable Type 5-A Pull-up enable EV DD Data P-ch Output N-ch disable Input enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O ...
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Type 10-F Pull-up enable EV Data Open drain Output disable Input enable Type 16 Feedback cut-off P-ch XT1 XT2 52 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (2/2) Type P-ch P-ch DD IN/OUT P-ch N-ch ...
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The CPU of the V850ES/SA2 and V850ES/SA3 is based on RISC architecture and executes almost all instructions in one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 50 ns: Main clock = 20 MHz Memory space ...
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CPU Register Set The registers of the V850ES/SA2 and V850ES/SA3 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. ...
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Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data variable ...
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System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. ...
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Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to ...
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NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those ...
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Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this ...
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Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a ...
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Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the ...
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Operation Modes The V850ES/SA2 and V850ES/SA3 have the following operation modes. (1) Single-chip mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to ...
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Address Space 3.4.1 CPU address space The CPU of the V850ES/SA2 and V850ES/SA3 has 32-bit architecture and supports linear address space (data space) for operand addressing (data access). It also supports ...
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Image For instruction addressing linear address space (program space) and an internal RAM area are supported linear address space (data space) is supported for operand addressing (data access). In ...
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Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a ...
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Memory map The V850ES/SA2 and V850ES/SA3 reserve the areas shown in Figure 3-3. Figure 3-3. Data Memory Map (Physical Addresses (80 KB ...
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...
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Areas (1) Internal ROM area (a) Memory map addresses 0000000H to 00FFFFFH is reserved as the internal ROM area. µ <1> PD703200 and 703200Y 128 KB are allocated to the following addresses as the internal physical ...
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CHAPTER 3 CPU FUNCTION Figure 3-6. Internal ROM/Internal Flash Memory Area (256 KB Access prohibited area ...
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Interrupt/exception table The V850ES/SA2 and V850ES/SA3 speed up the interrupt response time by fixing handler addresses corresponding to interrupts/exceptions. A collection of these handler addresses is called an interrupt/exception table, which is mapped to the internal ROM area. When ...
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Internal RAM area addresses 3FF0000H to 3FFEFFFH are reserved as the internal RAM area. µ <1> PD703200 and 703200Y 8 KB are allocated to the following addresses as the internal physical RAM. • 3FFD000H to 3FFEFFFH ...
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Internal peripheral I/O area addresses 3FFF000H to 3FFFFFFH are allocated as the internal peripheral I/O area. Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the internal peripheral ...
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Recommended use of address space The architecture of the V850ES/SA2 and V850ES/SA3 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in ...
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Figure 3-11. Recommended Memory Map Program space ...
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Peripheral I/O registers Address Function Register Name FFFFF004H Port register DL FFFFF004H Port register DLL FFFFF005H Port register DLH FFFFF006H Port register DH FFFFF008H Port register CS FFFFF00AH Port register CT FFFFF00CH Port register CM Note FFFFF00EH Port register ...
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Address Function Register Name FFFFF0C0H DMA transfer count register 0 FFFFF0C2H DMA transfer count register 1 FFFFF0C4H DMA transfer count register 2 FFFFF0C6H DMA transfer count register 3 FFFFF0D0H DMA addressing control register 0 FFFFF0D2H DMA addressing control register 1 ...
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Address Function Register Name FFFFF13AH Interrupt control register FFFFF13CH Interrupt control register FFFFF13EH Interrupt control register FFFFF140H Interrupt control register FFFFF142H Interrupt control register FFFFF144H Interrupt control register FFFFF146H Interrupt control register FFFFF148H Interrupt control register FFFFF14AH Interrupt control register ...
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Address Function Register Name FFFFF420H Port mode register 0 Note FFFFF424H Port mode register 2 FFFFF426H Port mode register 3 FFFFF428H Port mode register 4 FFFFF432H Port mode register 9 FFFFF432H Port mode register 9L FFFFF433H Port mode register 9H ...
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Address Function Register Name FFFFF644H Timer clock selection register 23 FFFFF644H Timer clock selection register 2 FFFFF645H Timer clock selection register 3 FFFFF646H Timer mode control register 23 FFFFF646H Timer mode control register 2 FFFFF647H Timer mode control register 3 ...
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Address Function Register Name FFFFF6EEH Week count setting register FFFFF6EEH Week count setting register L FFFFF6EFH Week count setting register H FFFFF802H System status register FFFFF810H DMA trigger factor register 0 FFFFF812H DMA trigger factor register 1 FFFFF814H DMA trigger ...
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Address Function Register Name FFFFFC00H External interrupt falling edge specification register 0 FFFFFC12H External interrupt falling edge specification register 9 FFFFFC12H External interrupt falling edge specification register 9L FFFFFC20H External interrupt rising edge specification register 0 FFFFFC32H External interrupt rising ...
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Address Function Register Name FFFFFD44H Clocked serial interface transmit buffer register 4 Note 2 FFFFFD80H IIC shift register Note 2 FFFFFD82H IIC control register Note 2 FFFFFD83H Slave address register FFFFFD84H IIC clock select register FFFFFD85H IIC function expansion register ...
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Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/SA2 and V850ES/SA3 have the following three special registers. • Power save control register (PSC) • Processor clock ...
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Setting data to special registers Set data to the special registers in the following sequence: <1> Store the DMA transfer state. <2> Disable DMA operation. <3> Prepare data to be set to the special register in a general-purpose register. ...
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Cautions 3. Five NOP instructions or more must be inserted immediately after setting the IDLE mode or software STOP mode (by setting the STP bit of the PSC register to 1). instructions are not necessary in other cases. 4. Finish ...
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System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W SYS 0 PRERR ...
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Notes Be sure to set the following register first when using the V850ES/SA2 and V850ES/SA3: • System wait control register (VSWC) After setting the VSWC register, set the other registers as necessary. When using the external bus, initialize each ...
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Features 4.1.1 V850ES/SA2 Input ports: 14 pins I/O ports: 68 pins I/O pins function alternately as other peripheral functions Can be set to input or output mode in 1-bit units. 4.1.2 V850ES/SA3 Input ports: 18 pins I/O ports: 84 ...
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Basic Configuration of Port 4.2.1 V850ES/SA2 The V850ES/SA2 has a total of 82 input/output port pins (of which 14 are input-only port pins): ports CM, CS, CT, DH, and DL. The port configuration ...
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V850ES/SA3 The V850ES/SA3 has a total of 102 input/output port pins (of which 18 are input-only port pins): ports CD, CM, CS, CT, DH, and DL. The port configuration is shown below. ...
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Port Configuration Table 4-1. Port Configuration (V850ES/SA2) Item Control registers Port mode registers (PMn CD, CM, CS, CT, DH, DL) Port mode control registers (PMCn CM, CS, ...
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Port 0 Port 0 can be set to the input or output mode in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name V850ES/SA2 V850ES/SA3 (1) Function of port 0 Input/output data ...
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Registers (a) Port register 0 (P0) Port register 0 (P0 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Port mode control register 0 (PMC0) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PMC0 0 PMC05 0 ...
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Pull-up resistor option register 0 (PU0) This is an 8-bit register that specifies connection of an internal pull-up resistor. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PU0 0 0 PU0n ...
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External interrupt rising edge specification register 0 (INTR0) This 8-bit register specifies detection of the rising edge of the external interrupt pins. It can be read or written in 8-bit or 1-bit units. Caution Set the port mode after ...
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Block diagram Figure 4-3. Block Diagram of P00 and P05 WR PU PU0 PU0n WR INTR INTR0 INTR0n WR INTF INTF0 INTF0n WR PMC PMC0 PMC0n WR PM PM0 PM0n WR PORT P0 Output latch (P0n) RD NMI, INTP4 ...
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WR PU PU0 PU0n WR INTR INTR0 INTR0n WR INTF INTF0 INTF0n WR PMC PMC0 PMC0n WR PM PM0 PM0n WR PORT Output latch (P0n) RD Edge detection INTP0 to INTP3 input TI2 to TI5 input Caution These pins do ...
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Port 2 Port 2 can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port 2 (V850ES/SA3) Input/output data ...
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Registers (a) Port register 2 (P2) Port register 2 (P2 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Port mode control register 2 (PMC2) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PMC2 0 0 PMC22 ...
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Pull-up resistor option register 2 (PU2) This is an 8-bit register that specifies connection of an internal pull-up resistor. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PU2 0 PU2n 0 ...
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Block diagram PMC PORT Output latch RD Caution This pin does not have hysteresis characteristics in the port mode. It has hysteresis characteristics only when an input-pin alternate function is used. Remark P2: ...
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WR PU PU2 PU21 WR PF PF2 PF21 WR PMC PMC2 PMC21 WR PM PM2 PM21 WR PORT SO4 output P2 Output latch (P21) Address RD Remark P2: Port register 2 PM2: Port mode register 2 PMC2: Port mode control ...
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WR PU PU2 PU22 WR PF PF2 PF22 WR PMC PMC2 PMC22 WR PM PM2 PM22 WR PORT SCK4 output P2 Output latch (P22) Address SCK4 input RD Caution This pin does not have hysteresis characteristics in the port mode. ...
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Port 3 Port 3 can be set to the input or output mode in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port 3 Input/output data ...
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Registers (a) Port register 3 (P3) Port register 3 (P3 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Port mode control register 3 (PMC3) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PMC3 0 PMC32 0 ...
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Port function register 3 (PF3) This 8-bit register specifies normal output or N-ch open-drain output. It can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PF3 0 0 PF3n 0 Normal output 1 N-ch ...
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Block diagram PFC PFC3 PFC30 WR PMC PMC3 PMC30 PORT Output latch RD Caution This pin does not have hysteresis characteristics in the port mode. It has hysteresis characteristics only when an input-pin ...
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WR PU PU3 PU31 WR PF PF3 PF31 WR PMC PFC3 PFC31 WR PMC PMC3 PMC31 WR PM PM3 PM31 SO1 output WR PORT TXD0 output P3 Output latch (P31) Address RD Remark P3: Port register 3 PM3: Port mode ...
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WR PU PU3 PU32 WR PF PF3 PF32 WR PMC PMC3 PMC32 WR PM PM3 PM32 WR PORT SCK1 output P3 Output latch (P32) Address SCK1 input RD Caution This pin does not have hysteresis characteristics in the port mode. ...
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Port 4 Port 4 can be set to the input or output mode in 1-bit units. The number of I/O port bits each product is the same. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port 4 Input/output data can ...
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Registers (a) Port register 4 (P4) Port register 4 (P4 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Port mode control register 4 (PMC4) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PMC4 0 PMC46 PMC46 ...
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Port function control register 4 (PFC4) This 8-bit register specifies control mode 1 or control mode 2. It can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PFC4 0 PFC46 PFC46 0 INTP11 1 ...
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Port function register 4 (PF4) This 8-bit register specifies normal output or N-ch open-drain output. It can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PF4 0 0 PF4n 0 Normal output 1 N-ch ...
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Block diagram PMC PORT RD Caution This pin does not have hysteresis characteristics in the port mode. It has hysteresis characteristics only when an input-pin alternate function is used. Remark P4: Port register ...
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WR PU PU4 PU41 WR PF PF4 PF41 WR PFC PFC4 PFC41 WR PMC PMC4 PMC41 WR PM PM4 PM41 SO0 output WR PORT SDA output P4 Output latch (P41) Address RD Caution This pin does not have hysteresis characteristics ...
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WR PU PU4 PU42 WR PF PF4 PF42 WR PFC PFC4 PFC42 WR PMC PMC4 PMC42 WR PM PM4 PM42 SCK0 output WR PORT SCL output P4 Output latch (P42) RD Address SCK0 input SCL input Caution This pin does ...
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Figure 4-14. Block Diagram of P43 and P45 WR PU PU4 PU4n WR PMC PMC4 PMC4n WR PM PM4 PM4n WR PORT P4 Output latch (P4n) Address RD INTP00/TI0/TCLR0, Noise INTP10/TI1/TCLR1 input elimination Caution These pins do not have hysteresis ...
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Figure 4-15. Block Diagram of P44 and P46 WR PU PU4 PU4n WR PFC PFC4 PFC4n WR PMC PMC4 PMC4n WR PM PM4 PM4n WR PORT TO0, TO1 output P4 Output latch (P4n) Address RD INTP01, INTP11 input Caution These ...
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Port 7 All the pins of port 7 are fixed to the input mode. The number of input port bits differs depending on the product. Commercial Name V850ES/SA2 V850ES/SA3 (1) Function of port 7 Input data can be specified ...
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Register (a) Port register 7 (P7) Port register 16-bit register that is used to read the pin level. This register is read-only, in 16-bit units. If the higher 8 bits of the P7 register are used ...
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Port 8 Port 8 can control input/output in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name V850ES/SA2 V850ES/SA3 (1) Function of port 8 Input data can be specified in 1-bit units ...
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Block diagram Figure 4-17. Block Diagram of P80 and P81 RD ANO0, ANO1 output 126 CHAPTER 4 PORT FUNCTIONS P-ch N-ch User’s Manual U15905EJ2V1UD P80/ANO0, P81/ANO1 ...
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Port 9 Port 9 can be set to the input or output mode in 1-bit units. The number of I/O port bits each product is the same. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port 9 Input/output data can ...
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Registers (a) Port register 9 (P9) Port register 9 (P9 16-bit register that controls reading a pin level and writing an output level. This register can be read or written in 16-bit units. If the higher 8 ...
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Port mode register 9 (PM9) This is a 16-bit register that specifies the input or output mode. This register can be read or written only in 16-bit units. If the higher 8 bits of the PM9 register is used ...
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Port mode control register 9 (PMC9) This is a 16-bit register that specifies the port mode or control mode. This register can be read or written only in 16-bit units. If the higher 8 bits of the PMC9 register ...
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CHAPTER 4 PORT FUNCTIONS PMC97 Specifies operation mode of P97 pin 0 I/O port 1 A7/TO5 output PMC96 Specifies operation mode of P96 pin 0 I/O port 1 A6/TO4 output PMC95 Specifies operation mode of P95 pin 0 I/O port ...
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Port function control register 9 (PFC9) This 16-bit register specifies control mode 1 or control mode 2. It can be read or written only in 16-bit units. If the higher 8 bits of the PFC9 register are used as ...
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CHAPTER 4 PORT FUNCTIONS PFC98 Specifies operation mode of P98 pin in control mode 0 A8 output (with separate bus) 1 RXD1 input PFC97 Specifies operation mode of P97 pin in control mode 0 A7 output (with separate bus) 1 ...
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Port function register 9 (PF9) This 16-bit register specifies normal output or N-ch open-drain output. The PF9 register can be read or written only in 16-bit units. If the higher 8 bits of the PF9 register are used as ...
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Pull-up resistor option register 9 (PU9) This is a 16-bit register that specifies connection of an internal pull-up resistor. This register can be read or written only in 16-bit units. If the higher 8 bits of the PU9 register ...
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External interrupt rising edge specification register 9 (INTR9) This 16-bit register specifies detection of the rising edge of the external interrupt pins. It can be read or written only in 16-bit units. If the higher 8 bits of the ...
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Block diagram Figure 4-18. Block Diagram of P90 and P91 WR PU PU9 PU9n WR PMC PMC9 PMC9n Output buffer off signal WR PM PM9 PM9n A0, A1 output WR PORT P9 Output latch (P9n) RD Remarks 1. P9: ...
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Figure 4-19. Block Diagram of P92 and P93 WR PU PU9 PU9n WR INTR INTR9 INTR9n WR INTF INTF9 INTF9n WR PFC PFC9 PFC9n WR PMC PMC9 PMC9n Output buffer WR PM off signal PM9 PM9n A2, A3 output WR ...
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Figure 4-20. Block Diagram of P94 to P97 and P99 WR PU PU9 PU9n WR PFC PFC9 PFC9n WR PMC PMC9 PMC9n Output buffer WR PM off signal PM9 PM9n output WR PORT TO2 to TO5, TXD1 ...
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Figure 4-21. Block Diagram of P98, P910, and P913 WR PU PU9 PU9n WR PFC PFC9 PFC9n WR PMC PMC9 PMC9n Output buffer WR PM off signal PM9 PM9n WR A8, A10, A13 output PORT P9 Output latch (P9n) RD ...
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Figure 4-22. Block Diagram of P911 and P914 WR PU PU9 PU9n WR PF PF9 PF9n WR PFC PFC9 PFC9n WR PMC PMC9 PMC9n Output buffer WR PM off signal PM9 PM9n A11, A14 output WR PORT SO2, SO3 output ...
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Figure 4-23. Block Diagram of P912 and P915 WR PU PU9 PU9n WR PF PF9 PF9n WR PFC PFC9 PFC9n WR PMC PMC9 PMC9n Output enable signal of SCK2 and SCK3 Output buffer off signal WR PM PM9 PM9n A12, ...
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Port CD Port CD can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port CD (V850ES/SA3) Input/output data ...
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Registers (a) Port register CD (PCD) Port register CD (PCD 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Block diagram Figure 4-24. Block Diagram of PCD1 to PCD3 WR PM PMCD PMCDn WR PORT PCD Output latch (PCDn) RD Remarks 1. PCD: Port register CD PMCD: Port mode register CHAPTER ...
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Port CM Port CM can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port CM Input/output data can ...
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Registers (a) Port register CM (PCM) Port register PCM (PCM 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Port mode control register CM (PMCCM) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PMCCM 0 PMCCM3 0 I/O ...
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Block diagram Figure 4-25. Block Diagram of PCM0 and PCM3 WR PMC PMCCM PMCCMn WR PM PMCM PMCMn WR PORT PCM Output latch (PCMn) WAIT, HLDRQ input RD Remarks 1. PCM: Port register CM PMCM: Port mode register CM ...
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Figure 4-26. Block Diagram of PCM1 and PCM2 WR PMC PMCCM PMCCMn WR PM PMCM PMCMn CLKOUT, HLDAK output WR PORT PCM Output latch (PCMn) Address RD Remarks 1. PCM: Port register CM PMCM: Port mode register CM PMCCM: Port ...
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Figure 4-27. Block Diagram of PCM4 and PCM5 WR PM PMCM PMCMn WR PORT PCM Output latch (PCMn) RD Remarks 1. PCM: Port register CM PMCM: Port mode register CHAPTER 4 PORT FUNCTIONS ...
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Port CS Port CS can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port CS Input/output data can ...
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Registers (a) Port register CS (PCS) Port register CS (PCS 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Port mode control register CS (PMCCS) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PMCCS 0 PMCCSn 0 I/O ...
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Block diagram Figure 4-28. Block Diagram of PCS0 to PCS3 WR PMC PMCCS PMCCSn WR PM PMCS PMCSn CS0 to CS3 output WR PORT PCS Output latch (PCSn) Address RD Remarks 1. PCS: Port register CS PMCS: Port mode ...
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Figure 4-29. Block Diagram of PCS4 to PCS7 PORT Output latch RD Remarks 1. PCS: Port register CS PMCS: Port mode register 156 CHAPTER 4 PORT FUNCTIONS PMCS PMCSn PCS ...
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Port CT Port CT can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port CT Input/output data can ...
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Registers (a) Port register CT (PCT) Port register PCT (PCT 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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CHAPTER 4 PORT FUNCTIONS (c) Port mode control register CT (PMCCT) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: 00H R/W PMCCT ...
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Block diagram Figure 4-30. Block Diagram of PCT0, PCT1, PCT4, and PCT6 WR PMC PMCCT PMCCTn WR PM PMCT PMCTn WR0, WR1, WR RD, ASTB output PORT PCT Output latch (PCTn) RD Remarks 1. PCT: Port register CT PMCT: ...
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Figure 4-31. Block Diagram of PCT2, PCT3, PCT5, and PCT7 WR PM PMCT PMCTn WR PORT PCT Output latch (PCTn) Address RD Remarks 1. PCT: Port register CT PMCT: Port mode register ...
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Port DH Port DH can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port DH Input/output data can ...
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Registers (a) Port register DH (PDH) Port register PDH (PDH 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: ...
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Port mode control register DH (PMCDH) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: 00H R/W Note PMCDH PMCDH7 PMCDH6 PMCDHn ...
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Block diagram Figure 4-32. Block Diagram of PDH0 to PDH7 WR PMC PMCDH PMCDHn Output buffer off signal WR PM PMDH PMDHn A16 to A23 output WR PORT PDH Output latch (PDHn) Address RD Remarks 1. PDH: Port register ...
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Port DL Port DL can be set to the input or output mode in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name V850ES/SA2 V850ES/SA3 (1) Functions of port DL Input/output data ...
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Registers (a) Port register DL (PDL) Port register DL (PDL 16-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. If the ...
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Port mode register DL (PMDL) This is a 16-bit register that specifies the input or output mode. This register can be read or written only in 16-bit units. If the higher 8 bits of the PMDL register are used ...
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Block diagram Figure 4-33. Block Diagram of PDL0 to PDL15 WR PMC PMCDL PMCDLn Output enable signal of AD0 to AD15 WR PM Output buffer off signal PMDL PMDLn Output of AD0 to AD15 WR PORT PDL Output latch ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P00 NMI Input P00 = Setting not needed INTP0 Input P01 = Setting not needed P01 TI2 Input P01 = Setting not needed INTP1 Input P02 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P43 INTP00 Input P43 = Setting not needed TI0 Input P43 = Setting not needed TCLR0 Input P43 = Setting not needed P44 INTP01 Input P44 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P711 ANI11 Input P711 = Setting impossible P712 ANI12 Input P712 = Setting impossible P713 ANI13 Input P713 = Setting impossible P714 ANI14 Input P714 = Setting impossible P715 ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P99 A9 Output P99 = Setting not needed TXD1 Output P99 = Setting not needed P910 A10 Output P910 = Setting not needed SI2 Input P910 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PCM0 WAIT Input PCM0 = Setting not needed PCM1 CLKOUT Output PCM1 = Setting not needed PCM2 HLDAK Output PCM2 = Setting not needed PCM3 HLDQR Input PCM3 = ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PDH0 A16 Output PDH0 = Setting not needed PDH1 A17 Output PDH1 = Setting not needed PDH2 A18 Output PDH2 = Setting not needed PDH3 A19 Output PDH3 = ...
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Cautions The operation of a port differs depending on whether the port is in the input or output mode, as described below. 4.4.1 Writing data to I/O port (1) In output mode A value can be written to the ...
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CHAPTER 5 BUS CONTROL FUNCTION The V850ES/SA2 and V850ES/SA3 are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplexed bus ...
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Table 5-2. External Control Pins (Separate Bus) Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 A0 to A15 P90 to P915 Note A16 to A23 PDH0 to PDH7 WAIT PCM0 CLKOUT PCM1 CS0 to CS3 PCS0 to ...
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Memory Block Function The 64 MB memory space is divided into memory blocks of (lower) 2 MB, 2MB, 4MB, and 8MB. programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in ...
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Chip select control function Of the 64 MB (linear) address space, the lower 16 MB (0000000H to 0FFFFFFH) include four chip select functions, CS0 to CS3. The areas that can be selected by CS0 to CS3 are fixed. By ...
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Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access Note ...
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Access by bus size The V850ES/SA2 and V850ES/SA3 access the internal peripheral I/O and external memory in 8-bit, 16-bit, or 32- bit units. The bus size is as follows. • The bus size of the internal peripheral I/O is ...
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CHAPTER 5 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) Address Halfword data External data bus ...
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Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External data bus ...
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CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address ( First access Address Word ...
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Access to address (4n) First access Second access Address Word data External data Word ...
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CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address ( First access Second access Address ...
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Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/ seven data wait states can be inserted in the bus cycle that is executed for ...
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External wait function To synchronize an extremely slow external device, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the ...
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Relationship between programmable wait and external wait Wait cycles are inserted as the result operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT ...
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Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (AWC). Address wait insertion is set for each chip select area (CS0 to CS3). ...
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Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in the ...
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Bus Hold Function 5.8.1 Functional outline The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has ...
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Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK = ...
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Bus Priority Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). ...
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Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A1 A23 to A16 ASTB CS3 to CS0 WAIT A1 D1 AD15 to AD0 RD 8-bit access AD15 to AD8 AD7 to ...
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CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A1 A23 to A16 ASTB CS3 to CS0 WAIT A1 D1 AD15 to AD0 11 00 WR1, WR0 8-bit access ...
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Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT HLDRQ HLDAK A23 to A16 AD15 to AD0 ASTB RD CS3 to CS0 Note This idle state (TI) does not depend on ...