LM3S2793-IBZ80-C1T

Manufacturer Part NumberLM3S2793-IBZ80-C1T
DescriptionIC ARM CORTEX MCU 128KB 108NFBGA
ManufacturerTexas Instruments
SeriesStellaris® 2000
LM3S2793-IBZ80-C1T datasheet
 


Specifications of LM3S2793-IBZ80-C1T

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed80MHzConnectivityCAN, EBI/EMI, I²C, IrDA, LIN, Microwire, QEI, SPI, SSI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, I²S, POR, PWM, WDTNumber Of I /o67
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size64K x 8Voltage - Supply (vcc/vdd)1.08 V ~ 1.32 V
Data ConvertersA/D 16x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case108-NFBGA
Processor SeriesStellaris 2000CoreARM Cortex M3
3rd Party Development ToolsJTAGjet-CortexM3, MDK-ARM, RL-ARM, ULINK2Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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T E X AS I NS TR UM E NTS - ADVANCE I NFO R MAT I O N
Stellaris® LM3S2793 Microcontroller
D ATA S H E E T
D S -L M3 S2 79 3- 95 38
Co pyri gh t © 20 07 -2 011
Texa s Instrument s I nco rp orat ed

LM3S2793-IBZ80-C1T Summary of contents

  • Page 1

    ... Stellaris® LM3S2793 Microcontroller NTS - ADVANCE I NFO R MAT ATA pyri gh t © 011 Texa s Instrument s I nco rp orat ed ...

  • Page 2

    ... ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ...

  • Page 3

    ... Memory System Ordering of Memory Accesses .............................................................. 90 2.4.3 Behavior of Memory Accesses ....................................................................................... 90 2.4.4 Software Ordering of Memory Accesses ......................................................................... 91 2.4.5 Bit-Banding ................................................................................................................... 92 2.4.6 Data Storage ................................................................................................................ 94 2.4.7 Synchronization Primitives ............................................................................................. 95 2.5 Exception Model ........................................................................................................... 96 2.5.1 Exception States ........................................................................................................... 96 2.5.2 Exception Types ............................................................................................................ 97 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 3 ...

  • Page 4

    ... Functional Description ................................................................................................. 189 5.2.1 Device Identification .................................................................................................... 190 5.2.2 Reset Control .............................................................................................................. 190 5.2.3 Non-Maskable Interrupt ............................................................................................... 195 5.2.4 Power Control ............................................................................................................. 195 5.2.5 Clock Control .............................................................................................................. 196 5.2.6 System Control ........................................................................................................... 203 5.3 Initialization and Configuration ..................................................................................... 205 5.4 Register Map .............................................................................................................. 205 4 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 5

    ... Transfer Size and Increment ........................................................................................ 369 8.2.8 Peripheral Interface ..................................................................................................... 369 8.2.9 Software Request ........................................................................................................ 369 8.2.10 Interrupts and Errors .................................................................................................... 370 8.3 Initialization and Configuration ..................................................................................... 370 8.3.1 Module Initialization ..................................................................................................... 370 8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 370 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 5 ...

  • Page 6

    ... Initialization and Configuration ..................................................................................... 553 11.4.1 One-Shot/Periodic Timer Mode .................................................................................... 553 11.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 554 11.4.3 Input Edge-Count Mode ............................................................................................... 554 11.4.4 Input Edge Timing Mode .............................................................................................. 555 11.4.5 PWM Mode ................................................................................................................. 555 11.5 Register Map .............................................................................................................. 556 11.6 Register Descriptions .................................................................................................. 557 6 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 7

    ... Register Descriptions .................................................................................................. 705 15 Synchronous Serial Interface (SSI) .................................................................... 753 15.1 Block Diagram ............................................................................................................ 754 15.2 Signal Description ....................................................................................................... 754 15.3 Functional Description ................................................................................................. 755 15.3.1 Bit Rate Generation ..................................................................................................... 756 15.3.2 FIFO Operation ........................................................................................................... 756 15.3.3 Interrupts .................................................................................................................... 756 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 7 ...

  • Page 8

    ... Test Mode ................................................................................................................... 881 18.3.14 Bit Timing Configuration Error Considerations ............................................................... 883 18.3.15 Bit Time and Bit Rate ................................................................................................... 883 18.3.16 Calculating the Bit Timing Parameters .......................................................................... 885 Interface ................................................................ 796 2 C Master) ............................................................................... 812 2 C Slave) ................................................................................. 824 2 S) Interface .................................................... 833 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 9

    ... Recommended DC Operating Conditions .................................................................... 1112 25.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics .............................................. 1113 25.1.4 Hibernation Module Characteristics ............................................................................ 1113 25.1.5 Flash Memory Characteristics .................................................................................... 1113 25.1.6 GPIO Module Characteristics ..................................................................................... 1114 25.1.7 Current Specifications ................................................................................................ 1114 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 9 ...

  • Page 10

    ... Package Dimensions ................................................................................................. 1178 C.1.2 Tray Dimensions ....................................................................................................... 1180 C.1.3 Tape and Reel Dimensions ........................................................................................ 1180 C.2 108-Ball BGA Package .............................................................................................. 1182 C.2.1 Package Dimensions ................................................................................................. 1182 C.2.2 Tray Dimensions ....................................................................................................... 1184 C.2.3 Tape and Reel Dimensions ........................................................................................ 1185 Interface ......................................................................... 1136 2 S) Interface ............................................................... 1137 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 11

    ... List of Figures Figure 1-1. Stellaris LM3S2793 Microcontroller High-Level Block Diagram .............................. 66 Figure 2-1. CPU Block Diagram ............................................................................................. 70 Figure 2-2. TPIU Block Diagram ............................................................................................ 71 Figure 2-3. Cortex-M3 Register Set ........................................................................................ 73 Figure 2-4. Bit-Band Mapping ................................................................................................ 94 Figure 2-5. Data Storage ....................................................................................................... 95 Figure 2-6. Vector table ....................................................................................................... 101 Figure 2-7. Exception Stack Frame ...................................................................................... 103 Figure 3-1 ...

  • Page 12

    ... Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 760 Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 761 Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 761 12 = 1.5 V ...................................................... 624 IN_ODD = 0.75 V .................................................... 625 IN_ODD = 2.25 V .................................................... 625 IN_ODD Texas Instruments-Advance Information March 20, 2011 ...

  • Page 13

    ... Figure 25-4. Power-On Reset Timing ................................................................................... 1121 Figure 25-5. Brown-Out Reset Timing .................................................................................. 1122 Figure 25-6. Power-On Reset and Voltage Parameters ......................................................... 1122 Figure 25-7. Voltage Requirements When Using an External V March 20, 2011 2 C Bus ................................................... 800 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Source ............................. 1123 DDC 13 ...

  • Page 14

    ... LQFP Tray Dimensions ........................................................................ 1180 Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1181 Figure C-4. 108-Ball BGA Package Dimensions .................................................................. 1182 Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1184 Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1185 14 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 15

    ... Flash Memory Protection Policy Combinations .................................................... 323 Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 326 Table 7-3. Flash Register Map ............................................................................................ 327 Table 8-1. μDMA Channel Assignments .............................................................................. 357 Table 8-2. Request Type Support ....................................................................................... 359 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 15 ...

  • Page 16

    ... Differential Sampling Pairs ................................................................................. 623 Table 13-5. ADC Register Map ............................................................................................. 632 Table 14-1. Signals for UART (100LQFP) ............................................................................. 694 Table 14-2. Signals for UART (108BGA) ............................................................................... 694 Table 14-3. Flow Control Mode ............................................................................................. 699 Table 14-4. UART Register Map ........................................................................................... 704 16 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 17

    ... Table 23-13. Connections for Unused Signals, 108-pin BGA .................................................. 1109 Table 24-1. Temperature Characteristics ............................................................................. 1111 March 20, 2011 2 C Master Timer Period versus Speed Mode ................................... 801 2 C) Interface Register Map ............................................. 811 2 S) Interface Register Map ................................... 845 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 17 ...

  • Page 18

    ... S Slave Clock (Receive and Transmit) ............................................................ 1137 2 Table 25-39 Master Mode .............................................................................................. 1137 2 Table 25-40 Slave Mode ................................................................................................ 1138 Table 25-41. Analog Comparator Characteristics ................................................................... 1138 Table 25-42. Analog Comparator Voltage Reference Characteristics ...................................... 1139 Table B-1. Part Ordering Information ................................................................................. 1176 18 Source Current Specifications ..................................................... 1116 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 19

    ... Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 136 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 136 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 136 Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 136 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 19 ...

  • Page 20

    ... Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 229 Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 230 Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 232 Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 234 2 Register 15 MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 235 20 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 21

    ... Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 337 Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 338 Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 339 Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 340 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 21 ...

  • Page 22

    ... DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 411 Register 30: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 412 General-Purpose Input/Outputs (GPIOs) ................................................................................... 413 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 427 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 428 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 429 22 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 23

    ... EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................ 526 Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................ 526 Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. 527 Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. 527 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 23 ...

  • Page 24

    ... Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 598 Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 599 Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 600 Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 601 Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 602 24 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 25

    ... ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 679 Register 35: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 680 Register 36: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 681 Register 37: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 682 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 25 ...

  • Page 26

    ... UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 748 Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 749 Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 750 Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 751 Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 752 26 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 27

    ... S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 848 2 Register Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 850 2 Register Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 851 2 Register Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 852 March 20, 2011 2 S) Interface ............................................................................ 833 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 27 ...

  • Page 28

    ... CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 916 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 916 Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 917 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 917 Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 918 28 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 29

    ... PWM3 Load (PWM3LOAD), offset 0x110 ........................................................................ 986 Register 32: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................. 987 Register 33: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................. 987 Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4 ................................................................ 987 Register 35: PWM3 Counter (PWM3COUNT), offset 0x114 ................................................................. 987 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 29 ...

  • Page 30

    ... PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 .......................................... 1005 Register 80: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ................................................... 1006 Register 81: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ................................................... 1006 Register 82: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ................................................... 1006 Register 83: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ................................................... 1006 30 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 31

    ... QEI Velocity (QEISPEED), offset 0x01C ........................................................................ 1027 Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................. 1028 Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ........................................................... 1030 Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ................................................... 1032 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 31 ...

  • Page 32

    ... Revision History Revision History The revision history table notes changes made between the indicated revisions of the LM3S2793 data sheet. Table 1. Revision History Date Revision Description March 2011 9538 ■ Clarified "Reset Control" section in the "System Control" chapter. ■ Corrected USB PLL speed in "Main Clock Tree" diagram. ...

  • Page 33

    ... Maximum Current Specifications, and Typical Current Consumption vs. Frequency sections. Clarified Reset, and Power and Brown-out Characteristics and added a new specification for powering down before powering back up. Added characteristics required when using an external regulator to provide power for V Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller . DDC 33 ...

  • Page 34

    ... Added "VDD Ramp when Waking from Hibernation" timing diagram. Added t parameter to "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" table. ALEADD Added "Host-Bus 8/16 Mode Muxed Read Timing" and "Host-Bus 8/16 Mode Muxed Write Timing" timing diagrams. Texas Instruments-Advance Information 2 C module 2 C slave registers. March 20, 2011 ...

  • Page 35

    ... Table 25-33 on page 1134. REFA Corrected values for t (SSIClk rise/fall time) in Table 25-35 on page 1134. CLKRF 2 Added I C Characteristics table (see Table 25-36 on page 1136). Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ® names: the Cortex-M3 Interrupt in Table 25-7 on page 1114. HIB_RTC 35 ...

  • Page 36

    ... GPIO pin to force the ROM Boot Loader to execute on reset. ■ Added three figures to the ADC chapter on sample phase control "Reset Characteristics" table, corrected Supply voltage (VDD) rise time. Clarified figure "SDRAM Initialization and Load Mode Register Timing". Added BSEL0n/BSEL1n to EPI timing diagrams. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 37

    ... In "Flash Memory Characteristics" table, corrected Mass erase time Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time Added table entry for VDD3ON power consumption to Table 25-7 on page 1114. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 37 ...

  • Page 38

    ... Changed SSI set up and hold times to be expressed in system clocks, not ns. ■ Updated Electrical Characteristics chapter with latest data. Changes were made to Hibernation, ADC and EPI content. ■ Additional minor data sheet clarifications and corrections. 38 Texas Instruments-Advance Information ® devices. March 20, 2011 ...

  • Page 39

    ... Modified General-Purpose Mode Read and Write Timing figure. Modified values for t and t parameters, and deleted Interface Characteristics figure. Major changes to ADC Characteristics tables, including adding additonal tables and diagram. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller parameter from EPI General-Purpose OD 39 ...

  • Page 40

    ... Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table. ■ Updated ROM DriverLib appendix with RevC0 functions. ■ Updated part ordering numbers. ■ Additional minor data sheet clarifications and corrections. May 2009 5285 Started tracking revision history. 40 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 41

    ... About This Document This data sheet provides reference information for the LM3S2793 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers ...

  • Page 42

    ... Bit cleared chip reset. 1 Bit set chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. 42 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 43

    ... Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 43 ...

  • Page 44

    ... These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S2793 microcontroller has the following features: ■ ARM Cortex-M3 Processor Core – 80-MHz operation; 100 DMIPS performance – ...

  • Page 45

    ... LQFP and 108-ball BGA package ■ Industrial (-40°C to 85°C) Temperature Range The LM3S2793 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security ...

  • Page 46

    ... Information” on page 1176 for ordering information for Stellaris family devices. 1.1 Functional Overview The following sections provide an overview of the features of the LM3S2793 microcontroller. The page number in parentheses indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 1176. ...

  • Page 47

    ... Memory Map (see page 87) A memory map lists the location of instructions and data in memory. The memory map for the LM3S2793 controller can be found in “Memory Model” on page 87. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. ...

  • Page 48

    ... The following sections describe the on-chip memory modules. 1.1.2.1 SRAM (see page 320) The LM3S2793 microcontroller provides single-cycle on-chip SRAM. The internal SRAM of the Stellaris devices is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor ...

  • Page 49

    ... Write channel request asserted by empty on the internal write FIFO (WFIFO) The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory (SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 2 C, the EPI is designed to act like a 49 ...

  • Page 50

    ... Optional "address" sizes from 4 bits to 20 bits – Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input ■ General parallel GPIO – bits, FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls 50 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 51

    ... The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from bytes of user information. The LM3S2793 microcontroller includes two CAN units with the following features: ■ CAN protocol version 2.0 part A/B ■ Bit rates Mbps ■ ...

  • Page 52

    ... Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level 52 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 53

    ... The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The LM3S2793 microcontroller includes two SSI modules with the following features: March 20, 2011 2 ...

  • Page 54

    ... Architectural Overview ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation ■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from bits ■ ...

  • Page 55

    ... Channel requests asserted when FIFO contains required amount of data 1.1.5 System Integration The LM3S2793 microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ ...

  • Page 56

    ... Device identification information: version, part number, SRAM size, Flash memory size, and so on ■ Power control – On-chip fixed Low Drop-Out (LDO) voltage regulator 56 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 57

    ... Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional options: ■ Operating modes: March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 57 ...

  • Page 58

    ... CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The LM3S2793 microcontroller includes eight Capture Compare PWM pins (CCP) that can be programmed to operate in the following modes: ■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. ...

  • Page 59

    ... The LM3S2793 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris Watchdog Timer module has the following features: ■ ...

  • Page 60

    ... Digital input enables 1.1.6 Advanced Motion Control The LM3S2793 microcontroller provides motion control functions integrated into the device, including: ■ Eight advanced PWM outputs for motion and energy applications ■ Four fault inputs to promote low-latency shutdown ■ Two Quadrature Encoder Inputs (QEI) The following provides more detail on these motion control functions ...

  • Page 61

    ... High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. The LM3S2793 PWM module consists of four PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector ...

  • Page 62

    ... The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 20 MHz for a 80-MHz system). The LM3S2793 microcontroller includes two QEI modules providing control of two motors at the same time with the following features: ■ Position integrator that tracks the encoder position ■ ...

  • Page 63

    ... ADC module uses burst requests for DMA 1.1.7.2 Analog Comparators (see page 919) An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The LM3S2793 microcontroller provides three independent March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 64

    ... This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. The LM3S2793 microcontroller provides three independent integrated analog comparators with the following functions: ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ ...

  • Page 65

    ... High-Level Block Diagram Figure 1-1 on page 66 depicts the features on the Stellaris LM3S2793 microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus ...

  • Page 66

    ... Architectural Overview Figure 1-1. Stellaris LM3S2793 Microcontroller High-Level Block Diagram JTAG/SWD System Control and Clocks (w/ Precis. Osc.) LM3S2793 DMA General- Purpose Timers (4) External Peripheral Interface I2C (2) CAN Controllers (2) Analog Comparators (3) PWM (8) 66 ARM® Cortex -M3 ROM (80 MHz) Flash DCode bus (128 KB) ...

  • Page 67

    ... Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 1034 ■ “Signal Tables” on page 1036 ■ “Operating Characteristics” on page 1111 ■ “Electrical Characteristics” on page 1112 ■ “Package Information” on page 1178 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 67 ...

  • Page 68

    ... DMIPS/MHz ® The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. 68 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 69

    ... ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 69 ...

  • Page 70

    ... Data Memory Protection Unit Data Watchpoint Flash and Trace Patch and Breakpoint Private Peripheral Bus (internal) Bus Matrix Debug Access Port Texas Instruments-Advance Information Serial ARM Wire Cortex-M3 Output Trace Port Trace (SWO) Port Interface Unit Instrumentation Trace Macrocell ROM Table Adv ...

  • Page 71

    ... An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 112). ■ System Control Block (SCB) March 20, 2011 Asynchronous FIFO Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Serial Wire Trace Out Trace Port (serializer) (SWO) ...

  • Page 72

    ... The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements 72 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 73

    ... SP (R13) PSP LR (R14) PC (R15) PSR Program status register PRIMASK FAULTMASK Exception mask registers BASEPRI CONTROL CONTROL register Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Stack Used a Main stack or process stack Main stack ‡ ‡ MSP Banked version of SP Special registers a 73 ...

  • Page 74

    ... Cortex General-Purpose Register 10 - Cortex General-Purpose Register 11 - Cortex General-Purpose Register 12 - Stack Pointer 0xFFFF.FFFF Link Register - Program Counter 0x0100.0000 Program Status Register 0x0000.0000 Priority Mask Register 0x0000.0000 Fault Mask Register 0x0000.0000 Base Priority Mask Register 0x0000.0000 Control Register Texas Instruments-Advance Information See page ...

  • Page 75

    ... Bit/Field Name 31:0 DATA March 20, 2011 DATA R/W R/W R/W R/W R DATA R/W R/W R/W R/W R Type Reset Description R/W - Register data. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 76

    ... R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the address of the stack pointer. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R March 20, 2011 - 0 - ...

  • Page 77

    ... LINK March 20, 2011 LINK R/W R/W R/W R/W R LINK R/W R/W R/W R/W R Type Reset Description R/W 0xFFFF.FFFF This field is the return address. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 78

    ... R/W R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the current program address. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R March 20, 2011 - 0 - ...

  • Page 79

    ... R/W R/W R/W R/W R/W Reset ICI / IT Type Reset March 20, 2011 Type Combination R/W APSR, EPSR, and IPSR RO EPSR and IPSR a R/W APSR and IPSR b R/W APSR and EPSR ICI / IT THUMB reserved Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller reserved ISRNUM ...

  • Page 80

    ... DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 81

    ... The value of this field is only meaningful when accessing PSR or EPSR. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 81 ...

  • Page 82

    ... Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x46 Interrupt Vector 54 0x47-0x7F Reserved See “Exception Types” on page 97 for more information. The value of this field is only meaningful when accessing PSR or IPSR. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 83

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority effect. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 84

    ... R/W 0 Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. Texas Instruments-Advance Information ...

  • Page 85

    ... All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 86

    ... MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. Texas Instruments-Advance Information ...

  • Page 87

    ... The processor has a fixed memory map that provides addressable memory. The memory map for the LM3S2793 controller is provided in Table 2-4 on page 87. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. ...

  • Page 88

    ... Analog Comparators GPIO Port J Reserved CAN0 Controller CAN1 Controller Reserved Reserved GPIO Port A (AHB aperture) GPIO Port B (AHB aperture) GPIO Port C (AHB aperture) GPIO Port D (AHB aperture) Texas Instruments-Advance Information For details, see page ... 426 768 768 - 705 705 705 - 812 812 - ...

  • Page 89

    ... Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) Reserved Trace Port Interface Unit (TPIU) Reserved Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller For details, see page ... 426 426 426 426 426 ...

  • Page 90

    ... Strongly XN bus Ordered Reserved - - Texas Instruments-Advance Information Description This executable region is for program code. Data can also be stored here. This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 92). ...

  • Page 91

    ... Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 91 ...

  • Page 92

    ... Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 93

    ... The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 93 ...

  • Page 94

    ... Figure 2-5 on page 95 illustrates how data is stored. 94 32-MB Alias Region 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 1-MB SRAM Bit-Band Region 0x200F.FFFE 0x200F.FFFD 0x2000.0002 0x2000.0001 Texas Instruments-Advance Information 0x23FF.FFE4 0x23FF.FFE0 0x2200.0004 0x2200.0000 0x200F.FFFC 0x2000.0000 March 20, 2011 ...

  • Page 95

    ... The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. March 20, 2011 Register Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 95 ...

  • Page 96

    ... See “Nested Vectored Interrupt Controller (NVIC)” on page 112 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: 96 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 97

    ... Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 97 ...

  • Page 98

    ... NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 99 lists the interrupts on the LM3S2793 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler ...

  • Page 99

    ... Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Activation b Offset Asynchronous Asynchronous Description Processor exceptions GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 PWM Fault PWM Generator 0 ...

  • Page 100

    ... Texas Instruments-Advance Information Description GPIO Port F GPIO Port G GPIO Port H UART2 SSI1 Timer 3A Timer QEI1 CAN0 CAN1 Reserved Hibernation Module Reserved PWM Generator 3 µDMA Software µDMA Error ADC1 Sequence 0 ADC1 Sequence 1 ...

  • Page 101

    ... IRQ0 0x0040 Systick 0x003C PendSV 0x0038 Reserved Reserved for Debug SVCall 0x002C Reserved Usage fault 0x0018 Bus fault 0x0014 Memory management fault 0x0010 Hard fault 0x000C NMI 0x0008 Reset 0x0004 Initial SP value 0x0000 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 101 ...

  • Page 102

    ... Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On 102 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 103

    ... Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC March 20, 2011 Pre-IRQ top of stack IRQ top of stack Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 103 ...

  • Page 104

    ... Reserved Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. Reserved Handler Fault Status Register Hard fault Hard Fault Status (HFAULTSTAT) Hard fault Hard Fault Status (HFAULTSTAT) Texas Instruments-Advance Information Bit Name VECT FORCED March 20, 2011 ...

  • Page 105

    ... Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Bit Name a IERR DERR MSTKE MUSTKE BSTKE BUSTKE IBUS ...

  • Page 106

    ... A program might have an idle loop to put the processor back to sleep mode. 106 Address Register Name - Memory Management Fault Address (MMADDR) Bus Fault Address (FAULTADDR) - Texas Instruments-Advance Information Register Description page 165 page 159 page 166 page 159 page 167 page 159 March 20, 2011 ...

  • Page 107

    ... Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 108 lists the supported instructions. Note: In Table 2-13 on page 108: ■ Angle brackets, <>, enclose alternative forms of the operand March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 107 ...

  • Page 108

    ... Load multiple registers, decrement Rn{!}, reglist before Load multiple registers, increment after Rn{!}, reglist Load register with word Rt, [Rn, #offset] Load register with byte Rt, [Rn, #offset] Load register with two bytes Rt, Rt2, [Rn, #offset] Texas Instruments-Advance Information Flags N,Z,C,V N,Z,C,V N,Z,C,V - N,Z,C N,Z N,Z,C ...

  • Page 109

    ... Rn Send event Signed multiply with accumulate RdLo, RdHi, Rn, Rm (32x32+64), 64-bit result Signed multiply (32x32), 64-bit result RdLo, RdHi, Rn, Rm Signed saturate Rd, #n, Rm {,shift #s} Store multiple registers, increment after Rn{!}, reglist Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Flags - - - - - - - N,Z,C N,Z ...

  • Page 110

    ... RdLo, RdHi, Rn, Rm Unsigned Saturate Rd, #n, Rm {,shift #s} Zero extend a Byte {Rd,} Rm, {,ROR #n} Zero extend a Halfword {Rd,} Rm, {,ROR #n} Unsigned saturate Rd, #n, Rm {,shift #s} Zero extend a byte {Rd,} Rm {,ROR #n} Zero extend a halfword {Rd,} Rm {,ROR #n} - Wait for event - Wait for interrupt Texas Instruments-Advance Information Flags - - - - - - - - - - - - N,Z,C,V N,Z,C,V - ...

  • Page 111

    ... A high-speed alarm timer using the system clock. March 20, 2011 ® implementation of the Cortex-M3 processor Core Peripheral System Timer Nested Vectored Interrupt Controller System Control Block Memory Protection Unit Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Description (see page ...) 111 112 114 114 111 ...

  • Page 112

    ... Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). 112 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 113

    ... Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 113 ...

  • Page 114

    ... Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. 114 Description All accesses to Strongly Ordered memory occur in program order. Memory-mapped peripherals Normal memory Texas Instruments-Advance Information March 20, 2011 ...

  • Page 115

    ... Region Number ; Region Base Address ; Region Size and Enable ; Region Attribute ; 0xE000ED98, MPU region number register ; Region Number ; Disable ; Region Size and Enable ; Region Base Address ; Region Attribute ; Enable ; Region Size and Enable Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 115 ...

  • Page 116

    ... MPU Region Base register ; Region base address and region number combined ; with VALID (bit 4) set ; Region Attribute, Size and Enable ; 0xE000ED9C, MPU Region Base register ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Texas Instruments-Advance Information March 20, 2011 ...

  • Page 117

    ... Normal 0 Normal 1 Normal 1 Normal 0 Normal 0 Normal 1 Reserved encoding 0 Reserved encoding 1 Normal 1 Normal Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB 64KB 0 Shareability Other Attributes Shareable - Shareable - Not shareable Outer and inner Shareable write-through ...

  • Page 118

    ... Reads by privileged software only. RO Read-only, by privileged or unprivileged software. RO Read-only, by privileged or unprivileged software. TEX 000b 000b Texas Instruments-Advance Information Shareability Other Attributes Not shareable Nonshared Device Not shareable Cached memory (BB = outer policy inner Shareable policy). See Table 3-4 for the encoding of the AA and BB bits. ...

  • Page 119

    ... Interrupt 32-54 Clear Pending 0x0000.0000 Interrupt 0-31 Active Bit 0x0000.0000 Interrupt 32-54 Active Bit 0x0000.0000 Interrupt 0-3 Priority Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Memory Type and Attributes Normal memory, shareable, write-back, write-allocate Device memory, shareable See page 122 124 ...

  • Page 120

    ... System Handler Priority 3 0x0000.0000 System Handler Control and State 0x0000.0000 Configurable Fault Status 0x0000.0000 Hard Fault Status - Memory Management Fault Address - Bus Fault Address 0x0000.0800 MPU Type Texas Instruments-Advance Information See page 136 136 136 136 136 136 136 136 136 136 ...

  • Page 121

    ... MPU Region Base Address Alias 2 0x0000.0000 MPU Region Attribute and Size Alias 2 0x0000.0000 MPU Region Base Address Alias 3 0x0000.0000 MPU Region Attribute and Size Alias 3 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller See page 169 171 172 174 172 174 ...

  • Page 122

    ... R/W 1 Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. Texas Instruments-Advance Information COUNT ...

  • Page 123

    ... Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 123 ...

  • Page 124

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. Texas Instruments-Advance Information RELOAD ...

  • Page 125

    ... This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 126

    ... Interrupt Enable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. Texas Instruments-Advance Information R/W R/W R/W R/W R/W ...

  • Page 127

    ... Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller INT R/W R/W R/W ...

  • Page 128

    ... Type Reset Description R/W 0x0000.0000 Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R ...

  • Page 129

    ... Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller INT R/W R/W R/W R/W R/W ...

  • Page 130

    ... On a write, no effect read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. Texas Instruments-Advance Information R/W R/W ...

  • Page 131

    ... On a read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller INT ...

  • Page 132

    ... On a read, indicates that the interrupt is not pending write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Advance Information R/W ...

  • Page 133

    ... On a write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller INT ...

  • Page 134

    ... Offset 0x300 Type RO, reset 0x0000.0000 Type Reset Type Reset Bit/Field Name 31:0 INT 134 INT INT Type Reset Description RO 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 135

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0x00.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller INT ...

  • Page 136

    ... Application Interrupt and Reset Control (APINT) register (see page 146) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. 136 Interrupt Interrupt [4n+3] Interrupt [4n+2] Interrupt [4n+1] Interrupt [4n] Texas Instruments-Advance Information March 20, 2011 ...

  • Page 137

    ... PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller reserved ...

  • Page 138

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WO 0x00 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. Texas Instruments-Advance Information ...

  • Page 139

    ... In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M3 processor. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 140

    ... No effect. 1 Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 141

    ... Constant Value Description 0xF Always reads as 0xF. RO 0xC23 Part Number Value Description 0xC23 Cortex-M3 processor. RO 0x0 Revision Number Value Description 0x0 The pn value in the rnpn product revision identifier, for example, the 0 in r2p0. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller CON ...

  • Page 142

    ... On a read, indicates a PendSV exception is not pending write, no effect read, indicates a PendSV exception is pending write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing the UNPENDSV bit. Texas Instruments-Advance Information ...

  • Page 143

    ... This bit provides status for all interrupts excluding NMI and Faults. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 143 ...

  • Page 144

    ... ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 79). Texas Instruments-Advance Information March 20, 2011 ...

  • Page 145

    ... Because there are 54 interrupts, the minimum alignment is 128 words. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller R/W ...

  • Page 146

    ... Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Group Subpriorities Priorities ...

  • Page 147

    ... This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable System Reset This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 147 ...

  • Page 148

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. Texas Instruments-Advance Information ...

  • Page 149

    ... Setting this bit enables an interrupt-driven application to avoid returning to an empty main application Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 149 ...

  • Page 150

    ... The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 151

    ... The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 103 for more information). Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 151 ...

  • Page 152

    ... Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 153

    ... RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 154

    ... This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 155

    ... Usage Fault Enable Value Description 0 Disables the usage fault exception. 1 Enables the usage fault exception. R/W 0 Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller USAGE BUS R/W R ...

  • Page 156

    ... This bit can be modified to change the pending status of the usage fault exception. R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 157

    ... Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 157 ...

  • Page 158

    ... Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 159

    ... Type Reset Description RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller NOCP INVPC INVSTAT UNDEF RO RO R/W1C ...

  • Page 160

    ... The processor has attempted an illegal load of EXC_RETURN to the result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing it. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 161

    ... Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 161 ...

  • Page 162

    ... An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 163

    ... MMADDR register. This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 163 ...

  • Page 164

    ... This fault occurs on any access region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 165

    ... This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 166

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W ...

  • Page 167

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller R/W R/W R/W R/W R/W R ...

  • Page 168

    ... Indicates there are eight supported MPU data regions. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation Separate or Unified MPU Value Description 0 Indicates the MPU is unified. Texas Instruments-Advance Information IREGION ...

  • Page 169

    ... reserved Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller PRIVDEFEN HFNMIENA ENABLE R/W R/W ...

  • Page 170

    ... When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 171

    ... R/W 0x0 MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ...

  • Page 172

    ... Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 173

    ... R/W 0x0 Region Number On a write, contains the value to be written to the MPUNUMBER register read, returns the current region number in the MPUNUMBER register. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 173 ...

  • Page 174

    ... GB No valid ADDR field in MPUBASE; the region occupies the complete memory map reserved R/W R/W R reserved R/W R/W R Texas Instruments-Advance Information Note Minimum permitted size - - - Maximum possible size TEX S C R/W R/W R/W R/W R/W R SIZE ENABLE R/W R/W R/W R/W R/W ...

  • Page 175

    ... R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 174 for more information. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 175 ...

  • Page 176

    ... Cortex-M3 Peripherals Bit/Field Name 0 ENABLE 176 Type Reset Description R/W 0 Region Enable Value Description 0 The region is disabled. 1 The region is enabled. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 177

    ... Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 177 ...

  • Page 178

    ... JTAG/SWD CLK. PC1 (3) I/O TTL JTAG TMS and SWDIO. PC3 (3) O TTL JTAG TDO and SWO. PC0 (3) I TTL JTAG/SWD CLK. PC2 (3) I TTL JTAG TDI. PC3 (3) O TTL JTAG TDO and SWO. Texas Instruments-Advance Information TDO Cortex-M3 Debug Port March 20, 2011 ...

  • Page 179

    ... JTAG TMS and SWDIO. PC3 (3) O TTL JTAG TDO and SWO. PC0 (3) I TTL JTAG/SWD CLK. PC2 (3) I TTL JTAG TDI. PC3 (3) O TTL JTAG TDO and SWO. PC1 (3) I TTL JTAG TMS and SWDIO. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 179 ...

  • Page 180

    ... The value of TDO depends on the current TAP state, the current instruction, and the data in the 180 Internal Pull-Up Internal Pull-Down Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Enabled Disabled Texas Instruments-Advance Information Drive Strength Drive Value N/A N/A N/A N/A N/A N/A 2-mA driver High-Z March 20, 2011 ...

  • Page 181

    ... TAP controller’s CAPTURE states and allows March 20, 2011 Select DR Scan 1 0 Capture Shift Exit Pause Exit Update Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Select IR Scan 1 0 Capture IR 0 Shift Exit Pause Exit Update 181 ...

  • Page 182

    ... ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. 182 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 183

    ... Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 183 ...

  • Page 184

    ... JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings. 184 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 185

    ... Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. BYPASS Connects TDI to TDO through a single Shift Register chain. Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 185 ...

  • Page 186

    ... ARM core. This information can be used by testing equipment and debuggers to automatically configure input and output data streams. IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 187 for more information. 186 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 187

    ... The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each March 20, 2011 12 11 Part Number Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 1 0 TDO Manufacturer ID 1 187 ...

  • Page 188

    ... The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 188 ... GPIO (m+1) GPIO Texas Instruments-Advance Information O TDO ... GPIO n March 20, 2011 ...

  • Page 189

    ... PB7 (4) I TTL Non-maskable interrupt. fixed I Analog Main oscillator crystal input or an external clock reference input. fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. fixed I TTL System reset input. Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller 189 ...

  • Page 190

    ... This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 Reset Sources The LM3S2793 microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 191). 2. External reset input pin (RST) assertion (see page 192). 3. Internal brown-out (BOR) detector (see page 193). ...

  • Page 191

    ... The internal POR is only active on the initial power-up of the microcontroller and when the microcontroller wakes from hibernation. The Power-On Reset timing is shown in Figure 25-4 on page 1121. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ) and generates DD 191 ...

  • Page 192

    ... Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RST kΩ to 100 kΩ µ the application requires the use of an external reset switch, Figure 5-3 on page 193 shows the proper circuitry to use. 192 VDD Texas Instruments-Advance Information and then de-asserted MIN March 20, 2011 ...

  • Page 193

    ... The internal Brown-Out Reset timing is shown in Figure 25-5 on page 1122. March 20, 2011 VDD brown-out condition is detected, the system BTH , an internal BOR condition is set. BTH level is restored. The RESC register can be examined DD Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller ) DD 193 ...

  • Page 194

    ... Watchdog Timer Reset The Watchdog Timer module's function is to prevent system hangs. The LM3S2793 microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module operates in the same manner except that because the PIOSC watchdog timer module different clock domain, register accesses must have a time delay between them ...

  • Page 195

    ... Main Oscillator Verification Failure The LM3S2793 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, a power-on reset is generated and control is transferred to the NMI handler ...

  • Page 196

    ... OSC0 input and OSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz to 196 GND Internal Logic and PLL GND Low-Noise LDO GND I/O Buffers GND GNDA Analog Circuits GNDA Texas Instruments-Advance Information March 20, 2011 ...

  • Page 197

    ... March 20, 2011 Drive PLL? Yes BYPASS = 0, OSCSRC = 0x1 No - Yes BYPASS = 0, OSCSRC = 0x0 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller Used as SysClk? Yes BYPASS = 1, OSCSRC = 0x1 Yes BYPASS = 1, OSCSRC = 0x2 Yes BYPASS = 1, OSCSRC = 0x0 Yes BYPASS = 1, OSCSRC = 0x3 Yes BYPASS = 1, OSCSRC2 = 0x7 No - 197 ...

  • Page 198

    ... MHz from the PLL output for proper ADC operation. The PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV in RCC). Note: When the ADC module is in operation, the system clock must be at least 16 MHz. 198 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 199

    ... RXINT RXFRAC TXINT TXFRAC PWMDW a XTAL PWRDN b PLL (400 MHz) c DIV400 ÷ 2 b,d BYPASS b,d ÷ 25 Texas Instruments-Advance Information Stellaris® LM3S2793 Microcontroller USB Clock Receive MCLK Transmit MCLK a USEPWMDIV a PWM Clock a,d USESYSDIV System Clock e SYSDIV PWRDN ADC Clock 199 ...

  • Page 200

    ... Clock source frequency/2 reserved Clock source frequency/2 66.67 MHz Clock source frequency/3 50 MHz Clock source frequency/4 40 MHz Clock source frequency/5 ... ... 20 MHz Clock source frequency/10 ... ... Texas Instruments-Advance Information a StellarisWare Parameter b SYSCTL_SYSDIV_1 SYSCTL_SYSDIV_2 SYSCTL_SYSDIV_3 SYSCTL_SYSDIV_4 SYSCTL_SYSDIV_5 SYSCTL_SYSDIV_6 SYSCTL_SYSDIV_7 SYSCTL_SYSDIV_8 SYSCTL_SYSDIV_9 SYSCTL_SYSDIV_10 SYSCTL_SYSDIV_11 SYSCTL_SYSDIV_12 ...