UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet
UPD70F3738GF-GAS-AX
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UPD70F3738GF-GAS-AX Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual V850ES/JG3-L 32-bit Single-Chip Microcontrollers Hardware μ PD70F3737 μ PD70F3738 μ PD70F3792 μ PD70F3793 Document No. U18953EJ5V0UD00 (5th edition) Date Published December 2009 NS 2007 ...
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User’s Manual U18953EJ5V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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Caution: This product uses SuperFlash IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America. ...
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The information in this document is current as of November, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/JG3-L and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JG3-L ...
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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG3-L V850ES Architecture User’s Manual V850ES/JG3-L Hardware User’s Manual Documents related to development tools QB-V850ESSX2 In-Circuit ...
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Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE − Products and Packages − Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note ...
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CHAPTER 1 INTRODUCTION ................................................................................................................ 23 1.1 General .......................................................................................................................................23 1.2 Features .....................................................................................................................................25 1.3 Application Fields .....................................................................................................................27 1.4 Ordering Information ................................................................................................................27 1.5 Pin Configuration (Top View)...................................................................................................28 1.6 Function Block Configuration..................................................................................................34 1.6.1 Internal block diagram .................................................................................................................34 1.6.2 Internal units ................................................................................................................................35 CHAPTER 2 PIN ...
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Port 9......................................................................................................................................... 122 4.3.8 Port CM ..................................................................................................................................... 130 4.3.9 Port CT...................................................................................................................................... 132 4.3.10 Port DH ..................................................................................................................................... 134 4.3.11 Port DL ...................................................................................................................................... 136 4.4 Block Diagrams.......................................................................................................................139 4.5 Port Register Settings When Alternate Function Is Used ..................................................170 4.6 Cautions...................................................................................................................................178 4.6.1 Cautions ...
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PLL Function ...........................................................................................................................223 6.5.1 Overview ...................................................................................................................................223 6.5.2 Registers ...................................................................................................................................224 6.5.3 Usage ........................................................................................................................................227 6.6 How to Connect a Resonator .................................................................................................228 6.6.1 Main clock oscillator ..................................................................................................................228 6.6.2 Subclock oscillator.....................................................................................................................228 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 231 7.1 Overview ..................................................................................................................................231 ...
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Interval timer mode.................................................................................................................... 442 9.4.2 Cautions .................................................................................................................................... 446 CHAPTER 10 WATCH TIMER ..............................................................................................................447 10.1 Functions .................................................................................................................................447 10.2 Configuration ..........................................................................................................................448 10.3 Control Registers....................................................................................................................450 10.4 Operation .................................................................................................................................454 10.4.1 Watch timer operations ............................................................................................................. 454 10.4.2 Interval timer operations ............................................................................................................ 455 10.5 Cautions...................................................................................................................................457 ...
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Registers ..................................................................................................................................505 14.5 Operation .................................................................................................................................516 14.5.1 Basic operation..........................................................................................................................516 14.5.2 Conversion timing......................................................................................................................517 14.5.3 Trigger modes ...........................................................................................................................518 14.5.4 Operation mode.........................................................................................................................520 14.5.5 Power-fail compare mode..........................................................................................................526 14.6 Cautions ...................................................................................................................................533 14.7 How to Read A/D Converter Characteristics Table .............................................................538 CHAPTER 15 D/A CONVERTER ......................................................................................................... ...
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UARTC0 and CSIB1 mode switching ........................................................................................ 591 17.4 Registers..................................................................................................................................592 17.5 Interrupt Request Signals ......................................................................................................601 17.6 Operation .................................................................................................................................602 17.6.1 Data format ............................................................................................................................... 602 17.6.2 UART transmission ................................................................................................................... 604 17.6.3 Continuous transmission procedure .......................................................................................... 605 17.6.4 UART reception......................................................................................................................... 607 17.6.5 Reception ...
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CHAPTER BUS .......................................................................................................................... 678 2 19.1 Mode Switching 19.1.1 UARTA2 and I 2 19.1.2 CSIB0 and I C01 mode switching ..............................................................................................679 2 19.1.3 UARTA1 and I 19.2 Features ...................................................................................................................................681 19.3 Configuration...........................................................................................................................682 19.4 Registers ...
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DMA Channel Priorities ..........................................................................................................770 20.8 Time Related to DMA Transfer ..............................................................................................771 20.9 DMA Transfer Start Factors ...................................................................................................772 20.10 DMA Abort Factors .................................................................................................................773 20.11 End of DMA Transfer ..............................................................................................................773 20.12 Operation Timing ....................................................................................................................773 20.13 Cautions...................................................................................................................................778 CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING ...
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CHAPTER 23 STANDBY FUNCTION .................................................................................................. 825 23.1 Overview ..................................................................................................................................825 23.2 Registers ..................................................................................................................................827 23.3 HALT Mode ..............................................................................................................................832 23.3.1 Setting and operation status ......................................................................................................832 23.3.2 Releasing HALT mode...............................................................................................................832 23.4 IDLE1 Mode..............................................................................................................................834 23.4.1 Setting and operation status ......................................................................................................834 23.4.2 Releasing IDLE1 mode..............................................................................................................835 23.5 ...
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CHAPTER 26 LOW-VOLTAGE DETECTOR (LVI)..............................................................................882 26.1 Functions .................................................................................................................................882 26.2 Configuration ..........................................................................................................................882 26.3 Registers..................................................................................................................................883 26.4 Operation .................................................................................................................................885 26.4.1 To use for internal reset signal .................................................................................................. 885 26.4.2 To use for interrupt .................................................................................................................... 886 CHAPTER 27 CRC FUNCTION ............................................................................................................887 27.1 Functions .................................................................................................................................887 ...
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Registers ...................................................................................................................................931 31.1.5 Operation...................................................................................................................................932 31.1.6 Cautions ....................................................................................................................................933 31.2 Debugging Without Using DCU .............................................................................................934 31.2.1 Circuit connection examples......................................................................................................934 31.2.2 Mask function ............................................................................................................................936 31.2.3 Allocation of user resources ......................................................................................................937 31.2.4 Cautions ....................................................................................................................................944 31.3 ROM Security Function ..........................................................................................................945 31.3.1 Security ID .................................................................................................................................945 ...
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Main clock oscillator characteristics .......................................................................................... 988 33.4.2 Subclock oscillator characteristics............................................................................................. 990 33.4.3 PLL characteristics .................................................................................................................... 991 33.4.4 Internal oscillator characteristics ............................................................................................... 991 33.5 Regulator Characteristics ......................................................................................................992 33.6 DC Characteristics..................................................................................................................993 33.6.1 Pin characteristics ..................................................................................................................... 993 33.6.2 Supply current characteristics ................................................................................................... ...
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APPENDIX D INSTRUCTION SET LIST ........................................................................................... 1052 D.1 Conventions.......................................................................................................................... 1052 D.2 Instruction Set (in Alphabetical Order) .............................................................................. 1055 APPENDIX E REVISION HISTORY.................................................................................................... 1062 E.1 Major Revisions in This Edition.......................................................................................... 1062 E.2 Revision History of Previous Editions............................................................................... 1063 22 User’s Manual ...
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The V850ES/JG3-L is one of the products in the NEC Electronics V850 single-chip microcontroller series designed for low-power operation for real-time control applications. 1.1 General The V850ES/JG3 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral ...
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Generic Name Part Number Internal Flash memory memory RAM Memory Logical space space External memory area External bus interface General-purpose register Clock Main clock (oscillation frequency) Subclock (oscillation frequency) Internal oscillator Minimum instruction execution time I/O port Timer 16-bit ...
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Features <R> Minimum instruction execution time (operating on main clock (f General-purpose registers: CPU features: Memory space: • Internal memory: • External bus interface: Separate bus/multiplexed bus output selectable Interrupts and exceptions: μ PD70F3737 μ PD70F3738 μ ...
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Timer function: 16-bit interval timer M (TMM): 16-bit timer/event counter P (TMP): 6 channels 16-bit timer/event counter Q (TMQ): 1 channel Watch timer: Watchdog timer: 1 channel Note Real-time counter : 1 channel 6 bits × 1 channel Real-time output ...
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Application Fields Digital cameras, electrical power meters, mobile terminals, digital home electronics, other consumer devices 1.4 Ordering Information <R> Part Number μ PD70F3737GC-UEU-AX μ PD70F3738GC-UEU-AX μ Note PD70F3737GF-GAS-AX μ Note PD70F3738GF-GAS-AX μ PD70F3737F1-CAH-A μ PD70F3738F1-CAH-A μ Note PD70F3792GC-UEU-AX μ ...
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Pin Configuration (Top View) 100-pin plastic LQFP (14 × 20) μ Note PD70F3737GF-GAS-AX Note Under development P71/ANI1 P70/ANI0 AV REF0 AV SS P10/ANO0 P11/ANO1 AV REF1 PDH4/A20 PDH5/A21 Note 1 FLMD0 V DD Note 2 REGC ...
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LQFP (fine pitch) (14 × 14) (1/2) μ μ PD70F3737GC-UEU-AX PD70F3738GC-UEU- REF0 P10/ANO0 P11/ANO1 REF1 PDH4/A20 6 PDH5/A21 7 Note 1 FLMD0 Note 2 REGC ...
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LQFP (fine pitch) (14 × 14) (2/2) μ Note PD70F3792GC-UEU-AX <R> Note Under development AV REF0 AV SS P10/ANO0 P11/ANO1 AV REF1 PDH4/A20 P02/NMI/A21 Note 1 FLMD0 V DD Note 2 REGC RESET XT1 ...
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FBGA (8 × 8) μ PF70F3737F1-CAH-A <R> Note Under development Pin No. Pin Name A1 AV REF0 A2 AV REF0 A3 P70/ANI0 A4 P74/ANI4 A5 P78/ANI8 PDL11/AD11 A8 PDL8/AD8 A9 PDL6/AD6 A10 PDL5/AD5/FLMD1 A11 ...
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Pin No. Pin Name P03/INTP0/ADTRG Note1 (/RTC1HZ) Note2 G4 PDH5/A21 Note1, 3 P02/NMI/A21 P915/A15/INTP6/TIP50/TOP50 G9 P914/A14/INTP5/TIP51/TOP51 G10 P913/A13/INTP4 G11 P912/A12/SCKB3 H1 XT1 H2 ...
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Pin functions A0 to A21: Address bus AD0 to AD15: Address/data bus ADTRG: A/D trigger input Analog input ANI0 to ANI11: ANO0, ANO1: Analog output ASCKA0: Asynchronous serial clock ASTB: Address strobe Analog reference voltage ...
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Function Block Configuration <R> 1.6.1 Internal block diagram Timer/counter function TIP00 to TIP50, TIP01 to TIP51 event counter P: TOP00 to TOP50, TOP01 to TOP51 TIQ00 to TIQ03 event counter Q: TOQ00 to TOQ03 16-bit interval timer 2: 1ch ...
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Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Real-time counter (for watch) ( The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768 kHz) or main clock. This can simultaneously be used as the interval timer based on the ...
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DCU (debug control unit) An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input level and ...
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List of Pin Functions The functions of the pins in the V850ES/JG3-L are described below. There are three types of pin I/O buffer power supplies: AV power supplies and the pins is described below. Power Supply AV REF0 AV ...
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Port functions <R> Function Pin No. I Note 1 P02 J2, I/O Note 2 Note P03 P04 Note 3 P05 P06 ...
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Function Pin No. I P70 Port 7 (refer to 4.3.6) 2 100 A3 I/O 12-bit I/O port P71 Input/output can be specified in 1-bit units. P72 100 98 C3 P73 P74 ...
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Function Pin No. I Port CM (refer to 4.3.8) PCM0 63 61 F11 I/O 4-bit I/O port PCM1 64 62 F10 Input/output can be specified in 1-bit units. PCM2 65 63 E10 PCM3 Port ...
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Non-port functions <R> Function Pin No. I Output Address bus for external memory L10 ...
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Function Pin No. I ADTRG Input A/D converter external trigger input tolerant. ANI0 2 100 A3 Input Analog voltage input for A/D converter ANI1 ANI2 100 98 C3 ANI3 ...
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Function Pin No. I INTP0 Input INTP1 INTP2 INTP3 INTP4 58 56 G10 INTP5 INTP6 INTP7 ...
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Function Pin No. I RXDA0 Input Serial receive data input (UARTA0 to UARTA2 tolerant. RXDA1 RXDA2 − Note RXDA3 32 J6 − Note RXDA4 46 J9 ...
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Function Pin No. I TIP00 Input External event count input/capture trigger input/external trigger input (TMP0 tolerant. Capture trigger input (TMP0). TIP01 tolerant. TIP10 External ...
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Function Pin No. I TOP00 Output TOP01 TOP10 TOP11 TOP20 52 50 J11 TOP21 51 49 K11 TOP30 50 48 K10 TOP31 49 47 L10 ...
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Pin States The operation states of pins in the various modes are described below. <R> Pin Name When Power During Reset Is Turned (Except When Note 1 On P05/DRST Pulled down P10/ANO0, Undefined P11/ANO1 P53/DDO Note 8 AD0 to ...
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Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins Pin Alternate Function Note1 P02 NMI (/A21) P03 INTP0/ADTRG (/RTC1HZ) P04 INTP1 (/RTCDIV/RTCLL) P05 INTP2/DRST P06 INTP3 P10, P11 ANO0, ANO1 P30 TXDA0/SOB4 P31 RXDA0/INTP7/SIB4 ...
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Pin Alternate Function P70 to ANI0 to ANI11 P711 P90 A0/KR6/TDXA1/SDA02 P91 A1/KR7/RXDA1/SCL02 P92 A2/TIP41/TOP41 (/TXDA4) P93 A3/TIP40/TOP40 (/RXDA4) P94 A4/TIP31/TOP31 (/TXDA5) P95 A5/TIP30/TOP30 (/RXDA5) Note1 P96 A6 (/TXDC0) /TIP21/TOP21 Note1 P97 A7/SIB1 (/RXDC0) /TIP20/ TOP20 P98 A8/SOB1 P99 ...
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Pin Alternate Function GF PDL6 to AD6 to AD15 PDL15 − − Note1 RV DD − REF0 − REF1 − − − ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5 EV Data Output disable Input enable Type 10-D Data Open drain Output disable Note Input enable Type 10-G Data Open drain Output disable Input enable Note Hysteresis characteristics are not ...
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Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P10/ANO0 pin • P11/ANO1 pin • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin CHAPTER 2 PIN FUNCTIONS User’s Manual U18953EJ5V0UD 53 ...
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The CPU of the V850ES/JG3-L is based on RISC architecture and executes almost all instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features Variable length instructions (16 bits/32 bits) Minimum instruction execution time (operating on ...
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CPU Register Set The registers of the V850ES/JG3-L can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program ...
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Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data variable ...
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System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. ...
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Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to ...
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NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those ...
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Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this ...
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Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a ...
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Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the ...
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Operation Modes The V850ES/JG3-L has the following operation modes. • Normal operation mode • Flash memory programming mode • Self programming mode • On-chip debug mode The operation mode is specified according to the status (input level) of the ...
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Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) ...
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Memory map The areas shown below are reserved in the V850ES/JG3-L. Figure 3-2. Data Memory Map (Physical Addresses Image ...
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Note The V850ES/JG3-L has 22 address pins, so the external memory area appears as a repeated 4 MB image. 66 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map Use prohibited ...
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Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (128 KB) 128 KB are allocated to addresses 00000000H to 0001FFFFH in the Accessing addresses 00020000H to 000FFFFFH is prohibited. ...
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Internal ROM (384 KB) 384 KB are allocated to addresses 00000000H to 0005FFFFH in the Accessing addresses 00060000H to 000FFFFFH is prohibited. (d) Internal ROM (512 KB) <R> 512 KB are allocated to addresses 00000000H to 0007FFFFH in ...
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Internal RAM area allocated to physical addresses 03FF0000H to 03FFEFFFH are reserved as the internal RAM area. (a) Internal RAM (8 KB are allocated to addresses 03FFD000H to 03FFEFFFH of the Accessing addresses ...
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Internal RAM (32 KB) <R> are allocated to addresses 03FF7000H to 03FFEFFFH of the Accessing addresses 03FF0000H to 03FF6FFFH is prohibited. Physical address space (d) Internal RAM (40 KB) <R> are allocated to addresses 03FF5000H ...
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On-chip peripheral I/O area 4 KB allocated to physical addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-12. On-Chip Peripheral I/O Area Physical address space ...
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Wraparound of data space The result of an operand address calculation operation that exceeds 32 bits is ignored. Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are contiguous, and wraparound occurs at the ...
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Data space With the V850ES/JG3-L, it seems that there are sixty-four 64 MB (26-bit address) physical address spaces on the 4 GB (32-bit address) CPU address space. Therefore, the most significant bit (bit 25 26-bit address of ...
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Application example of wraparound (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can ...
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Figure 3-16. Recommended Memory Map ( Program space ...
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Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H FFFFF006H Port DH register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF024H Port DL mode register ...
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Address Function Register Name FFFFF0D2H DMA addressing control register 1 FFFFF0D4H DMA addressing control register 2 FFFFF0D6H DMA addressing control register 3 FFFFF0E0H DMA channel control register 0 FFFFF0E2H DMA channel control register 1 FFFFF0E4H DMA channel control register 2 ...
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Address Function Register Name FFFFF140H Interrupt control register (INTTP3CC0) FFFFF142H Interrupt control register (INTTP3CC1) FFFFF144H Interrupt control register (INTTP4OV) FFFFF146H Interrupt control register (INTTP4CC0) FFFFF148H Interrupt control register (INTTP4CC1) FFFFF14AH Interrupt control register (INTTP5OV) FFFFF14CH Interrupt control register (INTTP5CC0) FFFFF14EH ...
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Address Function Register Name FFFFF200H A/D converter mode register 0 FFFFF201H A/D converter mode register 1 FFFFF202H A/D converter channel specification register FFFFF203H A/D converter mode register 2 FFFFF204H Power-fail compare mode register FFFFF205H Power-fail compare threshold value register FFFFF210H ...
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Address Function Register Name FFFFF331H Regulator protection register FFFFF332H Regulator output voltage level control register FFFFF340H IIC division clock select register FFFFF344H IIC division clock select register FFFFF380H Clock through select register FFFFF400H Port 0 register FFFFF402H Port 1 register ...
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Address Function Register Name FFFFF468H Port 4 function control register FFFFF46AH Port 5 function control register FFFFF472H Port 9 function control register FFFFF472H Port 9 function control register L FFFFF473H Port 9 function control register H FFFFF484H Data wait control ...
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Address Function Register Name FFFFF5B8H TMP2 capture/compare register 1 FFFFF5BAH TMP2 counter read buffer register FFFFF5C0H TMP3 control register 0 FFFFF5C1H TMP3 control register 1 FFFFF5C2H TMP3 I/O control register 0 FFFFF5C3H TMP3 I/O control register 1 FFFFF5C4H TMP3 I/O ...
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Address Function Register Name FFFFF712H Port 9 function control expansion register FFFFF712H Port 9 function control expansion register L FFFFF713H Port 9 function control expansion register H FFFFF802H System status register FFFFF80CH Internal oscillation mode register FFFFF810H DMA trigger factor ...
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Address Function Register Name FFFFFA30H UARTA3 control register 0 FFFFFA31H UARTA3 control register 1 FFFFFA32H UARTA3 control register 2 FFFFFA33H UARTA3 option control register 0 FFFFFA34H UARTA3 status register FFFFFA36H UARTA3 receive data register FFFFFA37H UARTA3 transmit data register FFFFFA40H ...
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Address Function Register Name FFFFFADDH RTC control register 0 FFFFFADEH RTC control register 1 FFFFFADFH RTC control register 2 FFFFFAE0H RTC control register 3 FFFFFB00H RTC backup control register 0 FFFFFB03H Subclock low-power operation control register FFFFFC00H External interrupt falling ...
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Address Function Register Name FFFFFD22H CSIB2 control register 2 FFFFFD23H CSIB2 status register FFFFFD24H CSIB2 receive data register FFFFFD24H CSIB2 receive data register L FFFFFD26H CSIB2 transmit data register FFFFFD26H CSIB2 transmit data register L FFFFFD30H CSIB3 control register 0 ...
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Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JG3-L has the following nine special registers. • Power save control register (PSC) • Clock control register (CKC) ...
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Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in ...
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Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1). Caution When a store instruction is executed to store data in the command ...
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System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After ...
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Registers to be set first Be sure to set the following registers first when using the V850ES/JG3-L. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After setting the ...
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Cautions (1) Accessing special on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the ...
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Conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction ...
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Features μ I/O port pins PD70F3737, 70F3738) μ PD70F3792, 70F3793) <R> • N-ch open-drain output selectable tolerant: 31) Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JG3-L features a total ...
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Port Configuration The ports consist of the following hardware. Item Control registers Port n mode register (PMn CD, CM, CT, DH, DL) Port n mode control register (PMCn ...
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Port n register (Pn) Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is made port latch that retains the output data and a circuit that ...
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Port n mode register (PMn) PMn specifies the input mode or output mode of the port. Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: FFH ...
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Port n function control register (PFCn) PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate functions. Each bit of the PFCn register corresponds to one pin of port ...
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Port n function register (PFn) PFn is a register that specifies normal output (CMOS output) or N-ch open-drain output. Each bit of the PFn register corresponds to one pin of port n and can be specified in 1-bit units. ...
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Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate function ...
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Port 0 Port 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. <R> Pin No. Function Name Note1 17 , J2, 19 P02 ...
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Port 0 mode register (PM0) After reset: FFH PM0 1 PM0n 0 1 <R> (3) Port 0 mode control register (PMC0) After reset: 00H PMC0 0 PMC06 0 1 PMC05 0 1 PMC04 0 1 PMC03 0 1 PMC02 ...
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Port 0 function control register (PFC0) After reset: 00H PFC0 0 μ Note PD70F3792, 70F3793 only Remark For details of alternate function specification, see 4.3.1 (6) specifications. <R> (5) Port 0 function control expansion register (PFCE0) ( After ...
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Port 0 function register (PF0) After reset: 00H R/W PF0 0 PF06 PF0n Specification of normal output (CMOS output) or N-ch open-drain output ( Normal output (CMOS output) 1 N-ch open-drain output Caution When ...
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Port 1 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Pin No. Function Name P10 ANO0 6 4 ...
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Port 1 mode register (PM1) After reset: FFH R/W PM1 1 PM1n 0 Output mode 1 Input mode Cautions 1. When using P1n as the alternate function (ANOn pin output), specify the input mode (PM1n bit = 1). 2. ...
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Port 3 Port 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Pin No. Function Name P30 ...
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Port 3 register (P3) After reset: 0000H (output latch (P3H) 0 (P3L) P37 P3n 0 Outputs 0 1 Outputs 1 Remarks 1. The P3 register can be read or written in 16-bit units. However, when using the ...
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Port 3 mode control register (PMC3) After reset: 0000H PMC3 (PMC3H) (PMC3L) μ Note PD70F3792, 70F3793 only Caution Be sure to clear bits “0”. Remarks 1. The PMC3 register can be read or written ...
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Port 3 function control register (PFC3) After reset: 0000H 15 PFC3 (PFC3H) 0 (PFC3L) 0 Remarks 1. For details of alternate function specification, see 4.3.3 (6) specifications. 2. The PFC3 register can be read or written in 16-bit units. ...
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Port 3 alternate function specifications PFC39 0 RXDA2 input 1 SCL00 I/O PFC38 0 TXDA2 output 1 SDA00 I/O PFC35 0 TIP11 input 1 TOP11 output PFC34 0 TIP10 input 1 TOP10 output PFC33 0 TIP01 input 1 TOP01 ...
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Port 3 function register (PF3) After reset: 0000H 15 PF3 (PF3H) 0 (PF3L) PF37 PF3n 0 1 Caution When an output pin is pulled Remarks 1. The PF3 register can be read or written in 16-bit ...
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Port 4 Port 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Pin No. Function Name P40 SIB0/SDA01 P41 SOB0/SCL01 26 ...
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Port 4 mode control register (PMC4) After reset: 00H R/W PMC4 0 PMC42 0 I/O port (P42) 1 SCKB0 I/O PMC41 0 I/O port (P41) 1 SOB0 output/SCL01 I/O PMC40 0 I/O port (P40) 1 SIB0 input/SDA01 I/O (4) ...
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Port 5 Port 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Pin No. Function Name P50 TIQ01/KR0/TOQ01/RTP00 P51 TIQ02/KR1/TOQ02/RTP01 41 ...
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Port 5 mode register (PM5) After reset: FFH R/W PM5 1 PM5n 0 Output mode 1 Input mode (3) Port 5 mode control register (PMC5) After reset: 00H R/W PMC5 0 PMC55 0 I/O port (P55) 1 SCKB2 I/O/KR5 ...
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Port 5 function control register (PFC5) After reset: 00H R/W PFC5 0 0 Remark For details of alternate function specification, see 4.3.5 (6) specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H R/W PFCE5 0 0 ...
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PFCE52 PFC52 PFCE51 PFC51 PFCE50 PFC50 Note KRn and TIQ0m are alternate functions. When using the ...
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Port 5 function register (PF5) After reset: 00H R/W PF5 0 0 PF5n Specification of normal output (CMOS output) or N-ch open-drain output ( Normal output (CMOS output) 1 N-ch open-drain output Cautions 1. ...
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Port 7 Port 12-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Pin No. Function Name 100 A3 P70 ANI0 1 99 ...
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Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) P7H 0 0 P77 P76 P7L P7n 0 Outputs 0 1 Outputs 1 Caution Do not read or write the P7H and P7L registers ...
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Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. <R> Pin No. Function Name P90 A0/KR6/TXDA1/SDA02 46 ...
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Port 9 register (P9) After reset: 0000H (output latch (P9H) P915 P914 (P9L) P97 P96 P9n 0 Outputs 0 1 Outputs 1 Remarks 1. The P9 register can be read or written in 16-bit units. However, ...
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Port 9 mode control register (PMC9) After reset: 0000H PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 Remarks 1. The PMC9 register can be read or written in ...
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CHAPTER 4 PORT FUNCTIONS PMC97 0 I/O port (P97 output/SIB1 input (/RXDC0 input) PMC96 0 I/O port (P96 output (/TXDC0 output) PMC95 0 I/O port (P95 output/TIP30 input/TOP30 output (/RXDA5 input) PMC94 0 I/O ...
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Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 and PFCE9 registers to 0000H. After reset: ...
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Port 9 alternate function specifications PFCE915 PFC915 PFCE914 PFC914 PFC913 0 A13 output 1 INTP4 input PFC912 0 A12 output 1 SCKB3 ...
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PFCE96 PFC96 PFCE95 PFC95 PFCE94 PFC94 PFCE93 PFC93 ...
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Port 9 function register (PF9) After reset: 0000H 15 PF9 (PF9H) PF915 PF914 (PF9L) PF97 PF96 PF9n Specification of normal output (CMOS output) or N-ch open-drain output ( 15) 0 Normal output (CMOS output) 1 N-ch ...
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Port CM Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-11. Port CM Alternate-Function Pins Pin No. Function Name ...
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Port CM mode control register (PMCCM) After reset: 00H R/W PMCCM 0 0 PMCCM3 0 I/O port (PCM3) 1 HLDRQ input PMCCM2 0 I/O port (PCM2) 1 HLDAK output PMCCM1 0 I/O port (PCM1) 1 CLKOUT output PMCCM0 0 ...
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Port CT Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-12. Port CT Alternate-Function Pins Pin No. Function Name ...
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Port CT mode control register (PMCCT) After reset: 00H R/W PMCCT 0 PMCCT6 PMCCT6 0 I/O port (PCT6) 1 ASTB output PMCCT4 0 I/O port (PCT4 output PMCCT1 0 I/O port (PCT1) 1 WR1 output PMCCT0 0 ...
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Port DH Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-13. Port DH Alternate-Function Pins Pin No. Function Name ...
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Port DH mode register (PMDH) After reset: FFH R/W PMDH 1 1 PMDHn 0 Output mode 1 Input mode μ Note PD70F3737, 70F3738 only (3) Port DH mode control register (PMCDH) After reset: 00H R/W PMCDH 0 0 PMCDHn ...
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Port DL Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-14. Port DL Alternate-Function Pins Pin No. Function Name ...
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Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 PDL14 (PDLL) PDL7 PDL6 PDLn 0 Outputs 0 1 Outputs 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when ...
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Port DL mode control register (PMCDL) After reset: 0000H 15 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Cautions 1. When the SMSEL bit of the EXIMC ...
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Block Diagrams PORT RD CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of Type A-1 PMmn Pmn Address P-ch A/D input signal N-ch User’s Manual U18953EJ5V0UD Pmn 139 ...
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PORT RD 140 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A-2 PMmn Pmn Address P-ch D/A output signal N-ch User’s Manual U18953EJ5V0UD Pmn ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type C PFmn WR PM PMmn WR PORT Pmn Address RD User’s Manual U18953EJ5V0UD EV DD P-ch Pmn N- 141 ...
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WR PMC PORT RD alternate function is used 142 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D-1 PMCmn PMmn Pmn Address Input signal when User’s Manual U18953EJ5V0UD Pmn ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-2 WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD User’s Manual U18953EJ5V0UD Pmn 143 ...
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WR PMC PMCmn Output enable signal of address/data bus Output buffer off signal WR PM PMmn Output signal when alternate function is used WR PORT Input enable signal of address/data bus Input signal when alternate function is used RD 144 ...
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Figure 4-9. Block Diagram of Type E PFmn Output enable signal when alternate function is used WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate ...
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WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note There are no hysteresis characteristics in port mode. ...
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Figure 4-11. Block Diagram of Type G PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note There ...
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WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD 148 CHAPTER 4 PORT FUNCTIONS Figure 4-12. ...
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Figure 4-13. Block Diagram of Type G PFmn Output enable signal when alternate function is used WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate ...
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WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal 1 when alternate function is used Input signal 2 when alternate function is used ...
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Figure 4-15. Block Diagram of Type G- PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used Notes 1. See 21.7 External Interrupt Request Input ...
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Figure 4-17. Block Diagram of Type N PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when Edge alternate ...
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WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when detection alternate function ...
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Figure 4-19. Block Diagram of Type N PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when Edge alternate ...
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WR PF PFmn Output enable signal whenalternate WR PFCE function is used PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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Figure 4-21. Block Diagram of Type U PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal ...
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Figure 4-23. Block Diagram of Type U PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is ...
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WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal ...
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Figure 4-25. Block Diagram of Type U PFmn WR OCDM0 OCDM0 Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used WR ...
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Figure 4-27. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when RD alternate ...
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Figure 4-29. Block Diagram of Type U- PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal 1 when ...
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Figure 4-31. Block Diagram of Type U- PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used ...
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WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used ...
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Figure 4-33. Block Diagram of Type AA PFmn External reset signal WR OCDM0 OCDM0 WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when ...
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Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port pin is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of ...
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Table 4-15. Settings When Pins Are Used for Alternate Functions (1/7) Function Alternate Function Pnx Bit of Name Pn Register Name I/O Input P02 NMI P02 = Setting not required Note1 A21 Input P02 = Setting not required Input P03 ...
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Table 4-15. Settings When Pins Are Used for Alternate Functions (2/7) Function Alternate Function Pnx Bit of Name Pn Register Name I/O P34 Input P34 = Setting not required TIP10 Output P34 = Setting not required TOP10 Input P35 TIP11 ...
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Table 4-15. Settings When Pins Are Used for Alternate Functions (3/7) Function Alternate Function Pnx Bit of Name Pn Register Name I/O Input P51 TIQ02 P51 = Setting not required Input KR1 P51 = Setting not required Output TOQ02 P51 ...
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Table 4-15. Settings When Pins Are Used for Alternate Functions (4/7) Function Alternate Function Pnx Bit of Name Pn Register Name I/O P70 ANI0 Input P70 = Setting not required P71 ANI1 Input P71 = Setting not required P72 ANI2 ...
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Table 4-15. Settings When Pins Are Used for Alternate Functions (5/7) Function Alternate Function Pnx Bit of Name Pn Register Name I/O P92 A2 Output P92 = Setting not required TIP41 Input P92 = Setting not required TOP41 Output P92 ...
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Table 4-15. Settings When Pins Are Used for Alternate Functions (6/7) Function Alternate Function Pnx Bit of Name Pn Register Name I/O P910 A10 Output P910 = Setting not required SIB3 Input P910 = Setting not required P911 A11 Output ...
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Table 4-15. Settings When Pins Are Used for Alternate Functions (7/7) Function Alternate Function Pnx Bit of Name Pn Register Name I/O A16 Output PDH0 PDH0 = Setting not required Output PDH1 A17 PDH1 = Setting not required PDH2 A18 ...
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Cautions 4.6.1 Cautions on setting port pins (1) In the V850ES/JG3-L, general-purpose port pins are shared with several peripheral I/O functions. To switch between using a pin as a general-purpose port pin (port mode) and as a peripheral function ...
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CHAPTER 4 PORT FUNCTIONS The setting order that may cause a malfunction when switching from the P41 pin function to the SCL01 pin function is shown below. Setting Order <1> Initial value (PMC41 bit = 0, PFC41 bit = 0, ...
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Figure 4-34. Example of Switching from P02 to NMI (Incorrect) PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Remark [Example 2] Switching from external pin (NMI) to general-purpose ...
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Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions or port/alternate functions, the value of the output latch of an input ...
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Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST high ...
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CHAPTER 5 BUS CONTROL FUNCTION The external bus interface function is used to connect external devices to areas other than the internal ROM, RAM, or on-chip I/O registers via ports 9, CM, CT, DL, and DH. These ports control address/data ...
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Bus Control Pins The following signals can be used to control an external device in each bus mode. Table 5-1. Bus Control Signals (When Multiplexed Bus Is Selected) Bus Control I/O Signal AD0 to AD15 I/O Address/data bus <R> ...
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Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed When the internal ROM, internal RAM, or on-chip peripheral I/O is accessed, the status of each pin is as follows. Table 5-3. Pin Statuses When Internal ...
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Memory Block Function The lower the 64 MB memory space is reserved for external memory expansion and is divided into memory blocks of 2 MB, 2 MB, 4 MB, and 8 MB. independently specified for each ...
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External Bus Interface Mode Control Function The V850ES/JG3-L includes the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus interface ...
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Bus Access 5.5.1 Number of clock cycles required for access The following table shows the number of basic clock cycles required for accessing each resource. Table 5-4. Number of Clock Cycles Required for Access Area (Bus Width) Bus Cycle ...
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Bus size setting function The external memory area of the V850ES/JG3-L is selected by memory blocks The bus size of each external memory area selected by memory block n can be set (to 8 bits or ...
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Access according to bus size The V850ES/JG3-L accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to ...
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CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width 8-bit data is transmitted/received via a 16-bit bus. Therefore even address is specified, the lower byte of the external data bus address is ...
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Halfword access (16 bits) (a) 16-bit data bus width 16-bit data is transmitted/received via a 16-bit bus. Therefore even address is specified, the lower and higher bytes of the external data bus address are accessed at the ...
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CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) 32-bit data is transmitted/received via a 16-bit bus. Therefore even address is specified, the data is transmitted/received in two accesses in 16-bit ...
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Access to address ( First access Address Word data External data bus <4> ...
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CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) 32-bit data is transmitted/received via an 8-bit bus. Therefore, the data is transmitted/received in four accesses. The data is transmitted/received to/from the specified even/odd address of the external data ...
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Access to address ( First access Second access Address Word ...
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Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O device seven data wait states can be inserted in the bus cycle that is executed ...
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External wait function To synchronize a low-speed device or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal ...