LM3S5791-IBZ80-C1T

Manufacturer Part NumberLM3S5791-IBZ80-C1T
DescriptionIC ARM CORTEX MCU 128KB 108NFBGA
ManufacturerTexas Instruments
SeriesStellaris® 5000
LM3S5791-IBZ80-C1T datasheet
 


Specifications of LM3S5791-IBZ80-C1T

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed80MHzConnectivityCAN, EBI/EMI, I²C, IrDA, LIN, Microwire, QEI, SPI, SSI, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, DMA, I²S, POR, PWM, WDTNumber Of I /o72
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size64K x 8Voltage - Supply (vcc/vdd)1.08 V ~ 1.32 V
Data ConvertersA/D 16x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case108-NFBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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T E X AS I NS TR UM E NTS - ADVANCE I NFO R MAT I O N
Stellaris® LM3S5791 Microcontroller
D ATA S H E E T
D S -L M3 S5 79 1- 95 38
Co pyri gh t © 20 07 -2 011
Texa s Instrument s I nco rp orat ed

LM3S5791-IBZ80-C1T Summary of contents

  • Page 1

    ... Stellaris® LM3S5791 Microcontroller NTS - ADVANCE I NFO R MAT ATA pyri gh t © 011 Texa s Instrument s I nco rp orat ed ...

  • Page 2

    ... ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ...

  • Page 3

    ... Memory System Ordering of Memory Accesses .............................................................. 97 2.4.3 Behavior of Memory Accesses ....................................................................................... 97 2.4.4 Software Ordering of Memory Accesses ......................................................................... 98 2.4.5 Bit-Banding ................................................................................................................... 99 2.4.6 Data Storage .............................................................................................................. 101 2.4.7 Synchronization Primitives ........................................................................................... 102 2.5 Exception Model ......................................................................................................... 103 2.5.1 Exception States ......................................................................................................... 103 2.5.2 Exception Types .......................................................................................................... 104 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 3 ...

  • Page 4

    ... Functional Description ................................................................................................. 196 5.2.1 Device Identification .................................................................................................... 197 5.2.2 Reset Control .............................................................................................................. 197 5.2.3 Non-Maskable Interrupt ............................................................................................... 202 5.2.4 Power Control ............................................................................................................. 202 5.2.5 Clock Control .............................................................................................................. 203 5.2.6 System Control ........................................................................................................... 210 5.3 Initialization and Configuration ..................................................................................... 211 5.4 Register Map .............................................................................................................. 211 4 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 5

    ... Pad Control ................................................................................................................. 400 8.2.6 Identification ............................................................................................................... 400 8.3 Initialization and Configuration ..................................................................................... 400 8.4 Register Map .............................................................................................................. 401 8.5 Register Descriptions .................................................................................................. 404 9 External Peripheral Interface (EPI) ..................................................................... 447 9.1 EPI Block Diagram ...................................................................................................... 448 9.2 Signal Description ....................................................................................................... 449 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 5 ...

  • Page 6

    ... Differential Sampling ................................................................................................... 602 12.3.6 Internal Temperature Sensor ........................................................................................ 605 12.3.7 Digital Comparator Unit ............................................................................................... 605 12.4 Initialization and Configuration ..................................................................................... 610 12.4.1 Module Initialization ..................................................................................................... 610 12.4.2 Sample Sequencer Configuration ................................................................................. 611 12.5 Register Map .............................................................................................................. 611 12.6 Register Descriptions .................................................................................................. 613 6 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 7

    ... Register Descriptions (I 15.7 Register Descriptions (I 16 Inter-Integrated Circuit Sound (I 16.1 Block Diagram ............................................................................................................ 813 16.2 Signal Description ....................................................................................................... 813 16.3 Functional Description ................................................................................................. 815 March 19, 2011 2 C) Interface ................................................................ 775 2 C Master) ............................................................................... 791 2 C Slave) ................................................................................. 803 2 S) Interface .................................................... 812 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 7 ...

  • Page 8

    ... Register Descriptions .................................................................................................. 925 19 Analog Comparators .......................................................................................... 1037 19.1 Block Diagram ........................................................................................................... 1038 19.2 Signal Description ..................................................................................................... 1038 19.3 Functional Description ............................................................................................... 1039 19.3.1 Internal Reference Programming ................................................................................ 1040 19.4 Initialization and Configuration .................................................................................... 1042 19.5 Register Map ............................................................................................................ 1042 19.6 Register Descriptions ................................................................................................. 1043 8 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 9

    ... Power and Brown-out Characteristics ......................................................................... 1241 25.2.4 JTAG and Boundary Scan .......................................................................................... 1243 25.2.5 Reset ........................................................................................................................ 1245 25.2.6 Sleep Modes ............................................................................................................. 1246 25.2.7 General-Purpose I/O (GPIO) ...................................................................................... 1246 25.2.8 External Peripheral Interface (EPI) .............................................................................. 1247 25.2.9 Analog-to-Digital Converter (ADC) .............................................................................. 1252 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 9 ...

  • Page 10

    ... Package Dimensions ................................................................................................. 1312 C.1.2 Tray Dimensions ....................................................................................................... 1314 C.1.3 Tape and Reel Dimensions ........................................................................................ 1314 C.2 108-Ball BGA Package .............................................................................................. 1316 C.2.1 Package Dimensions ................................................................................................. 1316 C.2.2 Tray Dimensions ....................................................................................................... 1318 C.2.3 Tape and Reel Dimensions ........................................................................................ 1319 Interface ......................................................................... 1255 2 S) Interface ............................................................... 1256 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 11

    ... List of Figures Figure 1-1. Stellaris LM3S5791 Microcontroller High-Level Block Diagram .............................. 73 Figure 2-1. CPU Block Diagram ............................................................................................. 77 Figure 2-2. TPIU Block Diagram ............................................................................................ 78 Figure 2-3. Cortex-M3 Register Set ........................................................................................ 80 Figure 2-4. Bit-Band Mapping .............................................................................................. 101 Figure 2-5. Data Storage ..................................................................................................... 102 Figure 2-6. Vector table ....................................................................................................... 108 Figure 2-7. ...

  • Page 12

    ... Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 741 Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 742 Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 742 12 = 1.5 V ...................................................... 603 IN_ODD = 0.75 V .................................................... 604 IN_ODD = 2.25 V .................................................... 604 IN_ODD Texas Instruments-Advance Information March 19, 2011 ...

  • Page 13

    ... Power-On Reset and Voltage Parameters ......................................................... 1243 Figure 25-7. Voltage Requirements When Using an External V Figure 25-8. JTAG Test Clock Input Timing ........................................................................... 1244 Figure 25-9. JTAG Test Access Port (TAP) Timing ................................................................ 1245 March 19, 2011 2 C Bus ................................................... 779 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Source ............................. 1243 DDC 13 ...

  • Page 14

    ... LQFP Tray Dimensions ........................................................................ 1314 Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1315 Figure C-4. 108-Ball BGA Package Dimensions .................................................................. 1316 Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1318 Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1319 14 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 15

    ... Table 7-2. Request Type Support ....................................................................................... 336 Table 7-3. Control Structure Memory Map ........................................................................... 337 Table 7-4. Channel Control Structure .................................................................................. 337 Table 7-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 346 Table 7-6. μDMA Interrupt Assignments .............................................................................. 347 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 15 ...

  • Page 16

    ... Flow Control Mode ............................................................................................. 679 Table 13-4. UART Register Map ........................................................................................... 683 Table 14-1. Signals for SSI (100LQFP) ................................................................................. 734 Table 14-2. Signals for SSI (108BGA) ................................................................................... 734 Table 14-3. SSI Register Map .............................................................................................. 746 Table 15-1. Signals for I2C (100LQFP) ................................................................................. 776 16 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 17

    ... Possible Pin Assignments for Alternate Functions .............................................. 1228 Table 23-12. Connections for Unused Signals (100-pin LQFP) ............................................... 1231 March 19, 2011 2 C Master Timer Period versus Speed Mode ................................... 780 2 C) Interface Register Map ............................................. 790 2 S) Interface Register Map ................................... 824 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 17 ...

  • Page 18

    ... S Slave Clock (Receive and Transmit) ............................................................ 1256 2 Table 25-35 Master Mode .............................................................................................. 1256 2 Table 25-36 Slave Mode ................................................................................................ 1257 Table 25-37. Analog Comparator Characteristics ................................................................... 1258 Table 25-38. Analog Comparator Voltage Reference Characteristics ...................................... 1258 Table B-1. Part Ordering Information ................................................................................. 1310 18 Source Current Specifications ..................................................... 1237 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 19

    ... Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 143 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 143 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 143 Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 143 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 19 ...

  • Page 20

    ... Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 236 Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 237 Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 239 2 Register 14 MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 240 Register 15: Device Identification 1 (DID1), offset 0x004 ..................................................................... 242 20 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 21

    ... Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 328 Register 22: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 329 Register 23: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 330 Register 24: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 331 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 21 ...

  • Page 22

    ... GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 418 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 419 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 420 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 421 Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 423 22 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 23

    ... EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 510 Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 511 Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 513 Register 29: EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 514 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 23 ...

  • Page 24

    ... Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 590 Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 591 Analog-to-Digital Converter (ADC) ............................................................................................. 592 Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 614 Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 615 24 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 25

    ... ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 670 Register 48: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 670 Register 49: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 670 Register 50: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 670 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 25 ...

  • Page 26

    ... SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 761 Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 762 Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 763 Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 764 Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 765 26 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 27

    ... S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 843 2 Register 16 Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 845 2 Register 17 Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 847 Controller Area Network (CAN) Module ..................................................................................... 848 Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 869 March 19, 2011 2 S) Interface ............................................................................ 812 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 27 ...

  • Page 28

    ... USB General Interrupt Status (USBIS), offset 0x00A ........................................................ 938 Register 8: USB Interrupt Enable (USBIE), offset 0x00B .................................................................... 941 Register 9: USB Frame Value (USBFRAME), offset 0x00C ................................................................ 944 Register 10: USB Endpoint Index (USBEPIDX), offset 0x00E .............................................................. 945 Register 11: USB Test Mode (USBTEST), offset 0x00F ....................................................................... 946 28 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 29

    ... USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A ...................... 960 Register 57: USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 ...................... 960 Register 58: USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA ...................... 960 Register 59: USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 ...................... 960 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 29 ...

  • Page 30

    ... Register 104: USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE ...................... 966 Register 105: USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 ...................... 966 Register 106: USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE ...................... 966 Register 107: USB Receive Hub Address Endpoint 8 (USBRXHUBADDR8), offset 0x0C6 ...................... 966 30 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 31

    ... Register 153: USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 ............... 981 Register 154: USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 ............... 981 Register 155: USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 ............... 981 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 31 ...

  • Page 32

    ... Register 201: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............... 992 Register 202: USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 ............... 992 Register 203: USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 ............... 992 32 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 33

    ... Register 249: USB Host Transmit Configure Type Endpoint 10 (USBTXTYPE10), offset 0x1AA ............. 1004 Register 250: USB Host Transmit Configure Type Endpoint 11 (USBTXTYPE11), offset 0x1BA ............. 1004 Register 251: USB Host Transmit Configure Type Endpoint 12 (USBTXTYPE12), offset 0x1CA ............. 1004 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 33 ...

  • Page 34

    ... Register 297: USB Host Receive Polling Interval Endpoint 13 (USBRXINTERVAL13), offset 0x1DD ...... 1010 Register 298: USB Host Receive Polling Interval Endpoint 14 (USBRXINTERVAL14), offset 0x1ED ...... 1010 Register 299: USB Host Receive Polling Interval Endpoint 15 (USBRXINTERVAL15), offset 0x1FD ....... 1010 34 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 35

    ... Register 330: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ........................................ 1033 Register 331: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C .................... 1034 Register 332: USB DMA Select (USBDMASEL), offset 0x450 .............................................................. 1035 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 35 ...

  • Page 36

    ... PWM3 Load (PWM3LOAD), offset 0x110 ...................................................................... 1104 Register 32: PWM0 Counter (PWM0COUNT), offset 0x054 ............................................................... 1105 Register 33: PWM1 Counter (PWM1COUNT), offset 0x094 ............................................................... 1105 Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4 .............................................................. 1105 Register 35: PWM3 Counter (PWM3COUNT), offset 0x114 ............................................................... 1105 Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1106 36 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 37

    ... Register 81: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ................................................... 1124 Register 82: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ................................................... 1124 Register 83: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ................................................... 1124 Register 84: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 ................................................... 1126 March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 37 ...

  • Page 38

    ... QEI Velocity Counter (QEICOUNT), offset 0x018 ........................................................... 1144 Register 8: QEI Velocity (QEISPEED), offset 0x01C ........................................................................ 1145 Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................. 1146 Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ........................................................... 1148 Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ................................................... 1150 38 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 39

    ... Revision History The revision history table notes changes made between the indicated revisions of the LM3S5791 data sheet. Table 1. Revision History Date Revision Description March 2011 9538 ■ Clarified "Reset Control" section in the "System Control" chapter. ■ Corrected USB PLL speed in "Main Clock Tree" diagram. ...

  • Page 40

    ... Maximum Current Specifications, and Typical Current Consumption vs. Frequency sections. Clarified Reset, and Power and Brown-out Characteristics and added a new specification for powering down before powering back up. Added characteristics required when using an external regulator to provide power for V Texas Instruments-Advance Information . DDC March 19, 2011 ...

  • Page 41

    ... Added "Power-On Reset and Voltage Parameters" timing diagram. Added t parameter to "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" table. ALEADD Added "Host-Bus 8/16 Mode Muxed Read Timing" and "Host-Bus 8/16 Mode Muxed Write Timing" timing diagrams. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 2 C module 2 C slave registers. 41 ...

  • Page 42

    ... Corrected reset timing in Table 25-21 on page 1245. Specified Max value for V in Table 25-29 on page 1253. REFA Corrected values for t (SSIClk rise/fall time) in Table 25-31 on page 1253. CLKRF 2 Added I C Characteristics table (see Table 25-32 on page 1255). Texas Instruments-Advance Information ® names: the Cortex-M3 Interrupt March 19, 2011 ...

  • Page 43

    ... Added three figures to the ADC chapter on sample phase control. ■ Clarified configuration of USB0VBUS and USB0ID in OTG mode. March 19, 2011 In "Reset Characteristics" table, corrected Supply voltage (VDD) rise time. Clarified figure "SDRAM Initialization and Load Mode Register Timing". Added BSEL0n/BSEL1n to EPI timing diagrams. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 43 ...

  • Page 44

    ... In "Flash Memory Characteristics" table, corrected Mass erase time Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time Added table entry for VDD3ON power consumption to Table 25-7 on page 1236. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 45

    ... Changed SSI set up and hold times to be expressed in system clocks, not ns. ■ Updated Electrical Characteristics chapter with latest data. Changes were made to ADC and EPI content. ■ Additional minor data sheet clarifications and corrections. March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ® devices. 45 ...

  • Page 46

    ... Modified Host-Bus 8/16 Mode Write Timing figure. Modified General-Purpose Mode Read and Write Timing figure. Modified values for t and t parameters, and deleted Interface Characteristics figure. Major changes to ADC Characteristics tables, including adding additonal tables and diagram. Texas Instruments-Advance Information parameter from EPI General-Purpose OD March 19, 2011 ...

  • Page 47

    ... Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table. ■ Updated ROM DriverLib appendix with RevC0 functions. ■ Updated part ordering numbers. ■ Additional minor data sheet clarifications and corrections. May 2009 5285 Started tracking revision history. March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 47 ...

  • Page 48

    ... About This Document About This Document This data sheet provides reference information for the LM3S5791 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers ...

  • Page 49

    ... Bit set chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 49 ...

  • Page 50

    ... Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 50 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 51

    ... These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S5791 microcontroller has the following features: ■ ARM Cortex-M3 Processor Core – 80-MHz operation; 100 DMIPS performance – ...

  • Page 52

    ... LQFP and 108-ball BGA package ■ Industrial (-40°C to 85°C) Temperature Range The LM3S5791 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security ...

  • Page 53

    ... Information” on page 1310 for ordering information for Stellaris family devices. 1.1 Functional Overview The following sections provide an overview of the features of the LM3S5791 microcontroller. The page number in parentheses indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 1310. ...

  • Page 54

    ... Memory Map (see page 94) A memory map lists the location of instructions and data in memory. The memory map for the LM3S5791 controller can be found in “Memory Model” on page 94. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. ...

  • Page 55

    ... The following sections describe the on-chip memory modules. 1.1.2.1 SRAM (see page 297) The LM3S5791 microcontroller provides single-cycle on-chip SRAM. The internal SRAM of the Stellaris devices is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor ...

  • Page 56

    ... U.S. Government. AES is a strong encryption method with reasonable performance and size. In addition fast in both hardware and software, is fairly easy to implement, and requires little memory. The Texas Instruments encryption package is available with full source code, and is based on lesser general public license (LGPL) source. An LGPL means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source) ...

  • Page 57

    ... FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls 1.1.4 Serial Communications Peripherals The LM3S5791 controller supports both asynchronous and synchronous serial communications with: ■ Two CAN 2.0 A/B controllers March 19, 2011 Texas Instruments-Advance Information Stellaris® ...

  • Page 58

    ... Universal Serial Bus (USB serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The LM3S5791 microcontroller supports three configurations in USB 2.0 full and low speed: USB Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other USB-enabled systems) ...

  • Page 59

    ... The LM3S5791 microcontroller includes three fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem status, and error conditions ...

  • Page 60

    ... C bus can be designated as either a master or a slave. Each I supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I The LM3S5791 microcontroller includes two I 2 ■ Devices on the I C bus can be designated as either a master or a slave – ...

  • Page 61

    ... SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The LM3S5791 microcontroller includes two SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ ...

  • Page 62

    ... Channel requests asserted when FIFO contains required amount of data 1.1.5 System Integration The LM3S5791 microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ ...

  • Page 63

    ... Direct Memory Access (see page 332) The LM3S5791 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μ ...

  • Page 64

    ... Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during power-saving modes ■ Flexible reset sources – Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) detector alerts to system power drops – Software reset 64 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 65

    ... Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The LM3S5791 microcontroller includes eight Capture Compare PWM pins (CCP) that can be programmed to operate in the following modes: March 19, 2011 Texas Instruments-Advance Information Stellaris® ...

  • Page 66

    ... The LM3S5791 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris Watchdog Timer module has the following features: ■ ...

  • Page 67

    ... High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. The LM3S5791 PWM module consists of four PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector ...

  • Page 68

    ... Synchronization of PWM output enables across the PWM generator blocks ■ Interrupt status summary of the PWM generator blocks ■ Extended fault capabilities with multiple fault signals, programmable polarities, and filtering ■ PWM generators can be operated independently or synchronized with other generators 68 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 69

    ... The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 20 MHz for a 80-MHz system). The LM3S5791 microcontroller includes two QEI modules providing control of two motors at the same time with the following features: ■ Position integrator that tracks the encoder position ■ ...

  • Page 70

    ... Analog Comparators (see page 1037) An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The LM3S5791 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. ...

  • Page 71

    ... Packaging and Temperature ■ Industrial-range 100-pin RoHS-compliant LQFP package ■ Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications The Stellaris family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 71 ...

  • Page 72

    ... High-Level Block Diagram Figure 1-1 on page 73 depicts the features on the Stellaris LM3S5791 microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus ...

  • Page 73

    ... Figure 1-1. Stellaris LM3S5791 Microcontroller High-Level Block Diagram JTAG/SWD System Control and Clocks (w/ Precis. Osc.) LM3S5791 DMA GPIOs (72) USB OTG (FS PHY) SSI (2) I2S Analog Comparators (3) PWM (8) March 19, 2011 ARM® Cortex -M3 ROM (80 MHz) Flash DCode bus (128 KB) NVIC MPU ICode bus ...

  • Page 74

    ... Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 1152 ■ “Signal Tables” on page 1154 ■ “Operating Characteristics” on page 1233 ■ “Electrical Characteristics” on page 1234 ■ “Package Information” on page 1312 74 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 75

    ... The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 75 ...

  • Page 76

    ... ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 76 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 77

    ... Unit Data Watchpoint Flash and Trace Patch and Breakpoint Private Peripheral Bus (internal) Bus Matrix Debug Access Port Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Serial ARM Wire Cortex-M3 Output Trace Port Trace (SWO) Port Interface Unit Instrumentation Trace Macrocell ROM Table Adv ...

  • Page 78

    ... Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 119). ■ System Control Block (SCB) 78 Asynchronous FIFO Texas Instruments-Advance Information Serial Wire Trace Out Trace Port (serializer) (SWO) ...

  • Page 79

    ... The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 79 ...

  • Page 80

    ... R11 R12 ‡ SP (R13) PSP LR (R14) PC (R15) PSR Program status register PRIMASK FAULTMASK Exception mask registers BASEPRI CONTROL CONTROL register Texas Instruments-Advance Information Stack Used a Main stack or process stack Main stack ‡ ‡ MSP Banked version of SP Special registers March 19, 2011 a ...

  • Page 81

    ... Cortex General-Purpose Register 11 - Cortex General-Purpose Register 12 - Stack Pointer 0xFFFF.FFFF Link Register - Program Counter 0x0100.0000 Program Status Register 0x0000.0000 Priority Mask Register 0x0000.0000 Fault Mask Register 0x0000.0000 Base Priority Mask Register 0x0000.0000 Control Register Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller See page ...

  • Page 82

    ... R/W R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31:0 DATA DATA R/W R/W R/W R/W R DATA R/W R/W R/W R/W R Type Reset Description R/W - Register data. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R March 19, 2011 - 0 - ...

  • Page 83

    ... Bit/Field Name 31:0 SP March 19, 2011 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the address of the stack pointer. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 84

    ... R/W Reset Bit/Field Name 31:0 LINK LINK R/W R/W R/W R/W R LINK R/W R/W R/W R/W R Type Reset Description R/W 0xFFFF.FFFF This field is the return address. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R March 19, 2011 ...

  • Page 85

    ... Bit/Field Name 31:0 PC March 19, 2011 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the current program address. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 86

    ... Type R/W, reset 0x0100.0000 Type R/W R/W R/W R/W R/W Reset ICI / IT Type Reset Type Combination R/W APSR, EPSR, and IPSR RO EPSR and IPSR a R/W APSR and IPSR b R/W APSR and EPSR ICI / IT THUMB reserved Texas Instruments-Advance Information reserved ISRNUM March 19, 2011 ...

  • Page 87

    ... DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 87 ...

  • Page 88

    ... The value of this field is only meaningful when accessing PSR or EPSR. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 89

    ... PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x46 Interrupt Vector 54 0x47-0x7F Reserved See “Exception Types” on page 104 for more information. The value of this field is only meaningful when accessing PSR or IPSR. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 89 ...

  • Page 90

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority effect. Texas Instruments-Advance Information ...

  • Page 91

    ... R/W 0 Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 92

    ... All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 93

    ... In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 94

    ... The processor has a fixed memory map that provides addressable memory. The memory map for the LM3S5791 controller is provided in Table 2-4 on page 94. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. ...

  • Page 95

    ... Analog Comparators GPIO Port J Reserved CAN0 Controller CAN1 Controller Reserved USB Reserved Reserved GPIO Port A (AHB aperture) GPIO Port B (AHB aperture) Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller For details, see page ... 404 747 747 - 684 684 684 - 791 791 - 404 ...

  • Page 96

    ... Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) Reserved Trace Port Interface Unit (TPIU) Reserved Texas Instruments-Advance Information For details, see page ... 404 404 404 404 404 ...

  • Page 97

    ... Ordered Reserved - - Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Description This executable region is for program code. Data can also be stored here. This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 99) ...

  • Page 98

    ... Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching 98 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 99

    ... Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 99 ...

  • Page 100

    ... The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) 100 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 101

    ... Figure 2-5 on page 102 illustrates how data is stored. March 19, 2011 32-MB Alias Region 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 1-MB SRAM Bit-Band Region 0x200F.FFFE 0x200F.FFFD 0x2000.0002 0x2000.0001 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 0x23FF.FFE4 0x23FF.FFE0 0x2200.0004 0x2200.0000 0x200F.FFFC 0x2000.0000 101 ...

  • Page 102

    ... The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 102 Register Texas Instruments-Advance Information March 19, 2011 ...

  • Page 103

    ... See “Nested Vectored Interrupt Controller (NVIC)” on page 119 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 103 ...

  • Page 104

    ... Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return 104 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 105

    ... NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 106 lists the interrupts on the LM3S5791 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler ...

  • Page 106

    ... Texas Instruments-Advance Information Activation b Offset Asynchronous Asynchronous Description Processor exceptions GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 PWM Fault PWM Generator 0 PWM Generator 1 PWM Generator 2 ...

  • Page 107

    ... Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Description GPIO Port F GPIO Port G GPIO Port H UART2 SSI1 Timer 3A Timer QEI1 CAN0 CAN1 Reserved USB PWM Generator 3 µDMA Software µDMA Error ADC1 Sequence 0 ...

  • Page 108

    ... IRQ1 0x0044 IRQ0 0x0040 Systick 0x003C PendSV 0x0038 Reserved Reserved for Debug SVCall 0x002C Reserved Usage fault 0x0018 Bus fault 0x0014 Memory management fault 0x0010 Hard fault 0x000C NMI 0x0008 Reset 0x0004 Initial SP value 0x0000 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 109

    ... Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 109 ...

  • Page 110

    ... Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC 110 Pre-IRQ top of stack IRQ top of stack Texas Instruments-Advance Information March 19, 2011 ...

  • Page 111

    ... Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. Reserved Handler Fault Status Register Hard fault Hard Fault Status (HFAULTSTAT) Hard fault Hard Fault Status (HFAULTSTAT) Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Bit Name VECT FORCED 111 ...

  • Page 112

    ... Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Texas Instruments-Advance Information Bit Name a IERR DERR MSTKE MUSTKE BSTKE BUSTKE IBUS ...

  • Page 113

    ... A program might have an idle loop to put the processor back to sleep mode. March 19, 2011 Address Register Name - Memory Management Fault Address (MMADDR) Bus Fault Address (FAULTADDR) - Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Register Description page 172 page 166 page 173 page 166 page 174 page 166 113 ...

  • Page 114

    ... For more information about SYSCTRL, see page 155. 2.8 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 115 lists the supported instructions. Note: In Table 2-13 on page 115: ■ Angle brackets, <>, enclose alternative forms of the operand 114 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 115

    ... Rn{!}, reglist before Load multiple registers, increment after Rn{!}, reglist Load register with word Rt, [Rn, #offset] Load register with byte Rt, [Rn, #offset] Load register with two bytes Rt, Rt2, [Rn, #offset] Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Flags N,Z,C,V N,Z,C,V N,Z,C,V - N,Z,C N,Z N,Z,C ...

  • Page 116

    ... Rd, Rn, #lsb, #width Signed divide {Rd,} Rn Send event Signed multiply with accumulate RdLo, RdHi, Rn, Rm (32x32+64), 64-bit result Signed multiply (32x32), 64-bit result RdLo, RdHi, Rn, Rm Signed saturate Rd, #n, Rm {,shift #s} Store multiple registers, increment after Rn{!}, reglist Texas Instruments-Advance Information Flags - - - - - - - N,Z,C N,Z N,Z,C ...

  • Page 117

    ... Rd, #n, Rm {,shift #s} Zero extend a Byte {Rd,} Rm, {,ROR #n} Zero extend a Halfword {Rd,} Rm, {,ROR #n} Unsigned saturate Rd, #n, Rm {,shift #s} Zero extend a byte {Rd,} Rm {,ROR #n} Zero extend a halfword {Rd,} Rm {,ROR #n} - Wait for event - Wait for interrupt Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Flags - - - - - - - - - - - - N,Z,C,V N,Z,C,V ...

  • Page 118

    ... A high-speed alarm timer using the system clock. 118 ® implementation of the Cortex-M3 processor Core Peripheral System Timer Nested Vectored Interrupt Controller System Control Block Memory Protection Unit Texas Instruments-Advance Information Description (see page ...) 118 119 121 121 March 19, 2011 ...

  • Page 119

    ... Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 119 ...

  • Page 120

    ... ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 120 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 121

    ... Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. March 19, 2011 Description All accesses to Strongly Ordered memory occur in program order. Memory-mapped peripherals Normal memory Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 121 ...

  • Page 122

    ... MPU region number register ; Region Number ; Region Base Address ; Region Size and Enable ; Region Attribute ; 0xE000ED98, MPU region number register ; Region Number ; Disable ; Region Size and Enable ; Region Base Address ; Region Attribute ; Enable ; Region Size and Enable Texas Instruments-Advance Information March 19, 2011 ...

  • Page 123

    ... Region base address and region number combined ; with VALID (bit 4) set ; Region Attribute, Size and Enable ; 0xE000ED9C, MPU Region Base register ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 123 ...

  • Page 124

    ... Device 0 Normal 0 Normal 1 Normal 1 Normal 0 Normal 0 Normal 1 Reserved encoding 0 Reserved encoding 1 Normal 1 Normal Texas Instruments-Advance Information Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB 64KB 0 Shareability Other Attributes Shareable - Shareable - Not shareable Outer and inner Shareable write-through. No write Not shareable allocate ...

  • Page 125

    ... Read-only, by privileged or unprivileged software. RO Read-only, by privileged or unprivileged software. TEX 000b 000b Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Shareability Other Attributes Not shareable Nonshared Device Not shareable Cached memory (BB = outer policy inner Shareable policy). See Table 3-4 for the encoding of the AA and BB bits ...

  • Page 126

    ... Interrupt 0-31 Clear Pending 0x0000.0000 Interrupt 32-54 Clear Pending 0x0000.0000 Interrupt 0-31 Active Bit 0x0000.0000 Interrupt 32-54 Active Bit 0x0000.0000 Interrupt 0-3 Priority Texas Instruments-Advance Information Memory Type and Attributes Normal memory, shareable, write-back, write-allocate Device memory, shareable See page 129 131 ...

  • Page 127

    ... System Handler Control and State 0x0000.0000 Configurable Fault Status 0x0000.0000 Hard Fault Status - Memory Management Fault Address - Bus Fault Address 0x0000.0800 MPU Type Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller See page 143 143 143 143 143 143 143 143 143 ...

  • Page 128

    ... MPU Region Attribute and Size Alias 1 0x0000.0000 MPU Region Base Address Alias 2 0x0000.0000 MPU Region Attribute and Size Alias 2 0x0000.0000 MPU Region Base Address Alias 3 0x0000.0000 MPU Region Attribute and Size Alias 3 Texas Instruments-Advance Information See page 176 178 179 181 179 181 ...

  • Page 129

    ... R/W 1 Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller COUNT ...

  • Page 130

    ... Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 131

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller RELOAD R/W ...

  • Page 132

    ... This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. Texas Instruments-Advance Information ...

  • Page 133

    ... Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller R/W R/W R/W R/W ...

  • Page 134

    ... Interrupt Enable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. Texas Instruments-Advance Information INT R/W R/W R/W R/W ...

  • Page 135

    ... Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller R/W R/W R/W R/W R/W R/W ...

  • Page 136

    ... R/W 0x00.0000 Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. Texas Instruments-Advance Information INT R/W R/W R/W R/W R/W ...

  • Page 137

    ... On a read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller R/W ...

  • Page 138

    ... On a write, no effect read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. Texas Instruments-Advance Information INT R/W ...

  • Page 139

    ... On a write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller R/W ...

  • Page 140

    ... On a read, indicates that the interrupt is not pending write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Advance Information INT ...

  • Page 141

    ... Type Reset Type Reset Bit/Field Name 31:0 INT March 19, 2011 INT INT Type Reset Description RO 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 141 ...

  • Page 142

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0x00.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Advance Information INT ...

  • Page 143

    ... Application Interrupt and Reset Control (APINT) register (see page 153) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. March 19, 2011 Interrupt Interrupt [4n+3] Interrupt [4n+2] Interrupt [4n+1] Interrupt [4n] Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 143 ...

  • Page 144

    ... PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 145

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WO 0x00 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 146

    ... Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M3 processor. Texas Instruments-Advance Information ...

  • Page 147

    ... Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 147 ...

  • Page 148

    ... RO 0xF Constant Value Description 0xF Always reads as 0xF. RO 0xC23 Part Number Value Description 0xC23 Cortex-M3 processor. RO 0x0 Revision Number Value Description 0x0 The pn value in the rnpn product revision identifier, for example, the 0 in r2p0. Texas Instruments-Advance Information CON ...

  • Page 149

    ... On a write, no effect read, indicates a PendSV exception is pending write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing the UNPENDSV bit. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 150

    ... This bit provides status for all interrupts excluding NMI and Faults. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 151

    ... Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 86). Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 151 ...

  • Page 152

    ... Because there are 54 interrupts, the minimum alignment is 128 words. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 153

    ... The Stellaris implementation uses only little-endian mode so this is cleared 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Group Subpriorities Priorities ...

  • Page 154

    ... Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable System Reset This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 155

    ... R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 156

    ... Setting this bit enables an interrupt-driven application to avoid returning to an empty main application Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 157

    ... The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 158

    ... Value Description 0 The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 110 for more information). Texas Instruments-Advance Information March 19, 2011 ...

  • Page 159

    ... Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller reserved ...

  • Page 160

    ... This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 161

    ... RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 162

    ... R/W 0 Usage Fault Enable Value Description 0 Disables the usage fault exception. 1 Enables the usage fault exception. R/W 0 Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. Texas Instruments-Advance Information USAGE BUS R/W R ...

  • Page 163

    ... SysTick Exception Active Value Description 0 A SysTick exception is not active SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 163 ...

  • Page 164

    ... R/W 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 165

    ... Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 165 ...

  • Page 166

    ... R/W1C R/W1C Type Reset Description RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information NOCP INVPC INVSTAT UNDEF RO RO R/W1C R/W1C R/W1C ...

  • Page 167

    ... result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing it. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 167 ...

  • Page 168

    ... Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 169

    ... The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 169 ...

  • Page 170

    ... MMADDR register. This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 171

    ... When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 171 ...

  • Page 172

    ... When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 173

    ... R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller R/W R/W R/W R/W R/W R ...

  • Page 174

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W ...

  • Page 175

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation Separate or Unified MPU Value Description 0 Indicates the MPU is unified. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller IREGION ...

  • Page 176

    ... reserved Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information PRIVDEFEN HFNMIENA ENABLE R/W R/W R March 19, 2011 ...

  • Page 177

    ... When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 177 ...

  • Page 178

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0x0 MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. Texas Instruments-Advance Information ...

  • Page 179

    ... The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller ...

  • Page 180

    ... R/W 0x0 Region Number On a write, contains the value to be written to the MPUNUMBER register read, returns the current region number in the MPUNUMBER register. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 181

    ... No valid ADDR field in MPUBASE; the region occupies the complete memory map reserved R/W R/W R reserved R/W R/W R Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Note Minimum permitted size - - - Maximum possible size TEX S C R/W R/W R/W R/W R/W R SIZE ENABLE R/W R/W R/W ...

  • Page 182

    ... R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 181 for more information. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 183

    ... Bit/Field Name 0 ENABLE March 19, 2011 Type Reset Description R/W 0 Region Enable Value Description 0 The region is disabled. 1 The region is enabled. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 183 ...

  • Page 184

    ... Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 184 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 185

    ... TTL JTAG TMS and SWDIO. PC3 (3) O TTL JTAG TDO and SWO. PC0 (3) I TTL JTAG/SWD CLK. PC2 (3) I TTL JTAG TDI. PC3 (3) O TTL JTAG TDO and SWO. Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller TDO Cortex-M3 Debug Port 185 ...

  • Page 186

    ... TTL JTAG TMS and SWDIO. PC3 (3) O TTL JTAG TDO and SWO. PC0 (3) I TTL JTAG/SWD CLK. PC2 (3) I TTL JTAG TDI. PC3 (3) O TTL JTAG TDO and SWO. PC1 (3) I TTL JTAG TMS and SWDIO. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 187

    ... The value of TDO depends on the current TAP state, the current instruction, and the data in the March 19, 2011 Internal Pull-Up Internal Pull-Down Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Enabled Disabled Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller Drive Strength Drive Value N/A N/A N/A N/A N/A N/A 2-mA driver High-Z 187 ...

  • Page 188

    ... The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows 188 Select DR Scan 1 0 Capture Shift Exit Pause Exit Update Texas Instruments-Advance Information Select IR Scan 1 0 Capture IR 0 Shift Exit Pause Exit Update March 19, 2011 ...

  • Page 189

    ... Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 189 ...

  • Page 190

    ... Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. 190 Texas Instruments-Advance Information March 19, 2011 ...

  • Page 191

    ... JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings. March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 191 ...

  • Page 192

    ... IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. BYPASS Connects TDI to TDO through a single Shift Register chain. Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 193

    ... IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 194 for more information. March 19, 2011 Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller 193 ...

  • Page 194

    ... The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each 194 12 11 Part Number Texas Instruments-Advance Information 1 0 TDO Manufacturer ID 1 March 19, 2011 ...

  • Page 195

    ... The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. March 19, 2011 ... GPIO (m+1) GPIO Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller O TDO ... GPIO n 195 ...

  • Page 196

    ... Buffer Type Description PB7 (4) I TTL Non-maskable interrupt. fixed I Analog Main oscillator crystal input or an external clock reference input. fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. fixed I TTL System reset input. Texas Instruments-Advance Information March 19, 2011 ...

  • Page 197

    ... This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 Reset Sources The LM3S5791 microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 198). 2. External reset input pin (RST) assertion (see page 198). 3. Internal brown-out (BOR) detector (see page 200). ...

  • Page 198

    ... Figure 25-4 on page 1242. 5.2.2.3 External RST Pin Note recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. 198 Texas Instruments-Advance Information ) and generates DD March 19, 2011 ...

  • Page 199

    ... VDD Stellaris® RST kΩ to 100 kΩ µ the application requires the use of an external reset switch, Figure 5-3 on page 200 shows the proper circuitry to use. March 19, 2011 VDD Texas Instruments-Advance Information Stellaris® LM3S5791 Microcontroller and then de-asserted MIN 199 ...

  • Page 200

    ... The internal Brown-Out Reset timing is shown in Figure 25-5 on page 1242. 200 VDD brown-out condition is detected, the system BTH , an internal BOR condition is set. BTH level is restored. The RESC register can be examined DD Texas Instruments-Advance Information ) DD March 19, 2011 ...