LM3S5651-IBZ80-C1T

Manufacturer Part NumberLM3S5651-IBZ80-C1T
DescriptionIC ARM CORTEX MCU 128KB 108NFBGA
ManufacturerTexas Instruments
SeriesStellaris® 5000
LM3S5651-IBZ80-C1T datasheet
 


Specifications of LM3S5651-IBZ80-C1T

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed80MHzConnectivityCAN, I²C, IrDA, LIN, Microwire, QEI, SPI, SSI, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, DMA, I²S, POR, PWM, WDTNumber Of I /o67
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size32K x 8Voltage - Supply (vcc/vdd)1.08 V ~ 1.32 V
Data ConvertersA/D 16x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case108-NFBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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T E X AS I NS TR UM E NTS - ADVANCE I NFO R MAT I O N
Stellaris® LM3S5651 Microcontroller
D ATA S H E E T
D S -L M3 S5 65 1- 95 38
Co pyri gh t © 20 07 -2 011
Texa s Instrument s I nco rp orat ed

LM3S5651-IBZ80-C1T Summary of contents

  • Page 1

    ... Stellaris® LM3S5651 Microcontroller NTS - ADVANCE I NFO R MAT ATA pyri gh t © 011 Texa s Instrument s I nco rp orat ed ...

  • Page 2

    ... ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ...

  • Page 3

    ... Memory System Ordering of Memory Accesses .............................................................. 92 2.4.3 Behavior of Memory Accesses ....................................................................................... 92 2.4.4 Software Ordering of Memory Accesses ......................................................................... 92 2.4.5 Bit-Banding ................................................................................................................... 94 2.4.6 Data Storage ................................................................................................................ 96 2.4.7 Synchronization Primitives ............................................................................................. 97 2.5 Exception Model ........................................................................................................... 98 2.5.1 Exception States ........................................................................................................... 98 2.5.2 Exception Types ............................................................................................................ 99 2.5.3 Exception Handlers ..................................................................................................... 102 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 3 ...

  • Page 4

    ... Device Identification .................................................................................................... 192 5.2.2 Reset Control .............................................................................................................. 192 5.2.3 Non-Maskable Interrupt ............................................................................................... 197 5.2.4 Power Control ............................................................................................................. 197 5.2.5 Clock Control .............................................................................................................. 198 5.2.6 System Control ........................................................................................................... 206 5.3 Initialization and Configuration ..................................................................................... 207 5.4 Register Map .............................................................................................................. 208 5.5 Register Descriptions .................................................................................................. 209 4 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 5

    ... Peripheral Interface ..................................................................................................... 371 8.2.9 Software Request ........................................................................................................ 371 8.2.10 Interrupts and Errors .................................................................................................... 372 8.3 Initialization and Configuration ..................................................................................... 372 8.3.1 Module Initialization ..................................................................................................... 372 8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 372 8.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 374 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 5 ...

  • Page 6

    ... Register Map .............................................................................................................. 519 11.5 Register Descriptions .................................................................................................. 520 12 Analog-to-Digital Converter (ADC) ..................................................................... 542 12.1 Block Diagram ............................................................................................................ 543 12.2 Signal Description ....................................................................................................... 544 12.3 Functional Description ................................................................................................. 546 12.3.1 Sample Sequencers .................................................................................................... 546 12.3.2 Module Control ............................................................................................................ 547 12.3.3 Hardware Sample Averaging Circuit ............................................................................. 549 6 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 7

    ... Signal Description ....................................................................................................... 726 15.3 Functional Description ................................................................................................. 727 2 15.3 Bus Functional Overview ........................................................................................ 727 15.3.2 Available Speed Modes ............................................................................................... 729 15.3.3 Interrupts .................................................................................................................... 730 15.3.4 Loopback Operation .................................................................................................... 731 15.3.5 Command Sequence Flow Charts ................................................................................ 732 March 20, 2011 2 C) Interface ................................................................ 725 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 7 ...

  • Page 8

    ... Operation as a Host .................................................................................................... 856 18.3.3 OTG Mode .................................................................................................................. 860 18.3.4 DMA Operation ........................................................................................................... 862 18.4 Initialization and Configuration ..................................................................................... 863 18.4.1 Pin Configuration ......................................................................................................... 863 18.4.2 Endpoint Configuration ................................................................................................ 863 18.5 Register Map .............................................................................................................. 864 Master) ............................................................................... 741 2 C Slave) ................................................................................. 753 2 S) Interface .................................................... 762 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 9

    ... On-Chip Low Drop-Out (LDO) Regulator Characteristics .............................................. 1170 25.1.4 Hibernation Module Characteristics ............................................................................ 1170 25.1.5 Flash Memory Characteristics .................................................................................... 1170 25.1.6 GPIO Module Characteristics ..................................................................................... 1171 25.1.7 USB Module Characteristics ....................................................................................... 1171 25.1.8 Current Specifications ................................................................................................ 1171 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 9 ...

  • Page 10

    ... Package Dimensions ................................................................................................. 1243 C.1.2 Tray Dimensions ....................................................................................................... 1245 C.1.3 Tape and Reel Dimensions ........................................................................................ 1245 C.2 108-Ball BGA Package .............................................................................................. 1247 C.2.1 Package Dimensions ................................................................................................. 1247 C.2.2 Tray Dimensions ....................................................................................................... 1249 C.2.3 Tape and Reel Dimensions ........................................................................................ 1250 Interface ......................................................................... 1188 2 S) Interface ............................................................... 1189 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 11

    ... List of Figures Figure 1-1. Stellaris LM3S5651 Microcontroller High-Level Block Diagram .............................. 68 Figure 2-1. CPU Block Diagram ............................................................................................. 72 Figure 2-2. TPIU Block Diagram ............................................................................................ 73 Figure 2-3. Cortex-M3 Register Set ........................................................................................ 75 Figure 2-4. Bit-Band Mapping ................................................................................................ 96 Figure 2-5. Data Storage ....................................................................................................... 97 Figure 2-6. Vector table ....................................................................................................... 103 Figure 2-7. Exception Stack Frame ...................................................................................... 105 Figure 3-1 ...

  • Page 12

    ... Right-Justified Data Transfer .............................................................................. 766 Figure 17-1. CAN Controller Block Diagram ............................................................................ 799 Figure 17-2. CAN Data/Remote Frame .................................................................................. 801 Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 809 12 = 1.5 V ...................................................... 553 IN_ODD = 0.75 V .................................................... 554 IN_ODD = 2.25 V .................................................... 554 IN_ODD 2 C Bus ................................................... 729 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 13

    ... LQFP Tape and Reel Dimensions ......................................................... 1246 Figure C-4. 108-Ball BGA Package Dimensions .................................................................. 1247 Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1249 Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1250 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Source ............................. 1180 DDC 13 ...

  • Page 14

    ... Hibernation Module Register Map ....................................................................... 303 Table 7-1. Flash Memory Protection Policy Combinations .................................................... 325 Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 328 Table 7-3. Flash Register Map ............................................................................................ 329 Table 8-1. μDMA Channel Assignments .............................................................................. 359 Table 8-2. Request Type Support ....................................................................................... 361 14 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 15

    ... Signals for I2C (108BGA) ................................................................................... 726 Table 15-3. Examples of I Table 15-4. Inter-Integrated Circuit (I Table 15-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 745 March 20, 2011 2 C Master Timer Period versus Speed Mode ................................... 730 2 C) Interface Register Map ............................................. 740 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 15 ...

  • Page 16

    ... Table 23-12. Connections for Unused Signals (100-pin LQFP) ............................................... 1166 Table 23-13. Connections for Unused Signals, 108-pin BGA .................................................. 1167 Table 24-1. Temperature Characteristics ............................................................................. 1168 Table 24-2. Thermal Characteristics ................................................................................... 1168 Table 24-3. ESD Absolute Maximum Ratings ...................................................................... 1168 Interface Register Map ................................... 774 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 17

    ... S Master Mode .............................................................................................. 1189 2 Table 25-37 Slave Mode ................................................................................................ 1190 Table 25-38. Analog Comparator Characteristics ................................................................... 1191 Table 25-39. Analog Comparator Voltage Reference Characteristics ...................................... 1191 Table B-1. Part Ordering Information ................................................................................. 1241 March 20, 2011 Source Current Specifications ..................................................... 1173 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 17 ...

  • Page 18

    ... Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 138 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 138 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 138 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 138 Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 138 18 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 19

    ... Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 233 Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 235 Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 237 2 Register 15 MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 238 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 19 ...

  • Page 20

    ... Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 338 Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 339 Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 340 Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 341 Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 342 20 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 21

    ... DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 414 General-Purpose Input/Outputs (GPIOs) ................................................................................... 415 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 429 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 430 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 431 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 21 ...

  • Page 22

    ... GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 508 Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 509 Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 510 Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 511 Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 512 22 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 23

    ... ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 595 Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 596 Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 596 Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 596 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 23 ...

  • Page 24

    ... UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 658 Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 661 Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 664 Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 666 Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 667 24 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 25

    ... C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 750 2 Register Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 751 2 Register Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 752 2 Register Master Configuration (I2CMCR), offset 0x020 ............................................................ 753 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 25 ...

  • Page 26

    ... Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 838 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 838 Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 840 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 840 Interface ............................................................................ 762 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 27

    ... USB Device Control (USBDEVCTL), offset 0x060 ............................................................ 900 Register 29: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 ................................. 902 Register 30: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 .................................. 902 Register 31: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................. 903 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 27 ...

  • Page 28

    ... USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB ............................ 912 Register 77: USB Transmit Hub Port Endpoint 8 (USBTXHUBPORT8), offset 0x0C3 ............................ 912 Register 78: USB Transmit Hub Port Endpoint 9 (USBTXHUBPORT9), offset 0x0CB ............................ 912 Register 79: USB Transmit Hub Port Endpoint 10 (USBTXHUBPORT10), offset 0x0D3 ........................ 912 28 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 29

    ... Register 125: USB Receive Hub Port Endpoint 11 (USBRXHUBPORT11), offset 0x0DF ......................... 918 Register 126: USB Receive Hub Port Endpoint 12 (USBRXHUBPORT12), offset 0x0E7 ......................... 918 Register 127: USB Receive Hub Port Endpoint 13 (USBRXHUBPORT13), offset 0x0EF ......................... 918 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 29 ...

  • Page 30

    ... Register 173: USB Transmit Control and Status Endpoint 9 High (USBTXCSRH9), offset 0x193 ............. 936 Register 174: USB Transmit Control and Status Endpoint 10 High (USBTXCSRH10), offset 0x1A3 ......... 936 Register 175: USB Transmit Control and Status Endpoint 11 High (USBTXCSRH11), offset 0x1B3 .......... 936 30 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 31

    ... Register 221: USB Receive Control and Status Endpoint 12 High (USBRXCSRH12), offset 0x1C7 ......... 947 Register 222: USB Receive Control and Status Endpoint 13 High (USBRXCSRH13), offset 0x1D7 ......... 947 Register 223: USB Receive Control and Status Endpoint 14 High (USBRXCSRH14), offset 0x1E7 .......... 947 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 31 ...

  • Page 32

    ... Register 268: USB Host Transmit Interval Endpoint 14 (USBTXINTERVAL14), offset 0x1EB ................... 956 Register 269: USB Host Transmit Interval Endpoint 15 (USBTXINTERVAL15), offset 0x1FB ................... 956 Register 270: USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................... 958 Register 271: USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................... 958 32 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 33

    ... Register 307: USB Request Packet Count in Block Transfer Endpoint 8 (USBRQPKTCOUNT8), offset 0x320 ........................................................................................................................... 962 Register 308: USB Request Packet Count in Block Transfer Endpoint 9 (USBRQPKTCOUNT9), offset 0x324 ........................................................................................................................... 962 Register 309: USB Request Packet Count in Block Transfer Endpoint 10 (USBRQPKTCOUNT10), offset 0x328 ........................................................................................................................... 962 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 33 ...

  • Page 34

    ... PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 1023 Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ...................................................... 1025 Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C .............................................. 1027 Register 9: PWM Status (PWMSTATUS), offset 0x020 .................................................................... 1029 Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ........................................... 1031 34 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 35

    ... PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1063 Register 56: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1063 Register 57: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1066 Register 58: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1066 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 35 ...

  • Page 36

    ... QEI Velocity Counter (QEICOUNT), offset 0x018 ........................................................... 1088 Register 8: QEI Velocity (QEISPEED), offset 0x01C ........................................................................ 1089 Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................. 1090 Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ........................................................... 1092 Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ................................................... 1094 36 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 37

    ... Revision History The revision history table notes changes made between the indicated revisions of the LM3S5651 data sheet. Table 1. Revision History Date Revision Description March 2011 9538 ■ Clarified "Reset Control" section in the "System Control" chapter. ■ Corrected USB PLL speed in "Main Clock Tree" diagram. ...

  • Page 38

    ... Characteristics" table. VDD2_3 Added "Power-On Reset and Voltage Parameters" timing diagram. Added t su"pply voltage parameter to "Hibernation Module AC Characteristics" table. VDDRISE_HIB Added "VDD Ramp when Waking from Hibernation" timing diagram. Texas Instruments-Advance Information 2 C module 2 C slave registers. March 20, 2011 ...

  • Page 39

    ... Table 25-30 on page 1186. REFA Corrected values for t (SSIClk rise/fall time) in Table 25-32 on page 1186. CLKRF 2 Added I C Characteristics table (see Table 25-33 on page 1188). Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ® names: the Cortex-M3 Interrupt in Table 25-8 on page 1171. HIB_RTC 39 ...

  • Page 40

    ... Added three figures to the ADC chapter on sample phase control. ■ Clarified configuration of USB0VBUS and USB0ID in OTG mode "Reset Characteristics" table, corrected Supply voltage (VDD) rise time. Clarified figure "SDRAM Initialization and Load Mode Register Timing". Texas Instruments-Advance Information March 20, 2011 ...

  • Page 41

    ... In "Flash Memory Characteristics" table, corrected Mass erase time Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time Added table entry for VDD3ON power consumption to Table 25-8 on page 1171. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 41 ...

  • Page 42

    ... Changed SSI set up and hold times to be expressed in system clocks, not ns. ■ Updated Electrical Characteristics chapter with latest data. Changes were made to Hibernation, ADC and EPI content. ■ Additional minor data sheet clarifications and corrections. 42 Texas Instruments-Advance Information ® devices. March 20, 2011 ...

  • Page 43

    ... SDRAM Read Timing and SDRAM Write Timing figures. Modified Host-Bus 8/16 Mode Write Timing figure. Modified General-Purpose Mode Read and Write Timing figure. Major changes to ADC Characteristics tables, including adding additonal tables and diagram. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 43 ...

  • Page 44

    ... About This Document About This Document This data sheet provides reference information for the LM3S5651 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers ...

  • Page 45

    ... Bit set chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 45 ...

  • Page 46

    ... Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 46 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 47

    ... These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S5651 microcontroller has the following features: ■ ARM Cortex-M3 Processor Core – 80-MHz operation; 100 DMIPS performance – ...

  • Page 48

    ... HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S5651 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S5651 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time 48 ...

  • Page 49

    ... Information” on page 1241 for ordering information for Stellaris family devices. 1.1 Functional Overview The following sections provide an overview of the features of the LM3S5651 microcontroller. The page number in parentheses indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 1241. ...

  • Page 50

    ... Memory Map (see page 89) A memory map lists the location of instructions and data in memory. The memory map for the LM3S5651 controller can be found in “Memory Model” on page 89. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. ...

  • Page 51

    ... The following sections describe the on-chip memory modules. 1.1.2.1 SRAM (see page 322) The LM3S5651 microcontroller provides single-cycle on-chip SRAM. The internal SRAM of the Stellaris devices is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor ...

  • Page 52

    ... A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more readily. 1.1.3 Serial Communications Peripherals The LM3S5651 controller supports both asynchronous and synchronous serial communications with: ■ Two CAN 2.0 A/B controllers ■ USB 2.0 OTG/Host/Device ■ Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls) 2 ■ ...

  • Page 53

    ... Universal Serial Bus (USB serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The LM3S5651 microcontroller supports three configurations in USB 2.0 full and low speed: USB Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other USB-enabled systems) ...

  • Page 54

    ... The LM3S5651 microcontroller includes three fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem status, and error conditions ...

  • Page 55

    ... C bus can be designated as either a master or a slave. Each I supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I The LM3S5651 microcontroller includes two I 2 ■ Devices on the I C bus can be designated as either a master or a slave – ...

  • Page 56

    ... SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The LM3S5651 microcontroller includes two SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ ...

  • Page 57

    ... Channel requests asserted when FIFO contains required amount of data 1.1.4 System Integration The LM3S5651 microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ ...

  • Page 58

    ... Direct Memory Access (see page 357) The LM3S5651 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μ ...

  • Page 59

    ... Flexible reset sources – Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 59 ...

  • Page 60

    ... CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The LM3S5651 microcontroller includes eight Capture Compare PWM pins (CCP) that can be programmed to operate in the following modes: ■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. ...

  • Page 61

    ... The LM3S5651 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris Watchdog Timer module has the following features: ■ ...

  • Page 62

    ... Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 62 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 63

    ... High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. The LM3S5651 PWM module consists of three PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector ...

  • Page 64

    ... The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 20 MHz for a 80-MHz system). The LM3S5651 microcontroller includes two QEI modules providing control of two motors at the same time with the following features: ■ Position integrator that tracks the encoder position ■ ...

  • Page 65

    ... Analog The LM3S5651 microcontroller provides analog functions integrated into the device, including: ■ Two 10-bit Analog-to-Digital Converters (ADC) with 16 analog input channels and a sample rate of one million samples/second ■ Two analog comparators ■ 16 digital comparators ■ On-chip voltage regulator The following provides more detail on these analog functions. ...

  • Page 66

    ... Analog Comparators (see page 987) An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The LM3S5651 microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. ...

  • Page 67

    ... High-Level Block Diagram Figure 1-1 on page 68 depicts the features on the Stellaris LM3S5651 microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus ...

  • Page 68

    ... Architectural Overview Figure 1-1. Stellaris LM3S5651 Microcontroller High-Level Block Diagram JTAG/SWD System Control and Clocks (w/ Precis. Osc.) LM3S5651 DMA General- Purpose Timers (4) USB OTG (FS PHY) SSI (2) I2S Analog Comparators (2) PWM (6) 68 ARM® Cortex -M3 ROM (80 MHz) Flash DCode bus (128 KB) ...

  • Page 69

    ... Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 1096 ■ “Signal Tables” on page 1098 ■ “Operating Characteristics” on page 1168 ■ “Electrical Characteristics” on page 1169 ■ “Package Information” on page 1243 March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 69 ...

  • Page 70

    ... DMIPS/MHz ® The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. 70 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 71

    ... ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 71 ...

  • Page 72

    ... Data Memory Protection Unit Data Watchpoint Flash and Trace Patch and Breakpoint Private Peripheral Bus (internal) Bus Matrix Debug Access Port Texas Instruments-Advance Information Serial ARM Wire Cortex-M3 Output Trace Port Trace (SWO) Port Interface Unit Instrumentation Trace Macrocell ROM Table Adv ...

  • Page 73

    ... An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 114). ■ System Control Block (SCB) March 20, 2011 Asynchronous FIFO Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Serial Wire Trace Out Trace Port (serializer) (SWO) ...

  • Page 74

    ... The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements 74 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 75

    ... SP (R13) PSP LR (R14) PC (R15) PSR Program status register PRIMASK FAULTMASK Exception mask registers BASEPRI CONTROL CONTROL register Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Stack Used a Main stack or process stack Main stack ‡ ‡ MSP Banked version of SP Special registers a 75 ...

  • Page 76

    ... Cortex General-Purpose Register 10 - Cortex General-Purpose Register 11 - Cortex General-Purpose Register 12 - Stack Pointer 0xFFFF.FFFF Link Register - Program Counter 0x0100.0000 Program Status Register 0x0000.0000 Priority Mask Register 0x0000.0000 Fault Mask Register 0x0000.0000 Base Priority Mask Register 0x0000.0000 Control Register Texas Instruments-Advance Information See page ...

  • Page 77

    ... Bit/Field Name 31:0 DATA March 20, 2011 DATA R/W R/W R/W R/W R DATA R/W R/W R/W R/W R Type Reset Description R/W - Register data. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 78

    ... R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the address of the stack pointer. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R March 20, 2011 - 0 - ...

  • Page 79

    ... LINK March 20, 2011 LINK R/W R/W R/W R/W R LINK R/W R/W R/W R/W R Type Reset Description R/W 0xFFFF.FFFF This field is the return address. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 80

    ... R/W R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the current program address. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R March 20, 2011 - 0 - ...

  • Page 81

    ... R/W R/W R/W R/W R/W Reset ICI / IT Type Reset March 20, 2011 Type Combination R/W APSR, EPSR, and IPSR RO EPSR and IPSR a R/W APSR and IPSR b R/W APSR and EPSR ICI / IT THUMB reserved Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller reserved ISRNUM ...

  • Page 82

    ... DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 83

    ... The value of this field is only meaningful when accessing PSR or EPSR. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 83 ...

  • Page 84

    ... Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x46 Interrupt Vector 54 0x47-0x7F Reserved See “Exception Types” on page 99 for more information. The value of this field is only meaningful when accessing PSR or IPSR. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 85

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority effect. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ...

  • Page 86

    ... R/W 0 Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. Texas Instruments-Advance Information ...

  • Page 87

    ... All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ...

  • Page 88

    ... MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. Texas Instruments-Advance Information ...

  • Page 89

    ... The processor has a fixed memory map that provides addressable memory. The memory map for the LM3S5651 controller is provided in Table 2-4 on page 89. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. ...

  • Page 90

    ... ADC1 Reserved Analog Comparators GPIO Port J Reserved CAN0 Controller CAN1 Controller Reserved USB Reserved Reserved GPIO Port A (AHB aperture) GPIO Port B (AHB aperture) Texas Instruments-Advance Information For details, see page ... 428 697 697 - 634 634 634 - 741 741 - 428 428 428 ...

  • Page 91

    ... Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) Reserved Trace Port Interface Unit (TPIU) Reserved Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller For details, see page ... 428 428 428 428 428 ...

  • Page 92

    ... Strongly XN bus Ordered Reserved - - Texas Instruments-Advance Information Description This executable region is for program code. Data can also be stored here. This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 94). ...

  • Page 93

    ... If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 93 ...

  • Page 94

    ... Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 95

    ... The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 95 ...

  • Page 96

    ... Figure 2-5 on page 97 illustrates how data is stored. 96 32-MB Alias Region 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 1-MB SRAM Bit-Band Region 0x200F.FFFE 0x200F.FFFD 0x2000.0002 0x2000.0001 Texas Instruments-Advance Information 0x23FF.FFE4 0x23FF.FFE0 0x2200.0004 0x2200.0000 0x200F.FFFC 0x2000.0000 March 20, 2011 ...

  • Page 97

    ... The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. March 20, 2011 Register Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 97 ...

  • Page 98

    ... See “Nested Vectored Interrupt Controller (NVIC)” on page 114 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: 98 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 99

    ... Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 99 ...

  • Page 100

    ... NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 101 lists the interrupts on the LM3S5651 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler ...

  • Page 101

    ... Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Activation b Offset Asynchronous Asynchronous Description Processor exceptions GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 PWM Fault PWM Generator 0 PWM Generator 1 ...

  • Page 102

    ... Texas Instruments-Advance Information Description GPIO Port F GPIO Port G GPIO Port H UART2 SSI1 Timer 3A Timer QEI1 CAN0 CAN1 Reserved Hibernation Module USB Reserved µDMA Software µDMA Error ADC1 Sequence 0 ADC1 Sequence 1 ADC1 Sequence 2 ...

  • Page 103

    ... IRQ0 0x0040 Systick 0x003C PendSV 0x0038 Reserved Reserved for Debug SVCall 0x002C Reserved Usage fault 0x0018 Bus fault 0x0014 Memory management fault 0x0010 Hard fault 0x000C NMI 0x0008 Reset 0x0004 Initial SP value 0x0000 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 103 ...

  • Page 104

    ... Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On 104 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 105

    ... Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC March 20, 2011 Pre-IRQ top of stack IRQ top of stack Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 105 ...

  • Page 106

    ... Reserved Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. Reserved Handler Fault Status Register Hard fault Hard Fault Status (HFAULTSTAT) Hard fault Hard Fault Status (HFAULTSTAT) Texas Instruments-Advance Information Bit Name VECT FORCED March 20, 2011 ...

  • Page 107

    ... Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Bit Name a IERR DERR MSTKE MUSTKE BSTKE BUSTKE IBUS ...

  • Page 108

    ... A program might have an idle loop to put the processor back to sleep mode. 108 Address Register Name - Memory Management Fault Address (MMADDR) Bus Fault Address (FAULTADDR) - Texas Instruments-Advance Information Register Description page 167 page 161 page 168 page 161 page 169 page 161 March 20, 2011 ...

  • Page 109

    ... Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 110 lists the supported instructions. Note: In Table 2-13 on page 110: ■ Angle brackets, <>, enclose alternative forms of the operand March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 109 ...

  • Page 110

    ... Load multiple registers, decrement Rn{!}, reglist before Load multiple registers, increment after Rn{!}, reglist Load register with word Rt, [Rn, #offset] Load register with byte Rt, [Rn, #offset] Load register with two bytes Rt, Rt2, [Rn, #offset] Texas Instruments-Advance Information Flags N,Z,C,V N,Z,C,V N,Z,C,V - N,Z,C N,Z N,Z,C ...

  • Page 111

    ... Rn Send event Signed multiply with accumulate RdLo, RdHi, Rn, Rm (32x32+64), 64-bit result Signed multiply (32x32), 64-bit result RdLo, RdHi, Rn, Rm Signed saturate Rd, #n, Rm {,shift #s} Store multiple registers, increment after Rn{!}, reglist Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Flags - - - - - - - N,Z,C N,Z ...

  • Page 112

    ... RdLo, RdHi, Rn, Rm Unsigned Saturate Rd, #n, Rm {,shift #s} Zero extend a Byte {Rd,} Rm, {,ROR #n} Zero extend a Halfword {Rd,} Rm, {,ROR #n} Unsigned saturate Rd, #n, Rm {,shift #s} Zero extend a byte {Rd,} Rm {,ROR #n} Zero extend a halfword {Rd,} Rm {,ROR #n} - Wait for event - Wait for interrupt Texas Instruments-Advance Information Flags - - - - - - - - - - - - N,Z,C,V N,Z,C,V - ...

  • Page 113

    ... A high-speed alarm timer using the system clock. March 20, 2011 ® implementation of the Cortex-M3 processor Core Peripheral System Timer Nested Vectored Interrupt Controller System Control Block Memory Protection Unit Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Description (see page ...) 113 114 116 116 113 ...

  • Page 114

    ... Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). 114 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 115

    ... Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 115 ...

  • Page 116

    ... Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. 116 Description All accesses to Strongly Ordered memory occur in program order. Memory-mapped peripherals Normal memory Texas Instruments-Advance Information March 20, 2011 ...

  • Page 117

    ... Region Number ; Region Base Address ; Region Size and Enable ; Region Attribute ; 0xE000ED98, MPU region number register ; Region Number ; Disable ; Region Size and Enable ; Region Base Address ; Region Attribute ; Enable ; Region Size and Enable Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 117 ...

  • Page 118

    ... MPU Region Base register ; Region base address and region number combined ; with VALID (bit 4) set ; Region Attribute, Size and Enable ; 0xE000ED9C, MPU Region Base register ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Texas Instruments-Advance Information March 20, 2011 ...

  • Page 119

    ... Normal 0 Normal 1 Normal 1 Normal 0 Normal 0 Normal 1 Reserved encoding 0 Reserved encoding 1 Normal 1 Normal Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB 64KB 0 Shareability Other Attributes Shareable - Shareable - Not shareable Outer and inner Shareable write-through ...

  • Page 120

    ... Reads by privileged software only. RO Read-only, by privileged or unprivileged software. RO Read-only, by privileged or unprivileged software. TEX 000b 000b Texas Instruments-Advance Information Shareability Other Attributes Not shareable Nonshared Device Not shareable Cached memory (BB = outer policy inner Shareable policy). See Table 3-4 for the encoding of the AA and BB bits. ...

  • Page 121

    ... Interrupt 32-54 Clear Pending 0x0000.0000 Interrupt 0-31 Active Bit 0x0000.0000 Interrupt 32-54 Active Bit 0x0000.0000 Interrupt 0-3 Priority Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Memory Type and Attributes Normal memory, shareable, write-back, write-allocate Device memory, shareable See page 124 126 ...

  • Page 122

    ... System Handler Priority 3 0x0000.0000 System Handler Control and State 0x0000.0000 Configurable Fault Status 0x0000.0000 Hard Fault Status - Memory Management Fault Address - Bus Fault Address 0x0000.0800 MPU Type Texas Instruments-Advance Information See page 138 138 138 138 138 138 138 138 138 138 ...

  • Page 123

    ... MPU Region Base Address Alias 2 0x0000.0000 MPU Region Attribute and Size Alias 2 0x0000.0000 MPU Region Base Address Alias 3 0x0000.0000 MPU Region Attribute and Size Alias 3 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller See page 171 173 174 176 174 176 ...

  • Page 124

    ... R/W 1 Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. Texas Instruments-Advance Information COUNT ...

  • Page 125

    ... Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 125 ...

  • Page 126

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. Texas Instruments-Advance Information RELOAD ...

  • Page 127

    ... This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ...

  • Page 128

    ... Interrupt Enable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. Texas Instruments-Advance Information R/W R/W R/W R/W R/W ...

  • Page 129

    ... Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller INT R/W R/W R/W ...

  • Page 130

    ... Type Reset Description R/W 0x0000.0000 Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R ...

  • Page 131

    ... Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller INT R/W R/W R/W R/W R/W ...

  • Page 132

    ... On a write, no effect read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. Texas Instruments-Advance Information R/W R/W ...

  • Page 133

    ... On a read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller INT ...

  • Page 134

    ... On a read, indicates that the interrupt is not pending write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Advance Information R/W ...

  • Page 135

    ... On a write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller INT ...

  • Page 136

    ... Offset 0x300 Type RO, reset 0x0000.0000 Type Reset Type Reset Bit/Field Name 31:0 INT 136 INT INT Type Reset Description RO 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 137

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0x00.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller INT ...

  • Page 138

    ... Application Interrupt and Reset Control (APINT) register (see page 148) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. 138 Interrupt Interrupt [4n+3] Interrupt [4n+2] Interrupt [4n+1] Interrupt [4n] Texas Instruments-Advance Information March 20, 2011 ...

  • Page 139

    ... PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller reserved ...

  • Page 140

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WO 0x00 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. Texas Instruments-Advance Information ...

  • Page 141

    ... In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M3 processor. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ...

  • Page 142

    ... No effect. 1 Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 143

    ... Constant Value Description 0xF Always reads as 0xF. RO 0xC23 Part Number Value Description 0xC23 Cortex-M3 processor. RO 0x0 Revision Number Value Description 0x0 The pn value in the rnpn product revision identifier, for example, the 0 in r2p0. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller CON ...

  • Page 144

    ... On a read, indicates a PendSV exception is not pending write, no effect read, indicates a PendSV exception is pending write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing the UNPENDSV bit. Texas Instruments-Advance Information ...

  • Page 145

    ... This bit provides status for all interrupts excluding NMI and Faults. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 145 ...

  • Page 146

    ... ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 81). Texas Instruments-Advance Information March 20, 2011 ...

  • Page 147

    ... Because there are 54 interrupts, the minimum alignment is 128 words. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller R/W ...

  • Page 148

    ... Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Group Subpriorities Priorities ...

  • Page 149

    ... This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable System Reset This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 149 ...

  • Page 150

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. Texas Instruments-Advance Information ...

  • Page 151

    ... Setting this bit enables an interrupt-driven application to avoid returning to an empty main application Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 151 ...

  • Page 152

    ... The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 153

    ... The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 105 for more information). Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 153 ...

  • Page 154

    ... Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 155

    ... RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ...

  • Page 156

    ... This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 157

    ... Usage Fault Enable Value Description 0 Disables the usage fault exception. 1 Enables the usage fault exception. R/W 0 Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller USAGE BUS R/W R ...

  • Page 158

    ... This bit can be modified to change the pending status of the usage fault exception. R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 159

    ... Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 159 ...

  • Page 160

    ... Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 161

    ... Type Reset Description RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller NOCP INVPC INVSTAT UNDEF RO RO R/W1C ...

  • Page 162

    ... The processor has attempted an illegal load of EXC_RETURN to the result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing it. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 163

    ... Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 163 ...

  • Page 164

    ... An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 165

    ... MMADDR register. This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 165 ...

  • Page 166

    ... This fault occurs on any access region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing it. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 167

    ... This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ...

  • Page 168

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. Texas Instruments-Advance Information R/W R/W R/W R/W R/W R R/W R/W R/W ...

  • Page 169

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller R/W R/W R/W R/W R/W R ...

  • Page 170

    ... Indicates there are eight supported MPU data regions. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation Separate or Unified MPU Value Description 0 Indicates the MPU is unified. Texas Instruments-Advance Information IREGION ...

  • Page 171

    ... reserved Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller PRIVDEFEN HFNMIENA ENABLE R/W R/W ...

  • Page 172

    ... When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 173

    ... R/W 0x0 MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ...

  • Page 174

    ... Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Advance Information ...

  • Page 175

    ... R/W 0x0 Region Number On a write, contains the value to be written to the MPUNUMBER register read, returns the current region number in the MPUNUMBER register. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 175 ...

  • Page 176

    ... GB No valid ADDR field in MPUBASE; the region occupies the complete memory map reserved R/W R/W R reserved R/W R/W R Texas Instruments-Advance Information Note Minimum permitted size - - - Maximum possible size TEX S C R/W R/W R/W R/W R/W R SIZE ENABLE R/W R/W R/W R/W R/W ...

  • Page 177

    ... R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 176 for more information. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 177 ...

  • Page 178

    ... Cortex-M3 Peripherals Bit/Field Name 0 ENABLE 178 Type Reset Description R/W 0 Region Enable Value Description 0 The region is disabled. 1 The region is enabled. Texas Instruments-Advance Information March 20, 2011 ...

  • Page 179

    ... Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 179 ...

  • Page 180

    ... JTAG/SWD CLK. PC1 (3) I/O TTL JTAG TMS and SWDIO. PC3 (3) O TTL JTAG TDO and SWO. PC0 (3) I TTL JTAG/SWD CLK. PC2 (3) I TTL JTAG TDI. PC3 (3) O TTL JTAG TDO and SWO. Texas Instruments-Advance Information TDO Cortex-M3 Debug Port March 20, 2011 ...

  • Page 181

    ... JTAG TMS and SWDIO. PC3 (3) O TTL JTAG TDO and SWO. PC0 (3) I TTL JTAG/SWD CLK. PC2 (3) I TTL JTAG TDI. PC3 (3) O TTL JTAG TDO and SWO. PC1 (3) I TTL JTAG TMS and SWDIO. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 181 ...

  • Page 182

    ... The value of TDO depends on the current TAP state, the current instruction, and the data in the 182 Internal Pull-Up Internal Pull-Down Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Enabled Disabled Texas Instruments-Advance Information Drive Strength Drive Value N/A N/A N/A N/A N/A N/A 2-mA driver High-Z March 20, 2011 ...

  • Page 183

    ... TAP controller’s CAPTURE states and allows March 20, 2011 Select DR Scan 1 0 Capture Shift Exit Pause Exit Update Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Select IR Scan 1 0 Capture IR 0 Shift Exit Pause Exit Update 183 ...

  • Page 184

    ... ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. 184 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 185

    ... Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 185 ...

  • Page 186

    ... JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings. 186 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 187

    ... Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. BYPASS Connects TDI to TDO through a single Shift Register chain. Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 187 ...

  • Page 188

    ... ARM core. This information can be used by testing equipment and debuggers to automatically configure input and output data streams. IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 189 for more information. 188 Texas Instruments-Advance Information March 20, 2011 ...

  • Page 189

    ... The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each March 20, 2011 12 11 Part Number Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 1 0 TDO Manufacturer ID 1 189 ...

  • Page 190

    ... The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 190 ... GPIO (m+1) GPIO Texas Instruments-Advance Information O TDO ... GPIO n March 20, 2011 ...

  • Page 191

    ... PB7 (4) I TTL Non-maskable interrupt. fixed I Analog Main oscillator crystal input or an external clock reference input. fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. fixed I TTL System reset input. Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller 191 ...

  • Page 192

    ... This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 Reset Sources The LM3S5651 microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 193). 2. External reset input pin (RST) assertion (see page 194). 3. Internal brown-out (BOR) detector (see page 195). ...

  • Page 193

    ... The internal POR is only active on the initial power-up of the microcontroller and when the microcontroller wakes from hibernation. The Power-On Reset timing is shown in Figure 25-4 on page 1179. March 20, 2011 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ) and generates DD 193 ...

  • Page 194

    ... Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RST kΩ to 100 kΩ µ the application requires the use of an external reset switch, Figure 5-3 on page 195 shows the proper circuitry to use. 194 VDD Texas Instruments-Advance Information and then de-asserted MIN March 20, 2011 ...

  • Page 195

    ... The internal Brown-Out Reset timing is shown in Figure 25-5 on page 1179. March 20, 2011 VDD brown-out condition is detected, the system BTH , an internal BOR condition is set. BTH level is restored. The RESC register can be examined DD Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller ) DD 195 ...

  • Page 196

    ... Watchdog Timer Reset The Watchdog Timer module's function is to prevent system hangs. The LM3S5651 microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module operates in the same manner except that because the PIOSC watchdog timer module different clock domain, register accesses must have a time delay between them ...

  • Page 197

    ... Main Oscillator Verification Failure The LM3S5651 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, a power-on reset is generated and control is transferred to the NMI handler ...

  • Page 198

    ... OSC0 input and OSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz to 198 GND Internal Logic and PLL GND Low-Noise LDO GND I/O Buffers GND GNDA Analog Circuits GNDA Texas Instruments-Advance Information March 20, 2011 ...

  • Page 199

    ... March 20, 2011 Drive PLL? Yes BYPASS = 0, OSCSRC = 0x1 No - Yes BYPASS = 0, OSCSRC = 0x0 Texas Instruments-Advance Information Stellaris® LM3S5651 Microcontroller Used as SysClk? Yes BYPASS = 1, OSCSRC = 0x1 Yes BYPASS = 1, OSCSRC = 0x2 Yes BYPASS = 1, OSCSRC = 0x0 Yes BYPASS = 1, OSCSRC = 0x3 Yes BYPASS = 1, OSCSRC2 = 0x7 No - 199 ...

  • Page 200

    ... PWMDIV in RCC). Note: When the ADC module is in operation, the system clock must be at least 16 MHz. When the USB module is in operation, MOSC must be provided with a clock source, and the system clock must be at least 20 MHz. 200 Texas Instruments-Advance Information March 20, 2011 ...