LM3S6611-IBZ50-A2T

Manufacturer Part NumberLM3S6611-IBZ50-A2T
DescriptionIC ARM CORTEX MCU 128KB 108NFBGA
ManufacturerTexas Instruments
SeriesStellaris® 6000
LM3S6611-IBZ50-A2T datasheets
 


Specifications of LM3S6611-IBZ50-A2T

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed50MHzConnectivityEthernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o46
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size32K x 8Voltage - Supply (vcc/vdd)2.25 V ~ 2.75 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case108-NFBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
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TE X AS I NS TRUM E NT S -P RO DUC TI O N D ATA
Stellaris® LM3S6611 Microcontroller
D ATA S HE E T
D S- L M3S 66 11 - 9 102
Co pyri gh t © 2 00 7 -2 011
Texas In strumen ts Inco rpora ted

LM3S6611-IBZ50-A2T Summary of contents

  • Page 1

    ... Stellaris® LM3S6611 Microcontroller M3S 102 TRUM DUC ATA D ATA pyri gh t © 011 Texas In strumen ts Inco rpora ted ...

  • Page 2

    ... Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ...

  • Page 3

    ... Memory System Ordering of Memory Accesses .............................................................. 65 2.4.3 Behavior of Memory Accesses ....................................................................................... 65 2.4.4 Software Ordering of Memory Accesses ......................................................................... 66 2.4.5 Bit-Banding ................................................................................................................... 67 2.4.6 Data Storage ................................................................................................................ 69 2.4.7 Synchronization Primitives ............................................................................................. 70 2.5 Exception Model ........................................................................................................... 71 2.5.1 Exception States ........................................................................................................... 71 2.5.2 Exception Types ............................................................................................................ 72 2.5.3 Exception Handlers ....................................................................................................... 75 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 3 ...

  • Page 4

    ... Reset Control .............................................................................................................. 162 5.1.3 Power Control ............................................................................................................. 166 5.1.4 Clock Control .............................................................................................................. 167 5.1.5 System Control ........................................................................................................... 172 5.2 Initialization and Configuration ..................................................................................... 173 5.3 Register Map .............................................................................................................. 174 5.4 Register Descriptions .................................................................................................. 175 6 Hibernation Module .............................................................................................. 225 6.1 Block Diagram ............................................................................................................ 226 4 Texas Instruments-Production Data January 09, 2011 ...

  • Page 5

    ... GPTM Reset Conditions .............................................................................................. 314 9.2.2 32-Bit Timer Operating Modes ...................................................................................... 314 9.2.3 16-Bit Timer Operating Modes ...................................................................................... 315 9.3 Initialization and Configuration ..................................................................................... 319 9.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 319 9.3.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 320 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 5 ...

  • Page 6

    ... C Bus Functional Overview ........................................................................................ 451 13.2.2 Available Speed Modes ............................................................................................... 453 13.2.3 Interrupts .................................................................................................................... 454 13.2.4 Loopback Operation .................................................................................................... 455 13.2.5 Command Sequence Flow Charts ................................................................................ 455 13.3 Initialization and Configuration ..................................................................................... 462 13.4 Register Map .............................................................................................................. 463 13.5 Register Descriptions ( Interface ................................................................ 450 2 C Master) ............................................................................... 464 Texas Instruments-Production Data January 09, 2011 ...

  • Page 7

    ... JTAG and Boundary Scan ............................................................................................ 580 19.2.4 Reset ......................................................................................................................... 582 19.2.5 Sleep Modes ............................................................................................................... 584 19.2.6 Hibernation Module ..................................................................................................... 584 19.2.7 General-Purpose I/O (GPIO) ........................................................................................ 584 19.2.8 Synchronous Serial Interface (SSI) ............................................................................... 585 19.2.9 Inter-Integrated Circuit (I January 09, 2011 2 C Slave) ................................................................................. 477 2 C) Interface ........................................................................... 586 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 7 ...

  • Page 8

    ... LQFP Package ............................................................................................... 617 D.1.1 Package Dimensions ................................................................................................... 617 D.1.2 Tray Dimensions ......................................................................................................... 619 D.1.3 Tape and Reel Dimensions .......................................................................................... 619 D.2 108-Ball BGA Package ................................................................................................ 621 D.2.1 Package Dimensions ................................................................................................... 621 D.2.2 Tray Dimensions ......................................................................................................... 623 D.2.3 Tape and Reel Dimensions .......................................................................................... 624 8 Texas Instruments-Production Data January 09, 2011 ...

  • Page 9

    ... List of Figures Figure 1-1. Stellaris LM3S6611 Microcontroller High-Level Block Diagram ............................... 37 Figure 2-1. CPU Block Diagram ............................................................................................. 46 Figure 2-2. TPIU Block Diagram ............................................................................................ 47 Figure 2-3. Cortex-M3 Register Set ........................................................................................ 49 Figure 2-4. Bit-Band Mapping ................................................................................................ 69 Figure 2-5. Data Storage ....................................................................................................... 70 Figure 2-6. Vector table ......................................................................................................... 76 Figure 2-7. Exception Stack Frame ........................................................................................ 78 Figure 3-1 ...

  • Page 10

    ... LQFP Tray Dimensions .......................................................................... 619 Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 620 Figure D-4. 108-Ball BGA Package Dimensions .................................................................... 621 Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 623 Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 624 Bus ................................................... 453 Texas Instruments-Production Data January 09, 2011 ...

  • Page 11

    ... Timers Register Map .......................................................................................... 322 Table 10-1. Watchdog Timer Register Map ............................................................................ 350 Table 11-1. UART Register Map ........................................................................................... 379 Table 12-1. SSI Register Map .............................................................................................. 424 Table 13-1. Examples of I January 09, 2011 2 C Master Timer Period versus Speed Mode ................................... 454 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 11 ...

  • Page 12

    ... Table 19-24. 10BASE-T Transmitter Characteristics (informative) ............................................. 588 Table 19-25. 10BASE-T Receiver Characteristics .................................................................... 588 Table 19-26. Isolation Transformers ....................................................................................... 588 Table 19-27. Ethernet Reference Crystal ................................................................................ 589 Table 19-28. External XTLP Oscillator Characteristics ............................................................. 590 Table 19-29. Analog Comparator Characteristics ..................................................................... 590 Interface Register Map ............................................. 463 Texas Instruments-Production Data January 09, 2011 ...

  • Page 13

    ... Table 19-30. Analog Comparator Voltage Reference Characteristics ........................................ 590 Table C-1. Part Ordering Information ................................................................................... 615 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 13 ...

  • Page 14

    ... Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 111 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 111 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 111 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 111 Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 111 14 Texas Instruments-Production Data January 09, 2011 ...

  • Page 15

    ... Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 198 Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 200 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 202 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 203 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 15 ...

  • Page 16

    ... GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 279 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 280 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 281 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 282 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 283 16 Texas Instruments-Production Data January 09, 2011 ...

  • Page 17

    ... GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 345 Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 346 Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 347 Watchdog Timer ........................................................................................................................... 348 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 352 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 353 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 17 ...

  • Page 18

    ... UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 411 Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 412 Synchronous Serial Interface (SSI) ............................................................................................ 413 Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 425 Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 427 Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 429 18 Texas Instruments-Production Data January 09, 2011 ...

  • Page 19

    ... Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 507 Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 509 Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 510 Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 511 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 19 ...

  • Page 20

    ... Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 540 Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 541 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 541 Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 542 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 542 20 Texas Instruments-Production Data January 09, 2011 ...

  • Page 21

    ... Revision History The revision history table notes changes made between the indicated revisions of the LM3S6611 data sheet. Table 1. Revision History Date Revision Description January 2011 9102 ■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ to SYSRESREQ. ■ ...

  • Page 22

    ... V parameters from Operating Conditions table. SIH SIL Added table showing actual PLL frequency depending on input crystal. Changed the name of the t parameter to t HIB_REG_WRITE Changed SSI set up and hold times to be expressed in system clocks, not ns. Texas Instruments-Production Data . HIB_REG_ACCESS January 09, 2011 ...

  • Page 23

    ... Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter. August 2008 3447 ■ Added note on clearing interrupts to Interrupts chapter. ■ Added Power Architecture diagram to System Control chapter. ■ Additional minor data sheet clarifications and corrections. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller IR 23 ...

  • Page 24

    ... Battery voltage is not measured while in Hibernate mode. System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. Texas Instruments-Production Data ) in the "Maximum Ratings" table in the "Electrical January 09, 2011 ...

  • Page 25

    ... Started tracking revision history. January 09, 2011 The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins. The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 25 ...

  • Page 26

    ... About This Document About This Document This data sheet provides reference information for the LM3S6611 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers ...

  • Page 27

    ... Bit set chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 27 ...

  • Page 28

    ... Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 28 Texas Instruments-Production Data January 09, 2011 ...

  • Page 29

    ... For applications requiring extreme conservation of power, the LM3S6611 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S6611 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S6611 microcontroller perfectly for battery applications ...

  • Page 30

    ... Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer – Optimized for single-cycle flash usage – Three sleep modes with clock gating for low power – Single-cycle multiply instruction and hardware divide – Atomic operations – ARM Thumb2 mixed 16-/32-bit instruction set 30 Texas Instruments-Production Data January 09, 2011 ...

  • Page 31

    ... User-defined and managed flash-protection block – single-cycle SRAM ■ GPIOs – 10-46 GPIOs, depending on configuration – 5-V-tolerant in input configuration – Programmable control for GPIO interrupts • Interrupt generation masking • Edge-triggered on rising, falling, or both January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 31 ...

  • Page 32

    ... Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug – 16-bit Input Capture modes • Input edge count capture • Input edge time capture 32 Texas Instruments-Production Data January 09, 2011 ...

  • Page 33

    ... Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations • Programmable internal clock generator enabling division of reference clock 256 for low-power mode bit duration ■ Synchronous Serial Interface (SSI) – Two SSI modules, each with the following features: January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 33 ...

  • Page 34

    ... Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from bits – ...

  • Page 35

    ... Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – 3.3-V supply brown-out detection and reporting via interrupt or reset January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 35 ...

  • Page 36

    ... HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 37 depicts the features on the Stellaris LM3S6611 microcontroller. 36 Texas Instruments-Production Data January 09, 2011 ...

  • Page 37

    ... Figure 1-1. Stellaris LM3S6611 Microcontroller High-Level Block Diagram LM3S6611 January 09, 2011 JTAG/SWD ARM® Cortex -M3 (50 MHz) System Control and Clocks NVIC Bus Matrix Hibernation Module GPIOs (10-46) I2C (2) Ethernet MAC/PHY Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Flash DCode bus ...

  • Page 38

    ... Memory Map (see page 63) A memory map lists the location of instructions and data in memory. The memory map for the LM3S6611 controller can be found in Table 2-4 on page 63. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. ...

  • Page 39

    ... The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S6611 controller features Pulse Width Modulation (PWM) outputs. 1.4.2.1 PWM Pulse width modulation (PWM powerful technique for digitally encoding analog signal levels. ...

  • Page 40

    ... Synchronous Serial Interface (SSI four-wire bi-directional full and low-speed communications interface. The LM3S6611 controller includes two SSI modules that provide the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive ...

  • Page 41

    ... January 09, 2011 2 C modes are: Master Transmit, Master Receive, Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 2 C module supports 2 C master generates interrupts when 2 ...

  • Page 42

    ... Flash (see page 246) The LM3S6611 Flash controller supports 128 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected ...

  • Page 43

    ... Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 544 ■ “Signal Tables” on page 546 ■ “Operating Characteristics” on page 574 ■ “Electrical Characteristics” on page 575 ■ “Package Information” on page 617 January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 43 ...

  • Page 44

    ... DMIPS/MHz ® The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. 44 Texas Instruments-Production Data January 09, 2011 ...

  • Page 45

    ... ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 45 ...

  • Page 46

    ... Data Memory Protection Unit Data Watchpoint Flash and Trace Patch and Breakpoint Private Peripheral Bus (internal) Bus Matrix Debug Access Port Texas Instruments-Production Data Serial ARM Wire Cortex-M3 Output Trace Port Trace (SWO) Port Interface Unit Instrumentation Trace Macrocell ROM Table Adv ...

  • Page 47

    ... An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 87). ■ System Control Block (SCB) January 09, 2011 Asynchronous FIFO Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Serial Wire Trace Out Trace Port (serializer) (SWO) ...

  • Page 48

    ... The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements 48 Texas Instruments-Production Data January 09, 2011 ...

  • Page 49

    ... SP (R13) PSP LR (R14) PC (R15) PSR Program status register PRIMASK FAULTMASK Exception mask registers BASEPRI CONTROL CONTROL register Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Stack Used a Main stack or process stack Main stack ‡ ‡ MSP Banked version of SP Special registers a 49 ...

  • Page 50

    ... Cortex General-Purpose Register 10 - Cortex General-Purpose Register 11 - Cortex General-Purpose Register 12 - Stack Pointer 0xFFFF.FFFF Link Register - Program Counter 0x0100.0000 Program Status Register 0x0000.0000 Priority Mask Register 0x0000.0000 Fault Mask Register 0x0000.0000 Base Priority Mask Register 0x0000.0000 Control Register Texas Instruments-Production Data See page ...

  • Page 51

    ... Bit/Field Name 31:0 DATA January 09, 2011 DATA R/W R/W R/W R/W R DATA R/W R/W R/W R/W R Type Reset Description R/W - Register data. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 52

    ... R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the address of the stack pointer. Texas Instruments-Production Data R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R January 09, 2011 - 0 - ...

  • Page 53

    ... LINK January 09, 2011 LINK R/W R/W R/W R/W R LINK R/W R/W R/W R/W R Type Reset Description R/W 0xFFFF.FFFF This field is the return address. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R ...

  • Page 54

    ... R/W R/W R/W R/W R/W Reset - - - - - Bit/Field Name 31 R/W R/W R/W R/W R R/W R/W R/W R/W R Type Reset Description R/W - This field is the current program address. Texas Instruments-Production Data R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R January 09, 2011 - 0 - ...

  • Page 55

    ... R/W R/W R/W R/W R/W Reset ICI / IT Type Reset January 09, 2011 Type Combination R/W APSR, EPSR, and IPSR RO EPSR and IPSR a R/W APSR and IPSR b R/W APSR and EPSR ICI / IT THUMB reserved Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller reserved ISRNUM ...

  • Page 56

    ... DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. Texas Instruments-Production Data January 09, 2011 ...

  • Page 57

    ... The value of this field is only meaningful when accessing PSR or EPSR. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 57 ...

  • Page 58

    ... Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3B Interrupt Vector 43 0x3C-0x3F Reserved See “Exception Types” on page 72 for more information. The value of this field is only meaningful when accessing PSR or IPSR. Texas Instruments-Production Data January 09, 2011 ...

  • Page 59

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0 Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority effect. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 60

    ... R/W 0 Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. Texas Instruments-Production Data ...

  • Page 61

    ... All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 62

    ... MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. Texas Instruments-Production Data ...

  • Page 63

    ... The processor has a fixed memory map that provides addressable memory. The memory map for the LM3S6611 controller is provided in Table 2-4 on page 63. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. ...

  • Page 64

    ... Reserved Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) Reserved Trace Port Interface Unit (TPIU) Reserved Texas Instruments-Production Data For details, see page ... 424 - 379 379 379 - ...

  • Page 65

    ... Device XN External RAM Normal - Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Description This executable region is for program code. Data can also be stored here. This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 67) ...

  • Page 66

    ... DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. 66 Memory Region Memory Type Execute Never (XN) External device Device XN Private peripheral Strongly XN bus Ordered Reserved - - Texas Instruments-Production Data Description This region is for external device memory. This region includes the NVIC, system timer, and system control block. - January 09, 2011 ...

  • Page 67

    ... Table 2-6. SRAM Memory Bit-Banding Regions Address Range 0x2000.0000 - 0x200F.FFFF January 09, 2011 Memory Region Instruction and Data Accesses SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 67 ...

  • Page 68

    ... Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Texas Instruments-Production Data January 09, 2011 ...

  • Page 69

    ... Figure 2-5 on page 70 illustrates how data is stored. January 09, 2011 32-MB Alias Region 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 1-MB SRAM Bit-Band Region 0x200F.FFFE 0x200F.FFFD 0x2000.0002 0x2000.0001 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 0x23FF.FFE4 0x23FF.FFE0 0x2200.0004 0x2200.0000 0x200F.FFFC 0x2000.0000 69 ...

  • Page 70

    ... The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 70 Register Texas Instruments-Production Data January 09, 2011 ...

  • Page 71

    ... See “Nested Vectored Interrupt Controller (NVIC)” on page 87 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 71 ...

  • Page 72

    ... Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return 72 Texas Instruments-Production Data January 09, 2011 ...

  • Page 73

    ... NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 74 lists the interrupts on the LM3S6611 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler ...

  • Page 74

    ... Texas Instruments-Production Data Activation b Offset Asynchronous Asynchronous Description Processor exceptions GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 Reserved Watchdog Timer 0 Timer 0A Timer 0B Timer 1A Timer 1B ...

  • Page 75

    ... Table 2-8 on page 73. Figure 2-6 on page 76 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code January 09, 2011 Vector Address or Description Offset 38-41 - Reserved 42 0x0000.00E8 Ethernet Controller 43 0x0000.00EC Hibernation Module Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 75 ...

  • Page 76

    ... IRQ1 0x0044 IRQ0 0x0040 Systick 0x003C PendSV 0x0038 Reserved Reserved for Debug SVCall 0x002C Reserved Usage fault 0x0018 Bus fault 0x0014 Memory management fault 0x0010 Hard fault 0x000C NMI 0x0008 Reset 0x0004 Initial SP value 0x0000 Texas Instruments-Production Data January 09, 2011 ...

  • Page 77

    ... Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 77 ...

  • Page 78

    ... If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. 78 Pre-IRQ top of stack IRQ top of stack Texas Instruments-Production Data January 09, 2011 ...

  • Page 79

    ... Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses state from MSP. Execution uses MSP after return. Reserved Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. Reserved Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 79 ...

  • Page 80

    ... Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) Texas Instruments-Production Data Bit Name VECT FORCED a IERR DERR MSTKE MUSTKE BSTKE ...

  • Page 81

    ... Sleep mode and Deep-sleep mode. January 09, 2011 Address Register Name - Memory Management Fault Address (MMADDR) Bus Fault Address (FAULTADDR) - Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Register Description page 138 page 132 page 139 page 132 page 140 page 132 81 ...

  • Page 82

    ... In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 121. 82 Texas Instruments-Production Data January 09, 2011 ...

  • Page 83

    ... Rn , Op2 Change processor state, disable iflags interrupts Change processor state, enable iflags interrupts Data memory barrier - Data synchronization barrier - Exclusive OR { Op2 Instruction synchronization barrier - - If-Then condition block Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Flags N,Z,C,V N,Z,C,V N,Z,C,V - N,Z,C N,Z N,Z ...

  • Page 84

    ... Reverse byte order in each halfword Reverse byte order in bottom halfword and sign extend Rotate right <Rs|#n> Rotate right with extend Reverse subtract {Rd Op2 Subtract with carry {Rd Op2 Signed bit field extract #lsb , #width Texas Instruments-Production Data Flags - - - - - - - - - - - - - ...

  • Page 85

    ... RdLo, RdHi, Rn, Rm (32x32+32+32), 64-bit result Unsigned multiply (32x 2), 64-bit result RdLo, RdHi, Rn, Rm Unsigned saturate Rd, #n, Rm {,shift #s} Zero extend a byte {Rd,} Rm {,ROR #n} Zero extend a halfword {Rd,} Rm {,ROR #n} - Wait for event - Wait for interrupt Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Flags - - - - ...

  • Page 86

    ... An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. 86 ® implementation of the Cortex-M3 processor Core Peripheral System Timer Nested Vectored Interrupt Controller System Control Block Memory Protection Unit Texas Instruments-Production Data Description (see page ...) January 09, 2011 ...

  • Page 87

    ... Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 87 ...

  • Page 88

    ... ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 88 Texas Instruments-Production Data January 09, 2011 ...

  • Page 89

    ... Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. January 09, 2011 Description All accesses to Strongly Ordered memory occur in program order. Memory-mapped peripherals Normal memory Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 89 ...

  • Page 90

    ... MPU region number register ; Region Number ; Region Base Address ; Region Size and Enable ; Region Attribute ; 0xE000ED98, MPU region number register ; Region Number ; Disable ; Region Size and Enable ; Region Base Address ; Region Attribute ; Enable ; Region Size and Enable Texas Instruments-Production Data January 09, 2011 ...

  • Page 91

    ... Region base address and region number combined ; with VALID (bit 4) set ; Region Attribute, Size and Enable ; 0xE000ED9C, MPU Region Base register ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 91 ...

  • Page 92

    ... Shareable 0 Normal Not shareable 0 Normal Shareable 1 Reserved encoding - 0 Reserved encoding - 1 Normal Not shareable 1 Normal Shareable Texas Instruments-Production Data Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB 64KB 0 Other Attributes - - Outer and inner write-through. No write allocate. Outer and inner noncacheable ...

  • Page 93

    ... Read-only, by privileged or unprivileged software. RO Read-only, by privileged or unprivileged software. TEX 000b 000b Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Shareability Other Attributes Not shareable Nonshared Device Not shareable Cached memory (BB = outer policy inner Shareable policy). See Table 3-4 for the encoding of the AA and BB bits ...

  • Page 94

    ... Interrupt 0-31 Clear Pending 0x0000.0000 Interrupt 32-43 Clear Pending 0x0000.0000 Interrupt 0-31 Active Bit 0x0000.0000 Interrupt 32-43 Active Bit 0x0000.0000 Interrupt 0-3 Priority Texas Instruments-Production Data Memory Type and Attributes Normal memory, shareable, write-back, write-allocate Device memory, shareable See page 97 99 ...

  • Page 95

    ... Bus Fault Address 0x0000.0800 MPU Type 0x0000.0000 MPU Control 0x0000.0000 MPU Region Number 0x0000.0000 MPU Region Base Address 0x0000.0000 MPU Region Attribute and Size Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller See page 111 111 111 111 111 111 111 111 111 ...

  • Page 96

    ... MPU Region Attribute and Size Alias 1 0x0000.0000 MPU Region Base Address Alias 2 0x0000.0000 MPU Region Attribute and Size Alias 2 0x0000.0000 MPU Region Base Address Alias 3 0x0000.0000 MPU Region Attribute and Size Alias 3 Texas Instruments-Production Data See page 145 147 145 147 145 147 ...

  • Page 97

    ... R/W 0 Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller COUNT ...

  • Page 98

    ... Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. Texas Instruments-Production Data January 09, 2011 ...

  • Page 99

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller RELOAD R/W ...

  • Page 100

    ... This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. Texas Instruments-Production Data ...

  • Page 101

    ... Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller R/W R/W R/W R/W ...

  • Page 102

    ... R/W 0x000 Interrupt Enable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. Texas Instruments-Production Data ...

  • Page 103

    ... Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller R/W R/W R/W R/W R/W R/W ...

  • Page 104

    ... R/W 0x000 Interrupt Disable Value Description read, indicates the interrupt is disabled write, no effect read, indicates the interrupt is enabled write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. Texas Instruments-Production Data ...

  • Page 105

    ... On a read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller R/W ...

  • Page 106

    ... On a write, no effect read, indicates that the interrupt is pending write, the corresponding interrupt is set to pending even disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. Texas Instruments-Production Data ...

  • Page 107

    ... On a write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller R/W ...

  • Page 108

    ... On a read, indicates that the interrupt is not pending write, no effect read, indicates that the interrupt is pending write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [ longer pending. Setting a bit does not affect the active state of the corresponding interrupt. Texas Instruments-Production Data ...

  • Page 109

    ... Type Reset Type Reset Bit/Field Name 31:0 INT January 09, 2011 INT INT Type Reset Description RO 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 109 ...

  • Page 110

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RO 0x000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. Texas Instruments-Production Data ...

  • Page 111

    ... Offset 0x400 Type R/W, reset 0x0000.0000 INTD Type R/W R/W R Reset INTB Type R/W R/W R Reset January 09, 2011 Interrupt Interrupt [4n+3] Interrupt [4n+2] Interrupt [4n+1] Interrupt [4n reserved INTC R/W R reserved INTA R/W R Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller reserved R reserved R 111 ...

  • Page 112

    ... PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data January 09, 2011 ...

  • Page 113

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WO 0x00 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 114

    ... RO 0xF Constant Value Description 0xF Always reads as 0xF. RO 0xC23 Part Number Value Description 0xC23 Cortex-M3 processor. RO 0x1 Revision Number Value Description 0x1 The pn value in the rnpn product revision identifier, for example, the 1 in r1p1. Texas Instruments-Production Data CON ...

  • Page 115

    ... On a write, no effect read, indicates a PendSV exception is pending write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing the UNPENDSV bit. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 116

    ... This bit provides status for all interrupts excluding NMI and Faults. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data January 09, 2011 ...

  • Page 117

    ... Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 55). Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 117 ...

  • Page 118

    ... Because there are 43 interrupts, the minimum alignment is 64 words. RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 119

    ... The Stellaris implementation uses only little-endian mode so this is cleared 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Group Subpriorities Priorities ...

  • Page 120

    ... Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable System Reset This bit is reserved for Debug use and reads as 0. This bit must be written otherwise behavior is unpredictable. Texas Instruments-Production Data January 09, 2011 ...

  • Page 121

    ... R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 122

    ... Setting this bit enables an interrupt-driven application to avoid returning to an empty main application Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data January 09, 2011 ...

  • Page 123

    ... The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 124

    ... Thread State Control Value Description 0 The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 79 for more information). Texas Instruments-Production Data January 09, 2011 ...

  • Page 125

    ... Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller reserved ...

  • Page 126

    ... This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 127

    ... RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 128

    ... R/W 0 Usage Fault Enable Value Description 0 Disables the usage fault exception. 1 Enables the usage fault exception. R/W 0 Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. Texas Instruments-Production Data USAGE BUS R/W R ...

  • Page 129

    ... SysTick Exception Active Value Description 0 A SysTick exception is not active SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 129 ...

  • Page 130

    ... R/W 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. Texas Instruments-Production Data January 09, 2011 ...

  • Page 131

    ... Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 131 ...

  • Page 132

    ... R/W1C R/W1C Type Reset Description RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data NOCP INVPC INVSTAT UNDEF RO RO R/W1C R/W1C R/W1C ...

  • Page 133

    ... result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing it. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 133 ...

  • Page 134

    ... Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Production Data January 09, 2011 ...

  • Page 135

    ... The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing it. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 135 ...

  • Page 136

    ... MMADDR register. This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data January 09, 2011 ...

  • Page 137

    ... When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing it. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 137 ...

  • Page 138

    ... When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing it Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 139

    ... R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller R/W R/W R/W R/W R/W R ...

  • Page 140

    ... ADDR R/W R/W R/W R/W R Type Reset Description R/W - Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. Texas Instruments-Production Data R/W R/W R/W R/W R/W R R/W R/W R/W ...

  • Page 141

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation Separate or Unified MPU Value Description 0 Indicates the MPU is unified. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller IREGION ...

  • Page 142

    ... reserved Type Reset Description RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data PRIVDEFEN HFNMIENA ENABLE R/W R/W R January 09, 2011 ...

  • Page 143

    ... When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 143 ...

  • Page 144

    ... Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. R/W 0x0 MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. Texas Instruments-Production Data ...

  • Page 145

    ... The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 146

    ... R/W 0x0 Region Number On a write, contains the value to be written to the MPUNUMBER register read, returns the current region number in the MPUNUMBER register. Texas Instruments-Production Data January 09, 2011 ...

  • Page 147

    ... No valid ADDR field in MPUBASE; the region occupies the complete memory map reserved R/W R/W R reserved R/W R/W R Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Note Minimum permitted size - - - Maximum possible size TEX S C R/W R/W R/W R/W R/W R SIZE ENABLE R/W R/W R/W ...

  • Page 148

    ... R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 147 for more information. Texas Instruments-Production Data January 09, 2011 ...

  • Page 149

    ... Bit/Field Name 0 ENABLE January 09, 2011 Type Reset Description R/W 0 Region Enable Value Description 0 The region is disabled. 1 The region is enabled. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 149 ...

  • Page 150

    ... IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 150 Texas Instruments-Production Data January 09, 2011 ...

  • Page 151

    ... The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 4-1 on page 152. Detailed information on each pin follows. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller TDO Cortex-M3 Debug Port ...

  • Page 152

    ... PC1/TMS; otherwise JTAG communication could be lost. 152 Internal Pull-Up Internal Pull-Down Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Input Enabled Disabled Enabled Disabled Texas Instruments-Production Data Drive Strength Drive Value N/A N/A N/A N/A N/A N/A N/A N/A 2-mA driver High-Z January 09, 2011 ...

  • Page 153

    ... TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 153 ...

  • Page 154

    ... In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 154 Select DR Scan 1 0 Capture Shift Exit Pause Exit Update Texas Instruments-Production Data Select IR Scan 1 0 Capture Shift Exit Pause Exit Update January 09, 2011 ...

  • Page 155

    ... Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 155 ...

  • Page 156

    ... LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 156 Texas Instruments-Production Data January 09, 2011 ...

  • Page 157

    ... Description EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 157 ...

  • Page 158

    ... IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. BYPASS Connects TDI to TDO through a single Shift Register chain. Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Texas Instruments-Production Data January 09, 2011 ...

  • Page 159

    ... Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 159 ...

  • Page 160

    ... Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. 160 12 11 Part Number Texas Instruments-Production Data 1 0 TDO Manufacturer ID 1 January 09, 2011 ...

  • Page 161

    ... Interface V5 Architecture Specification. 4.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. January 09, 2011 ... GPIO m RST GPIO m+1 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ... O O TDO GPIO n 161 ...

  • Page 162

    ... Table 5-1 provides a summary of results of the various reset operations. Table 5-1. Reset Sources Reset Source Power-On Reset RST Brown-Out Reset 162 Core Reset? JTAG Reset? Yes Yes Yes Pin Config Only Yes Texas Instruments-Production Data On-Chip Peripherals Reset? Yes Yes No Yes January 09, 2011 ...

  • Page 163

    ... Figure 5-1 on page 164. DD January 09, 2011 Core Reset? JTAG Reset? Yes No Yes crossing 2 guarantee proper operation. For applications DD Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller On-Chip Peripherals Reset? No Yes b No Yes No Yes ) and generates DD ...

  • Page 164

    ... Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RST kΩ to 100 kΩ µ the application requires the use of an external reset switch, Figure 5-3 on page 165 shows the proper circuitry to use. 164 VDD Texas Instruments-Production Data and then de-asserted MIN January 09, 2011 ...

  • Page 165

    ... Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: January 09, 2011 VDD brown-out condition is detected, the system may BTH level is restored. The RESC register can be examined in the reset interrupt DD Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ) drops DD 165 ...

  • Page 166

    ... See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 576. VDDA must be supplied with 3 the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the LDO and the clock circuitry. 166 Texas Instruments-Production Data January 09, 2011 ...

  • Page 167

    ... The frequency of the internal oscillator is 12 MHz ± 30%. January 09, 2011 Ethernet PHY Internal Logic and PLL Low-noise LDO Analog circuits I/O Buffers Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller GNDPHY GNDPHY GNDPHY GNDPHY GND GND GND GND GNDA GNDA ...

  • Page 168

    ... Enabling/disabling of oscillators and PLL 168 Drive PLL? Used as SysClk? No BYPASS = 1 Yes No BYPASS = 1 Yes Yes BYPASS = 0, OSCSRC = Yes 0x0 No BYPASS = 1 Yes No BYPASS = 1 Yes Texas Instruments-Production Data BYPASS = 1, OSCSRC = 0x1 BYPASS = 1, OSCSRC = 0x2 BYPASS = 1, OSCSRC = 0x0 BYPASS = 1, OSCSRC = 0x3 BYPASS = 1, OSCSRC2 = 0x7 January 09, 2011 ...

  • Page 169

    ... Table 5-3 shows how the SYSDIV encoding affects the system clock frequency, January 09, 2011 PWMDW a XTAL b PLL ÷ 2 SYSDIV b,d BYPASS b,d ÷ 25 ÷ 50 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller a USEPWMDIV a PWM Clock a,d USESYSDIV System Clock b,d PWRDN ADC Clock CAN Clock 169 ...

  • Page 170

    ... MHz Clock source frequency/4 40 MHz Clock source frequency/5 33.33 MHz Clock source frequency/6 28.57 MHz Clock source frequency/7 25 MHz Clock source frequency/8 22.22 MHz Clock source frequency/9 Texas Instruments-Production Data a StellarisWare Parameter b SYSCTL_SYSDIV_1 SYSCTL_SYSDIV_2 SYSCTL_SYSDIV_3 SYSCTL_SYSDIV_4 SYSCTL_SYSDIV_5 SYSCTL_SYSDIV_6 SYSCTL_SYSDIV_7 SYSCTL_SYSDIV_8 SYSCTL_SYSDIV_9 ...

  • Page 171

    ... The modes are programmed using the RCC/RCC2 register fields (see page 184 and page 188). January 09, 2011 Frequency Frequency (BYPASS2=1) (BYPASS2=0) 20 MHz Clock source frequency/10 ... ... 3.125 MHz Clock source frequency/64 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller a StellarisWare Parameter SYSCTL_SYSDIV_10 ... SYSCTL_SYSDIV_64 171 ...

  • Page 172

    ... Run mode. See “Power Management” on page 81 for more details. 172 requirement. The counter is clocked by the main READY READY time met), after which it changes to the PLL. Software READY Texas Instruments-Production Data (see Table READY condition is met after one of the two January 09, 2011 ...

  • Page 173

    ... SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. January 09, 2011 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 173 ...

  • Page 174

    ... Run Mode Clock Gating Control Register 2 0x00000040 Sleep Mode Clock Gating Control Register 0 0x00000000 Sleep Mode Clock Gating Control Register 1 0x00000000 Sleep Mode Clock Gating Control Register 2 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 Texas Instruments-Production Data See page 176 191 193 194 196 198 ...

  • Page 175

    ... All addresses given are relative to the System Control base address of 0x400F.E000. January 09, 2011 Reset Description 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 0x0780.0000 Deep Sleep Clock Configuration Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller See page 211 218 190 175 ...

  • Page 176

    ... MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x1 Stellaris® Fury-class devices. Texas Instruments-Production Data CLASS ...

  • Page 177

    ... MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 177 ...

  • Page 178

    ... This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 179

    ... VADJ field are provided below. Value V (V) OUT 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ). OUT VADJ R/W R/W R/W R/W ...

  • Page 180

    ... An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 181

    ... If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 182

    ... BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 183

    ... When set, indicates a brown-out reset is the cause of the reset event. R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 184

    ... RCC2 register is used as the system clock divider rather than the SYSDIV field in this register Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data ...

  • Page 185

    ... Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller Crystal Frequency (MHz) Using the PLL 1.000 reserved reserved 2.000 reserved reserved 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz 5 ...

  • Page 186

    ... R/W 0 Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. R/W 1 Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). Texas Instruments-Production Data January 09, 2011 ...

  • Page 187

    ... RO - PLL F Value This field specifies the value supplied to the PLL’s F input PLL R Value This field specifies the value supplied to the PLL’s R input. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 188

    ... R/W 1 Power-Down PLL When set, powers down the PLL Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data reserved ...

  • Page 189

    ... Reserved 0x6 Reserved 0x7 32 kHz 32.768-kHz external oscillator RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 189 ...

  • Page 190

    ... Reserved 0x5 Reserved 0x6 Reserved 0x7 32 kHz Use 32.768-kHz external oscillator as source. RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data reserved ...

  • Page 191

    ... Value Description 0xE7 LM3S6611 RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin or 108-ball package Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller PARTNO ...

  • Page 192

    ... This bit specifies whether the device is RoHS-compliant indicates the part is RoHS-compliant Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified Texas Instruments-Production Data January 09, 2011 ...

  • Page 193

    ... Type Reset Description RO 0x007F SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x007F SRAM RO 0x003F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x003F 128 KB of Flash Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller ...

  • Page 194

    ... RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. Texas Instruments-Production Data ...

  • Page 195

    ... When set, indicates that the Serial Wire Output (SWO) trace port is present SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present JTAG Present When set, indicates that the JTAG debugger interface is present. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 195 ...

  • Page 196

    ... RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation I2C Module 1 Present When set, indicates that I2C module 1 is present. Texas Instruments-Production Data TIMER3 TIMER2 ...

  • Page 197

    ... RO 1 UART2 Present When set, indicates that UART module 2 is present UART1 Present When set, indicates that UART module 1 is present UART0 Present When set, indicates that UART module 0 is present. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 197 ...

  • Page 198

    ... RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. Texas Instruments-Production Data reserved RO RO ...

  • Page 199

    ... When set, indicates that the analog comparator 0 (-) input pin is present Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Texas Instruments-Production Data Stellaris® LM3S6611 Microcontroller 199 ...

  • Page 200

    ... When set, indicates that GPIO Port F is present GPIO Port E Present When set, indicates that GPIO Port E is present GPIO Port D Present When set, indicates that GPIO Port D is present GPIO Port C Present When set, indicates that GPIO Port C is present. Texas Instruments-Production Data ...