DS80C320-QCG+T&R Maxim Integrated Products, DS80C320-QCG+T&R Datasheet
DS80C320-QCG+T&R
Specifications of DS80C320-QCG+T&R
Related parts for DS80C320-QCG+T&R
DS80C320-QCG+T&R Summary of contents
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... Four 8-Bit I/O Ports Three 16-Bit Timer/Counters 256 Bytes Scratchpad RAM Addresses 64kB ROM and 64kB RAM High-Speed Architecture 4 Clocks/Machine Cycle (8032 = 12 33MHz (DS80C320 18MHz (DS80C323) Single-Cycle Instruction in 121ns Uses Less Power for Equivalent Work Dual Data Pointer Optional Variable Length MOVX to Access Fast/Slow RAM/Peripherals ...
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... As a result, every 8051 instruction is executed between 1.5 and 3 times faster than the original for the same crystal speed. Typical applications see a speed improvement of 2.5 times using the same code and same crystal. The DS80C320 offers a maximum crystal rate of 33MHz, resulting in apparent execution speeds of 82.5MHz (approximately 2 ...
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... XTAL1 PSEN DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers +5V (+3V for DS80C323) CC Digital Circuit Ground Reset Input. The RST input pin contains a Schmitt voltage input to recognize external active-high reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wired OR external reset sources not required for power-up, as the device provides this function internally ...
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... P1.0–P1.7 1–3 DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers FUNCTION Address Latch-Enable Output. This pin functions as a clock to latch the external address LSB from the multiplexed address/data bus. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles ...
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... DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers NAME Port 2, Output. Port 2 serves as the MSB for external addressing. P2.7 is A15 and P2.0 is A8. The device will automatically place the MSB of an address on P2 for external ROM and RAM access. Although Port 2 can be accessed like an ordinary I/O port, the value stored on the Port 2 latch will never be seen on the pins (due to memory access) ...
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... It may be necessary to use memories with faster access times if the same crystal frequency is used. Application Note 57: DS80C320 Memory Interface Timing is a useful tool to help the embedded system designer select the proper memories for her or his application. ...
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... In this updated core, dummy memory cycles have been eliminated conventional 80C32, machine cycles are generated by dividing the clock frequency by 12. In the DS80C320/DS80C323, the same machine cycle is performed in 4 clocks. Thus the fastest instruction, one machine cycle, is executed three times faster for the same crystal frequency ...
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... This is because in most cases, the DS80C320/DS80C323 use one cycle for each byte. The user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes ...
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... ANL direct ANL direct, #data 3 ORL ORL A, direct 2 ORL A, @Ri 1 ORL A, #data 2 ORL direct ORL direct, #data 3 DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers SYMBOL bit direct bit-address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address OSCILLATOR INSTRUCTION CYCLES 4 ...
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... AJMP addr 11 2 LJMP addr 16 3 SJMP rel 2 JMP @A+DPTR 1 JZ rel 2 JNZ rel 2 DJNZ Rn, rel 2 DJNZ direct, rel 3 *User selectable. DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers OSCILLATOR INSTRUCTION CYCLES MOVC A, 4 @A+DPTR 8 MOVC A, @A+PC 4 MOVX A, @Ri 8 MOVX A, @DPTR 4 MOVX @Ri MOVX @DPTR PUSH direct ...
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... Average: 2.5 MEMORY ACCESS The DS80C320/DS80C323 do not contain on-chip ROM and 256 bytes of scratchpad RAM. Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. Figure 3 shows a typical memory connection. Timing diagrams are provided in the Electrical Specifications section ...
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... STRETCH MEMORY CYCLE The DS80C320/DS80C323 allow the application software to adjust the speed of data memory access. The microcontroller is capable of performing the MOVX in as little as two instruction cycles. However, this value can be stretched as needed so that both fast memory and slow memory or peripherals can be accessed with no glue logic ...
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... Sample code listed below illustrates the saving from using the dual DPTR. The example program was original code written for an 8051 and requires a total of 1869 DS80C320/DS80C323 machine cycles. This takes 299s to execute at 25MHz. The new code using the Dual DPTR requires only 1097 machine cycles taking 175.5 ...
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... DJNZ R5, MOVE PERIPHERAL OVERVIEW Peripherals in the DS80C320/DS80C323 are accessed using the SFRs. The devices provide several of the most commonly needed peripheral functions in microcomputer-based systems. These functions are new to the 80C32 family and include a second serial port, power-fail reset, power-fail interrupt, and a programmable watchdog timer. These are briefly described in the following paragraphs. More details are available in the High-Speed Microcontroller User’ ...
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... WATCHDOG TIMER For applications that cannot afford to run out of control, the DS80C320/DS80C323 incorporate a programmable watchdog timer circuit. The watchdog timer circuit resets the microcontroller if software fails to reset the watchdog before the selected time interval has elapsed. The user selects one of four timeout values ...
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... Finally, the Watchdog Interrupt is enabled using EWDI (EIE.4). INTERRUPTS The DS80C320/DS80C323 provide 13 sources of interrupt with three priority levels. The Power-fail Interrupt (PFI), if enabled, always has the highest priority. There are two remaining user-selectable priorities: high and low. If two interrupts that have the same priority occur simultaneously, the natural precedence given in Table 4 determines which is acted upon ...
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... Idle mode itself, but the watchdog timer. As mentioned above, the Watchdog Timer provides an optional interrupt capability. This interrupt can provide a periodic interval timer to bring the DS80C320/DS80C323 out of Idle mode. This can be useful even if the Watchdog is not normally used. By enabling the Watchdog Timer and its interrupt prior to invoking Idle, a user can periodically come out of Idle perform an operation, then return to Idle until the next operation ...
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... For a 3.57MHz crystal, this is approximately 18ms. The processor sets a flag called RGMD - Ring Mode to tell software that the ring is being used. This bit at EXIF.2 will be logic 1 when the ring is in use. No serial communication or precision timing should be attempted while this bit is set, since the operating frequency is not precise. DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers ...
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... The protected bits are: EXIF.0 BGS Bandgap Select WDCON.6 POR Power-on Reset flag WDCON.1 EWT Enable Watchdog WDCON.0 RWT Reset Watchdog WDCON.3 WDIF Watchdog Interrupt Flag DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers ...
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... SPECIAL-FUNCTION REGISTERS Most special features of the DS80C320/DS80C323 or 80C32 are controlled by bits in the SFRs, allowing the devices to add many features but use the same instruction set. When writing software to use a new feature, the SFR must be defined to an assembler or compiler using an equate statement. This is the only change needed to access the new function ...
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... OH Output High Voltage Ports -1.5mA OH Output-High Voltage Ports 0, 2, ALE -8mA OH Input Low Current Ports 0.45V Transition Current from Ports Input Leakage Port 0, Bus Mode RST Pulldown Resistance DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers SYMBOL MIN V 4 4.25 PFW V 4.0 RST IDLE ...
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... Not a high-impedance input. This port is a weak address holding latch because Port dedicated as an address bus on the DS80C320. Peak current occurs near the input transition point of the latch, approximately 2V. 10. Over the industrial temperature range, this specification has a maximum value of 200A. ...
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... Instruction In Low to Address Float PSEN NOTES FOR DS80C320 AC ELECTRICAL CHARACTERISTICS All parameters apply to both commercial and industrial temperature operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency > ...
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... High to ALE RD WR High Note time period related to the Stretch memory cycle selection. The following table shows the value of MCS t for each Stretch selection. MCS DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers VARIABLE CLOCK SYMBOL MIN 2t -11 CLCL t RLRH t -11 MCS 2t -11 CLCL t WLWH t -11 ...
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... Idle mode current is measured with an 18MHz clock source driving XTAL1, V disconnected. 4. Stop mode current measured with XTAL1 and RST grounded When addressing external memory. This specification only applies to the first clock cycle following the transition. DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers SYMBOL MIN TYP V 2 ...
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... This is only the current required to hold the low level; transitions from I/O pin will also have to overcome the transition current. 12. Device operating range is 2.7V to 5.5V, however device is tested to 2.5V to ensure proper operation at minimum V . RST DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers - 0.3V. Not a high-impedance input. This port is a weak address latch because ...
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... Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change with the duty cycle variations. 5. Address is held in a weak latch until over-driven by external memory. DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 18 MHz SYMBOL MIN MAX ...
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... High ALE High Note time period related to the Stretch memory cycle selection. The following table shows the value of MCS t for each Stretch selection. MCS DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers VARIABLE CLOCK SYMBOL MIN 2t -11 CLCL t RLRH t -11 MCS 2t -11 CLCL t WLWH t -11 MCS ...
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... For completeness, the following is an explanation of the symbols. t Time A Address C Clock D Input data H Logic level high L Logic level low I Instruction P PSEN DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers SYMBOL MIN TYP t 10 CHCX t 10 CLCX t CLCH t CHCL CONDITIONS SM2 = 0; 12 clocks per cycle SM2 = 1 ...
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... Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox crystal. 2. Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 input meets the V PROGRAM MEMORY READ CYCLE DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers SYMBOL MIN TYP t 1.8 ...
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... DATA MEMORY READ CYCLE DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers ...
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... DATA MEMORY WRITE CYCLE DATA MEMORY WRITE WITH STRETCH = 1 DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers ...
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... DATA MEMORY WRITE WITH STRETCH = 2 EXTERNAL CLOCK DRIVE DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 4-CYCLE DATA MEMORY WRITE STRETCH VALUE = ...
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... SERIAL PORT MODE 0 TIMING DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2 = 1 ≥ TXD CLOCK = XTAL/4 SERIAL PORT 0 (SYNCHRONOUS MODE) SM2 = 0 ≥ TXD CLOCK = XTAL/ ...
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... POWER-CYCLE TIMING DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers ...
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... PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE 44 TQFP C44+2 44 MQFP M44+10 44 MQFP M44+5 40 PDIP P40+1 44 PLCC Q44+1 DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers DOCUMENT NO. 21-0293 21-0269 21-0826 21-0044 21-0049 ...
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... The following represent the key differences between the 103196 and the 041896 version of the DS80C320 data sheet. Please review this summary carefully. 1. Updated DS80C320 25MHz AC Characteristics. The following represent the key differences between the 041895 and the 031096 version of the DS80C320 data sheet. Please review this summary carefully. 1. Remove Port 0, Port 2 from V 2 ...
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... DATA SHEET REVISION SUMMARY (continued) The following represent the key differences between the 05/22/96 and the 10/21/97 version of the DS80C320 data sheet. Please review this summary carefully. DS80C320 1. Added note to clarify I specification Added note to clarify AC timing conditions. 3. Corrected erroneous t label on figure “Serial Port Mode 0 Timing” to read t QVXL 4 ...