UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet

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UPD70F3451GC-UBT-A

Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3451GC-UBT-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website: http://www.renesas.com
Old Company Name in Catalogs and Other Documents
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for UPD70F3451GC-UBT-A

UPD70F3451GC-UBT-A Summary of contents

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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User’s Manual V850E/IF3, V850E/IG3 32-bit Single-Chip Microcontrollers Hardware V850E/IF3: μ PD70F3451 μ PD70F3452 V850E/IG3: μ PD70F3453 μ PD70F3454 Document No. U18279EJ3V0UD00 (3rd edition) Date Published March 2010 N 2007 Printed in Japan ...

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User’s Manual U18279EJ3V0UD ...

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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, ...

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Caution: This product uses SuperFlash EEPROM is a trademark of NEC Electronics Corporation. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America. SuperFlash is a registered trademark ...

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Readers This manual is intended for users who wish to understand the functions of the V850E/IF3 μ ( PD70F3451, 70F3452) and V850E/IG3 ( application systems using the V850E/IF3 and V850E/IG3. Purpose This manual is intended to give users an understanding ...

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The mark “<R>” shows major revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Find what:” field. Conventions Data significance: Active low representation: xxx (overscore over pin ...

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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850E/IF3 and V850E/IG3 V850E1 Architecture User’s Manual V850E/IF3, V850E/IG3 Hardware User’s Manual V850E/IF3, V850E/IG3 Sample Programs ...

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Documents related to development tools (user’s manuals) QB-V850EIX3 In-Circuit Emulator QB-V850MINI On-Chip Debug Emulator QB-MINI2 On-Chip Debug Emulator with Programming Function QB-Programmer Programming GUI CA850 Ver. 3.20 C Compiler Package PM+ Ver. 6.30 Project Manager ID850QB Ver. 3.40 Integrated Debugger ...

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CHAPTER 1 INTRODUCTION .................................................................................................................20 1.1 Overview ....................................................................................................................................20 1.2 V850E/IF3 ...................................................................................................................................22 1.2.1 Features (V850E/IF3).................................................................................................................. 22 1.2.2 Application fields (V850E/IF3) ..................................................................................................... 24 1.2.3 Ordering information (V850E/IF3) ............................................................................................... 24 1.2.4 Pin configuration (V850E/IF3) ..................................................................................................... 25 1.2.5 Function blocks (V850E/IF3) ....................................................................................................... 27 1.3 V850E/IG3...................................................................................................................................30 ...

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V850E/IG3 ...................................................................................................................................98 4.2 Port Configuration.....................................................................................................................99 4.2.1 V850E/IF3....................................................................................................................................99 4.2.2 V850E/IG3 .................................................................................................................................100 4.3 Port Configuration.................................................................................................................. 101 4.3.1 Port 0.........................................................................................................................................106 4.3.2 Port 1.........................................................................................................................................113 4.3.3 Port 2.........................................................................................................................................119 4.3.4 Port 3.........................................................................................................................................125 4.3.5 Port 4.........................................................................................................................................131 4.3.6 Port 7.........................................................................................................................................137 4.3.7 Port DL ......................................................................................................................................139 4.4 Output Data ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) ..............................................................294 7.1 Overview ..................................................................................................................................294 7.2 Functions .................................................................................................................................294 7.3 Configuration ..........................................................................................................................295 7.4 Registers..................................................................................................................................297 7.5 Timer Output Operations .......................................................................................................312 7.6 Operation .................................................................................................................................313 7.6.1 Interval timer mode (TABnMD2 to TABnMD0 bits = 000).......................................................... 321 7.6.2 External ...

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System outline ...........................................................................................................................562 10.4.2 Dead-time control (generation of negative-phase wave signal) .................................................567 10.4.3 Interrupt culling function.............................................................................................................574 10.4.4 Operation to rewrite register with transfer function ....................................................................581 10.4.5 TAAn tuning operation for A/D conversion start trigger signal output ........................................599 10.4.6 A/D ...

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Configuration ..........................................................................................................................688 13.3 Control Registers....................................................................................................................691 13.4 Operation .................................................................................................................................697 13.4.1 Basic operation.......................................................................................................................... 697 13.4.2 Trigger mode ............................................................................................................................. 699 13.4.3 Operation mode......................................................................................................................... 700 13.5 Operation in Software Trigger Mode.....................................................................................707 13.6 Internal Equivalent Circuit .....................................................................................................711 13.7 Cautions...................................................................................................................................713 13.8 How to Read A/D ...

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Control Flow ........................................................................................................................... 793 15.10 Cautions .................................................................................................................................. 804 CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)............................................................... 806 16.1 Mode Switching Between CSIB and Other Serial Interface ............................................... 806 16.1.1 Mode switching between CSIB0 and UARTA0 ..........................................................................806 16.1.2 Mode switching between ...

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Operation without communication ............................................................................................. 894 17.7.5 Arbitration loss operation (operation as slave after arbitration loss) .......................................... 895 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss)..................... 897 17.8 Interrupt Request Signal (INTIIC) Generation Timing and Wait Control ...

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DMA source address registers (DSA0 to DSA3)..............................................................961 19.3.2 DMA destination address registers (DDA0 to DDA3).......................................................963 19.3.3 DMA transfer count registers (DBC0 to DBC3)................................................................965 19.3.4 DMA addressing control registers 0 to ...

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Periods in Which CPU Does Not Acknowledge Interrupts ...............................................1024 20.10 Caution...................................................................................................................................1024 CHAPTER 21 STANDBY FUNCTION.................................................................................................1025 21.1 Overview ................................................................................................................................1025 21.2 Control Registers..................................................................................................................1027 21.3 HALT Mode ............................................................................................................................1029 21.3.1 Setting and operation status.................................................................................................... 1029 21.3.2 Releasing HALT mode ............................................................................................................ 1029 21.4 IDLE ...

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Debugging Without Using DCU .......................................................................................... 1059 26.2.1 Circuit connection examples....................................................................................................1059 26.2.2 Maskable functions..................................................................................................................1062 26.2.3 Securing of user resources......................................................................................................1062 26.2.4 Cautions ..................................................................................................................................1068 26.3 ROM Security Function ....................................................................................................... 1069 26.3.1 Security ID ...............................................................................................................................1069 26.3.2 Setting .....................................................................................................................................1070 CHAPTER 27 FLASH MEMORY ........................................................................................................ ...

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Characteristics of A/D converters 0 and 1 ............................................................................... 1116 28.1.10 Characteristics of A/D converter 2........................................................................................... 1117 28.1.11 Operational amplifier characteristics ....................................................................................... 1118 28.1.12 Comparator characteristics...................................................................................................... 1119 28.1.13 Power-on-clear circuit (POC)................................................................................................... 1120 28.1.14 Low-voltage detector (LVI) ...................................................................................................... 1121 28.1.15 Flash ...

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The V850E/IF3 and V850E/IG3 are products of the NEC Electronics V850 single-chip microcontrollers. This chapter gives an outline of the V850E/IF3 and V850E/IG3. 1.1 Overview The V850E/IF3 and V850E/IG3 are 32-bit single-chip microcontrollers that use the V850E1 CPU core and ...

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Table 1-2 shows the differences in functions between the V850E/IF3 and V850E/IG3. Table 1-2. Differences in Functions Between V850E/IF3 and V850E/IG3 Item Port function I/O Input On-chip pull-up resistor Interrupt source External bus function Timers AA0 to AA4 Timers T0, ...

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V850E/IF3 1.2.1 Features (V850E/IF3) Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 ...

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Timer/counter function: 16-bit interval timer M (TMM): 4 channels 16-bit timer/event counter AA (TAA): 5 channels 16-bit timer/event counter AB (TAB): 2 channels 16-bit timer/event counter T (TMT): 2 channels Motor control function (uses timer TAB: 2 channels (TAB0, TAB1), ...

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Application fields (V850E/IF3) • Consumer equipment (such as inverter air conditioners, washing machines, driers, refrigerators, etc.) • Industrial equipment (such as motor control, general-purpose inverters, etc.) 1.2.3 Ordering information (V850E/IF3) Part Number μ PD70F3451GC-UBT-A μ PD70F3452GC-UBT-A Remark The V850E/IF3 ...

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Pin configuration (V850E/IF3) • 80-pin plastic LQFP (14 × 14) μ PD70F3451GC-UBT-A μ PD70F3452GC-UBT-A PDL4 61 PDL3 62 PDL2 63 PDL1 64 PDL0 SS1 REGC1 DD1 P01/TOA21/TIA21/INTP01 69 P00/TOA20/TIA20/TOA2OFF/INTP00 70 P17/TOB00/INTP09 71 P16/TOB0OFF/INTP08/ADTRG0/INTADT0 ...

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Pin Identification (V850E/IF3) ADTRG0, ADTRG1: A/D trigger input ANI00 to ANI05, ANI10 to ANI17, ANI20 to ANI23: Analog input Analog power supply DD0 DD2 Analog reference voltage REFP0 VREFP1 ...

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Function blocks (V850E/IF3) (1) Internal block diagram INTP00, INTP01, INTP08 to INTP18 TIA20, TIA21, TIA40, TIA41, TOA2OFF TOA20, TOA21, TOA40, TOA41 TIB00 to TIB03, TIB10 to TIB13, EVTB0, EVTB1, TRGB0, TRGB1, TOB0OFF, TOB1OFF TOB00 to TOB03, TOB10 to TOB13, ...

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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (32 bits × ...

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Timer/counter The V850E/IF3 incorporates four 16-bit interval timer M (TMM) channels, five 16-bit timer/event counter AA (TAA) channels, two 16-bit timer/event counter AB (TAB) channels, and two 16-bit timer/event counter T (TMT) channels, and can measure pulse interval widths ...

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V850E/IG3 1.3.1 Features (V850E/IG3) Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 ...

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DMA controller: 4 channels Transfer unit: Maximum transfer count: 65,536 (2 Transfer type: Transfer mode: Transfer target: Transfer request: Next address setting function I/O lines: Total: 64 (input ports: 8, I/O ports: 56) Timer/counter function: 16-bit interval timer M (TMM): ...

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Power-save function: HALT/IDLE/STOP mode Power-on-clear function Low-voltage detection function 100-pin plastic LQFP (fine pitch) (14 × 14) Package: 100-pin plastic LQFP (14 × 20) 161-pin plastic FBGA (10 × 10) Operation supply voltage: V DD0 (when A/D converter 0, 1 ...

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Pin configuration (V850E/IG3) • 100-pin plastic LQFP (fine pitch) (14 × 14) μ PD70F3453GC-8EA-A μ PD70F3454GC-8EA-A Note PDL5/AD5 /FLMD1 Note PDL4/AD4 Note PDL3/AD3 Note PDL2/AD2 Note PDL1/AD1 Note PDL0/AD0 P06/TENC01/TIT01/TOT01/INTP06 P05/TENC00/EVTT0/INTP05 P04/TECR0/TIT00/TOT00/INTP04 V SS1 REGC1 V DD1 P03/TOA31/TIA31/INTP03 P02/TOA30/TIA30/TOA3OFF/INTP02 ...

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LQFP (14 × 20) μ PD70F3453GF-GAS-AX μ PD70F3454GF-GAS-AX P46/TOA40/TIA40/INTP17 81 P47/TOA41/TIA41/INTP18 82 83 P30/RXDA1/SCL P31/TXDA1/SDA 84 P32/SIB1/RXDA2 85 P33/SOB1/TXDA2 86 87 P34/SCKB1/INTP11 P35/SIB2/RXDB 88 P36/SOB2/TXDB 89 P37/SCKB2/INTP12 90 P07/INTP07 SS0 EV 93 DD0 94 ...

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FBGA (10 × 10) μ PD70F3454F1-DA9-A Top View Index mark Pin No. Name A1 EV SS1 A2 IC1 A3 EV DD1 A4 P12/TOB0T2/TIB03/TOB03/A2 ...

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Pin No. Name F11 IC1 F12 PDL15/AD15 F13 EV DD0 F14 EV DD0 G1 AV DD1 G2 AV REFP1 G3 ANI13/CREF1L G4 ANI14/CREF1F G11 IC1 G12 P07/INTP07/CLKOUT G13 EV SS0 G14 EV SS0 H1 AV SS1 H2 AV SS1 H3 ...

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Pin Identification (V850E/IG3 A7: Address bus AD0 to AD15: Address/data bus ADTRG0, ADTRG1: A/D trigger input ANI00 to ANI05, ANI10 to ANI17, ANI20 to ANI27: Analog input ASTB: Address strobe Analog power supply DD0 ...

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Function blocks (V850E/IG3) (1) Internal block diagram INTC INTP00 to INTP18 TMM × 4 channels TIA20, TIA21, TIA30, TIA31, TIA40, TIA41, TOA2OFF, TOA3OFF × 5 channels TOA20, TOA21, TOA30, TOA31, TOA40, TOA41 TIB00 to TIB03, TIB10 to TIB13, EVTB0, ...

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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (32 bits × ...

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Interrupt controller (INTC) This controller handles hardware interrupt requests (INTP00 to INTP18, INTADT0, INTADT1) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple-interrupt servicing control can be ...

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Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O Port 0 8-bit I/O Timer/counter I/O, external interrupt input, external bus interface control signal output Port 1 8-bit I/O Timer/counter I/O, external ...

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The names and functions of the pins in the V850E/IF3 and V850E/IG3 are listed below. These pins can be divided into port pins and non-port pins according to their function. 2.1 List of Pin Functions There are two power supplies ...

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Port pins Pin Name Pin No. I/O IF3 IG3 P00 I/O Port 0 P01 − Note 1 P02 − Note 1 P03 88 16 ...

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Pin Name Pin No. I/O IF3 IG3 P20 I/O Port 2 8-bit I/O port P21 Input data read/output data write is P22 enabled in ...

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Pin Name Pin No. I/O IF3 IG3 P70 Input Port 7 P71 P72 P73 − Note 1 P74 21 49 ...

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Non-port pins Pin Name Pin No. I/O IF3 IG3 − − Note Output 8-bit address bus for external memory − − Note − − Note 1 A2 ...

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Pin Name Pin No. I/O IF3 IG3 ANI00 Input ANI01 ANI02 ANI03 ANI04 ANI05 1 2 ...

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Pin Name Pin No. IF3 IG3 E1, E2 SS0 H1, H2 SS1 Note 1 SS2 − − Note 2 CLKOUT 63 G12 Output CREF0L ...

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Pin Name Pin No. I/O IF3 IG3 − Note 1 EVTT0 Input EVTT1 L14 FLMD0 Input FLMD1 A12 − − − − Note ...

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Pin Name Pin No. I/O IF3 IG3 − − Note K14 Output − REGC0 N6, P6 REGC1 A8, B8 RESET Input RXDA0 38 ...

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Pin Name Pin No. I/O IF3 IG3 TIA21 Input − Note 2 TIA30 Input − Note 2 TIA31 TIA40 L12 Input TIA41 45 ...

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Pin Name Pin No. I/O IF3 IG3 TOB00 Output Timer output of TAB0 TOB01 TOB02 TOB03 TOB0B1 ...

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Pin Name Pin No. I/O IF3 IG3 TRGB0 Input TRGB1 TXDA0 N12 Output TXDA1 K12 TXDA2 J13 TXDB 52 ...

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Pin Status The operation statuses of pins in the various operation modes are described below. Table 2-2. Pin Operation Status in Operation Modes Operating Status Pin Note 1 Note 2 AD0 to AD15 (PDL0 to Hi-Z PDL15) Note 1 ...

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Pin I/O Circuits and Recommended Connection of Unused Pins It is recommended that kΩ resistors be used when connecting to AV only (V850E/IG3 only) via resistors. SS0 SS1 SS2 Pin ...

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Pin Alternate-Function Pin Name P30 RXDA1/SCL P31 TXDA1/SDA Note 1 P32 SIB1/RXDA2/CS1 P33 SOB1/TXDA2 Note 1 P34 SCKB1/INTP11/CS0 P35 SIB2/RXDB P36 SOB2/TXDB Note 1 P37 SCKB2/INTP12/ASTB P40 SIB0/RXDA0 Note 2 P41 SOB0/TXDA0/DCK Note 2 P42 SCKB0/INTP13/DDI P43 TECR1/TIT10/TOT10/INTP14 P44 TENC10/EVTT1/INTP15/WAIT ...

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Pin Alternate-Function Pin Name Note 1 PDL4 AD4 Note 1 PDL5 AD5 /FLMD1 Note 1 PDL6 AD6 Note 1 PDL7 AD7 Note 1 PDL8 AD8 Note 1 PDL9 AD9 Note 2 Note 1 PDL10 AD10 Note 2 Note 1 PDL11 ...

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Pin Alternate-Function Pin Name − Note 1 DDO − Note 1 DRST − FLMD0 − Note 2 IC0 − Note 2 IC1 − Note 2 IC2 − RESET Notes 1. V850E/IG3 only μ 2. PD70F3454F1-DA9-A only 3. A2, A13, B13, ...

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Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 2-M IN Note SS0 SS1 SS2 Type 3 DD0 DD1 Data SS0 SS1 EV Type 5-AG ...

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The CPU of the V850E/IF3 and V850E/IG3 is based on RISC architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 Features Minimum instruction execution time: 15 MHz internal operation) Thirty-two ...

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CPU Register Set The registers of the V850E/IF3 and V850E/IG3 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have a 32-bit width. For details, refer to V850E1 ...

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Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used as a data variable ...

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System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). System Register ...

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Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the ...

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NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the ...

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Program status word (PSW) The program status word (PSW collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the ...

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Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation ...

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Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and ...

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Operating Modes 3.3.1 Operating modes The V850E/IF3 and V850E/IG3 have the following operating modes. Mode specification is carried out using the FLMD0 and FLMD1 pins. (1) Normal operation mode In this mode, execution branches to the reset entry address ...

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Address Space 3.4.1 CPU address space The CPU of the V850E/IF3 and V850E/IG3 has 32-bit architecture and supports linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a ...

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Image A 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits ...

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Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow ...

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Memory map The V850E/IF3 and V850E/IG3 reserve areas as shown in Figure 3-4. μ PD70F3452 (V850E/IF3) μ PD70F3454 (V850E/IG3 On-chip peripheral I/O area ...

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Area (1) Internal ROM area internal ROM area, addresses 00000H to FFFFFH, is reserved. μ (a) PD70F3451 (V850E/IF3), 128 KB are provided at addresses 000000H to 01FFFFH as physical internal ROM. μ (b) PD70F3452 (V850E/IF3), 256 ...

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Internal RAM area The 12 KB area of addresses FFFC000H to FFFEFFFH is reserved for the internal RAM area. μ μ (a) PD70F3451 (V850E/IF3), The 8 KB area of addresses FFFC000H to FFFDFFFH is provided as physical internal RAM. ...

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On-chip peripheral I/O area memory, addresses FFFF000H to FFFFFFFH, is provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFH Note Addresses 3FFF000H to ...

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Recommended use of address space The architecture of the V850E/IF3 and V850E/IG3 requires that a register that serves as a pointer be secured for address generation in operand data accessing of data space. Operand data access from instruction can ...

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Figure 3-10. Recommended Memory Map Program space ...

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On-chip peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DLL register FFFFF005H Port DLH register FFFFF024H Port DL mode register FFFFF024H Port DL mode register L FFFFF025H Port DL mode register H FFFFF044H Port ...

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Address Function Register Name FFFFF100H Interrupt mask register 0 FFFFF100H Interrupt mask register 0L FFFFF101H Interrupt mask register 0H FFFFF102H Interrupt mask register 1 FFFFF102H Interrupt mask register 1L FFFFF103H Interrupt mask register 1H FFFFF104H Interrupt mask register 2 FFFFF104H ...

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Address Function Register Name FFFFF13CH Interrupt control register FFFFF13EH Interrupt control register FFFFF140H Interrupt control register FFFFF142H Interrupt control register FFFFF144H Interrupt control register FFFFF146H Interrupt control register FFFFF148H Interrupt control register FFFFF14AH Interrupt control register FFFFF14CH Interrupt control register ...

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Address Function Register Name FFFFF18CH Interrupt control register FFFFF18EH Interrupt control register FFFFF190H Interrupt control register FFFFF192H Interrupt control register FFFFF194H Interrupt control register FFFFF196H Interrupt control register FFFFF198H Interrupt control register FFFFF19AH Interrupt control register FFFFF19CH Interrupt control register ...

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Address Function Register Name FFFFF204H A/D0 conversion result register 2 FFFFF205H A/D0 conversion result register 2H FFFFF206H A/D0 conversion result register 3 FFFFF207H A/D0 conversion result register 3H FFFFF208H A/D0 conversion result register 4 FFFFF209H A/D0 conversion result register 4H ...

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Address Function Register Name FFFFF233H A/D converter 0 channel specification register 2 FFFFF240H A/D0 conversion result expansion register 0 FFFFF241H A/D0 conversion result expansion register 0H FFFFF242H A/D0 conversion result expansion register 1 FFFFF243H A/D0 conversion result expansion register 1H ...

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Address Function Register Name FFFFF292H A/D1 conversion result register 9 FFFFF293H A/D1 conversion result register 9H FFFFF294H A/D1 conversion result register 10 FFFFF295H A/D1 conversion result register 10H FFFFF296H A/D1 conversion result register 11 FFFFF297H A/D1 conversion result register 11H ...

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Address Function Register Name FFFFF2E3H Comparator 1 control register 2 FFFFF2E4H Comparator 1 control register 3 FFFFF2F0H A/D trigger falling edge specification register FFFFF2F2H A/D trigger rising edge specification register FFFFF2F4H Comparator output interrupt falling edge specification register FFFFF2F6H Comparator ...

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Address Function Register Name FFFFF554H TMM1 compare register 0 FFFFF560H TMM2 control register 0 FFFFF564H TMM2 compare register 0 FFFFF570H TMM3 control register 0 FFFFF574H TMM3 compare register 0 FFFFF580H TMT0 control register 0 FFFFF581H TMT0 control register 1 FFFFF582H ...

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Address Function Register Name FFFFF5E5H TAB0 option register 0 FFFFF5E6H TAB0 capture/compare register 0 FFFFF5E8H TAB0 capture/compare register 1 FFFFF5EAH TAB0 capture/compare register 2 FFFFF5ECH TAB0 capture/compare register 3 FFFFF5EEH TAB0 counter read buffer register FFFFF600H TAB0 option register 1 ...

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Address Function Register Name FFFFF680H TAA1 control register 0 FFFFF681H TAA1 control register 1 FFFFF685H TAA1 option register 0 FFFFF686H TAA1 capture/compare register 0 FFFFF688H TAA1 capture/compare register 1 FFFFF68AH TAA1 counter read buffer register FFFFF6A0H TAA2 control register 0 ...

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Address Function Register Name FFFFFA07H UARTA0 transmit data register FFFFFA10H UARTA1 control register 0 FFFFFA11H UARTA1 control register 1 FFFFFA12H UARTA1 control register 2 FFFFFA13H UARTA1 option control register 0 FFFFFA14H UARTA1 status register FFFFFA16H UARTA1 receive data register FFFFFA17H ...

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Address Function Register Name FFFFFB24H TAA4 I/O control register 2 FFFFFB25H TAA4 option register 0 FFFFFB26H TAA4 capture/compare register 0 FFFFFB28H TAA4 capture/compare register 1 FFFFFB2AH TAA4 counter read buffer register FFFFFB40H Digital noise elimination 1 control register 2 FFFFFB42H ...

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Address Function Register Name FFFFFC66H Port 3 function register FFFFFD00H CSIB0 control register 0 FFFFFD01H CSIB0 control register 1 FFFFFD02H CSIB0 control register 2 FFFFFD03H CSIB0 status register FFFFFD04H CSIB0 receive data register FFFFFD04H CSIB0 receive data register L FFFFFD06H ...

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Special registers Special registers are registers that are protected from being written with illegal data due to a program loop. The V850E/IF3 and V850E/IG3 have the following five special registers. • Power save control register (PSC) • Processor clock ...

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Setting data to special registers Set data to the special registers in the following sequence. <1> Prepare data to be set to the special register in a general-purpose register. <2> Write the data prepared in <1> to the command ...

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Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program loop. The first ...

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System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. If this register is not written in the correct sequence including an access to the PRCMD register, data is ...

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System wait control register (VSWC) The VSWC register is a register that controls the bus access wait for the on-chip peripheral I/O registers. Access to on-chip peripheral I/O registers of the V850E1 CPU core is basically made in 3 ...

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Features 4.1.1 V850E/IF3 Input-only ports: 4 I/O ports: 44 Input data read/output data write is enabled in 1-bit units. On-chip pull-up resistor can be connected in 1-bit units (ports and DL only). However, an on-chip pull-up ...

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Port Configuration 4.2.1 V850E/IF3 The V850E/IF3 incorporates a total of 48 input/output ports (including 4 input-only ports) labeled ports and DL. The port configuration is shown in Figure 4-1. There are two power supply systems ...

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V850E/IG3 The V850E/IG3 incorporates a total of 64 input/output ports (including 8 input-only ports) labeled ports and DL. The port configuration is shown in Figure 4-2. There are two power supply systems for the I/O ...

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Port Configuration Table 4-3. Port Configuration (V850E/IF3) Item Control registers Port n register (Pn DL) Port n mode register (PMn DL) Port n mode control register (PMCn: n ...

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Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the ...

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Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be ...

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Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. Each bit of this register corresponds to one pin ...

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Port settings Set the ports as follows. Figure 4-3. Register Settings and Pin Functions Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate function (when three or ...

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Port 0 Port 0 can be set to the input or output mode in 1-bit units. The number of I/O pins differs from one product to another. Generic Name V850E/IF3 V850E/IG3 Port 0 has an alternate function as the ...

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CHAPTER 4 PORT FUNCTIONS Cautions 3. To switch to external interrupt input (INTP0n) from the port mode (by changing the PMC0.PMC0n bit from 0 to 1), an external interrupt may be input if a wrong valid edge is detected. Therefore, ...

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Registers (a) Port 0 register (P0) After reset: Undefined Note P0 P07 P06 P0n 0 Output 0. 1 Output 1. Note Valid only for the V850E/IG3. With the V850E/IF3, the read value of this register is undefined. Remark V850E/IF3: ...

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Port 0 mode control register (PMC0) After reset: 00H R/W Note 1 PMC0 PMC07 PMC06 Note 1 PMC07 0 I/O port 1 INTP07 input Note 1 PMC06 0 I/O port 1 TENC01 input Note 1 PMC05 0 I/O port ...

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Port 0 function control register (PFC0) After reset: 00H R/W Note PFC0 PFC07 PFC06 Note Valid only in the V850E/IG3. With the V850E/IF3, be sure to set these bits to 0. Remark For the specifications of alternate functions, see ...

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CHAPTER 4 PORT FUNCTIONS (f) Setting of alternate function of port 0 Note 1 PFC07 0 INTP07 input 1 CLKOUT output Note 1 Note 1 PFCE06 PFC06 0 0 TENC01 input 0 1 TOT01 output 1 0 INTP06 input 1 ...

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PFCE01 PFC01 PFCE00 PFC00 (g) Pull-up resistor option register 0 (PU0) After reset: 00H R/W Note 1 PU0 PU07 PU06 PU0n 0 Do not ...

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Port 1 Port 1 can be set to the input or output mode in 1-bit units. Port 1 has an alternate function as the following pins. Table 4-7. Alternate-Function Pins of Port 1 Pin Name Pin No. IF3 IG3 ...

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Registers (a) Port 1 register (P1) After reset: Undefined P1 P17 P16 P1n 0 Output 0. 1 Output 1. Remark (b) Port 1 mode register (PM1) After reset: FFH R/W PM1 PM17 PM16 PM1n ...

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Port 1 mode control register (PMC1) After reset: 00H R/W PMC1 PMC17 PMC16 PMC17 0 I/O port 1 TOB00 output/INTP09 input/A7 output PMC16 0 I/O port 1 TOB0OFF input/INTP08 input/ADTRG0 input/INTADT0 input/A6 output PMC15 0 I/O port 1 TOB0B3 ...

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Port 1 function control register (PFC1) After reset: 00H R/W PFC1 PFC17 PFC16 Remark For the specifications of alternate functions, see 4.3.2 (1) (f) Settings of alternate functions of port 1. (e) Port 1 function control expansion register (PFCE1) ...

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CHAPTER 4 PORT FUNCTIONS (f) Settings of alternate functions of port 1 PFCE17 PFC17 0 0 TOB00 output 0 1 INTP09 input output 1 1 Setting prohibited PFCE16 PFC16 0 0 TOB0OFF input/INTP08 input (two functions are ...

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PFCE11 PFC11 PFCE10 PFC10 μ Note PD70F3454GC-8EA-A and 70F3454F1-DA9-A only (g) Pull-up resistor option register 1 (PU1) After reset: 00H R/W PU1 PU17 PU16 ...

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Port 2 Port 2 can be set to the input or output mode in 1-bit units. Port 2 has an alternate function as the following pins. Table 4-8. Alternate-Function Pins of Port 2 Pin Name Pin No. IF3 IG3 ...

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Registers (a) Port 2 register (P2) After reset: Undefined P2 P27 P26 P2n 0 Output 0. 1 Output 1. Remark (b) Port 2 mode register (PM2) After reset: FFH R/W PM2 PM27 PM26 PM2n ...

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CHAPTER 4 PORT FUNCTIONS (c) Port 2 mode control register (PMC2) After reset: 00H R/W Address: FFFFF444H PMC2 0 PMC26 PMC26 0 I/O port 1 TOB10 output/TOB1OFF input/INTP10 input/ADTRG1 input/INTADT1 input PMC25 0 I/O port 1 TOB1B3 output/TRGB1 input PMC24 ...

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Port 2 function control register (PFC2) After reset: 00H R/W PFC2 0 PFC26 Remark For the specifications of alternate functions, see 4.3.3 (1) (f) Settings of alternate functions of port 2. (e) Port 2 function control expansion register (PFCE2) ...

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CHAPTER 4 PORT FUNCTIONS (f) Settings of alternate functions of port 2 PFCE26 PFC26 0 0 TOB10 output 0 1 TOB1OFF input/INTP10 input (two functions are alternately used ADTRG1 input/INTADT1 input (two functions are alternately used ...

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Pull-up resistor option register 2 (PU2) After reset: 00H R/W PU2 PU27 PU26 PU2n 0 Do not connect 1 Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port ...

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Port 3 Port 3 can be set to the input or output mode in 1-bit units. Port 3 has an alternate function as the following pins. Table 4-9. Alternate-Function Pins of Port 3 Pin Name Pin No. IF3 IG3 ...

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Registers (a) Port 3 register (P3) After reset: Undefined P3 P37 P36 P3n 0 Output 0. 1 Output 1. Remark (b) Port 3 mode register (PM3) After reset: FFH R/W PM3 PM37 PM36 PM3n ...

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Port 3 mode control register (PMC3) After reset: 00H R/W PMC3 PMC37 PMC36 PMC37 0 I/O port 1 SCKB2 I/O/NTP12 input/ASTB output PMC36 0 I/O port 1 SOB2 output/TXDB output PMC35 0 I/O port 1 SIB2 input/RXDB input PMC34 ...

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Port 3 function control register (PFC3) After reset: 00H R/W PFC3 PFC37 PFC36 Remark For the specifications of alternate functions, see 4.3.4 (1) (f) Settings of alternate functions of port 3. (e) Port 3 function control expansion register (PFCE3) ...

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CHAPTER 4 PORT FUNCTIONS (f) Settings of alternate functions of port 3 PFCE37 PFC37 0 0 SCKB2 input/output 0 1 INTP12 input 1 0 ASTB output 1 1 Setting prohibited PFCE36 PFC36 0 0 SOB2 output 0 1 TXDB output ...

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PFCE31 PFC31 PFCE30 PFC30 (g) Pull-up resistor option register 3 (PU3) After reset: 00H R/W PU3 PU37 PU36 PU3n 0 Do not connect 1 ...

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Port 4 Port 4 can be set to the input or output mode in 1-bit units. Port 4 has an alternate function as the following pins. Table 4-10. Alternate-Function Pins of Port 4 Pin Name Pin No. IF3 IG3 ...

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Registers (a) Port 4 register (P4) After reset: Undefined P4 P47 P46 P4n 0 Output 0. 1 Output 1. Remark (b) Port 4 mode register (PM4) After reset: FFH R/W PM4 PM47 PM46 PM4n ...

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Port 4 mode control register (PMC4) After reset: 00H R/W PMC4 PMC47 PMC46 PMC47 0 I/O port 1 TOA41 output/TIA41 input/INTP18 input/RD output PMC46 0 I/O port 1 TOA40 output/TIA40 input/INTP17 input/WR0 output PMC45 0 I/O port 1 TENC11 ...

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Port 4 function control register (PFC4) After reset: 00H R/W PFC4 PFC47 PFC46 Remark For the specifications of alternate functions, see 4.3.5 (1) (f) Settings of alternate functions of port 4. (e) Port 4 function control expansion register (PFCE4) ...

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CHAPTER 4 PORT FUNCTIONS (f) Settings of alternate functions of port 4 PFCE47 PFC47 0 0 TOA41 output 0 1 TIA41 input 1 0 INTP18 input output PFCE46 PFC46 0 0 TOA40 output 0 1 TIA40 input ...

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PFCE41 PFC41 PFC40 0 1 (g) Pull-up resistor option register 4 (PU4) After reset: 00H PU4 PU47 PU4n 0 Do not connect 1 Connect Note An on-chip pull-up resistor can be connected ...

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Port 7 Port input port with all its pins fixed to the input mode. The number of input port pins differs depending on the product. Generic Name V850E/IF3 V850E/IG3 Port 7 has an alternate function as ...

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Registers (a) Port 7 register (P7) After reset: Undefined Note P7 P77 P76 P7n 0 Input low level. 1 Input high level. Note Valid only in the V850E/IG3. With the V850E/IF3, the read value of this register is undefined. ...

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Port DL Port DL can be set to the input or output mode in 1-bit units. Port DL has an alternate function as the following pins. Table 4-12. Alternate-Function Pins of Port DL Pin Name Pin No, IF3 IG3 ...

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Registers (a) Port DL register (PDL) After reset: Undefined 15 Note 1 Note 2 PDL (PDLH ) PDL15 7 (PDLL) PDL7 PDLn 0 1 Notes 1. To read/write bits the PDL register in 8-bit or ...

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Port DL mode register (PMDL) After reset: FFFFH 15 Note 1 Note 2 PMDL (PMDLH ) PMDL15 7 (PMDLL) PMDL7 PMDLn 0 1 Notes 1. To read/write bits the PMDL register in 8-bit or 1-bit ...

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Port DL mode control register (PMCDL) After reset: 0000H 15 Note 1 PMCDL (PMCDLH ) PMCDL15 7 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Notes 1. To read/write bits the ...

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Pull-up resistor option register DL (PUDL) After reset: 0000H 15 Note 1 Note 2 PUDL (PUDLH ) PUDL15 7 (PUDLL) PUDL7 PUDLn 0 1 Notes 1. To read/write bits the PUDL register in 8-bit or ...

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Output Data and Port Read Value for Each Setting Table 4-14 shows the values used to select the alternate function of the respective pins, output data and port read values for each setting. In addition to the settings shown ...

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Table 4-13. Output Data and Port Read Value for Each Setting (1/12) Port Name Function PMCmn Note P00, P01, P02 , Output port 0 Note P03 Input port TOA20, TOA21, 1 Note Note TOA30 , TOA31 TIA20, TIA21, 1 Note ...

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Table 4-13. Output Data and Port Read Value for Each Setting (2/12) Port Name Function PMCmn Note 1 P05 Output port 0 Input port Note 1 TENC00 1 Note 1 EVTT0 1 Note 1 INTP05 1 Note 1 P07 Output ...

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Table 4-13. Output Data and Port Read Value for Each Setting (3/12) Port Name Function PMCmn P10 to P12 Output port 0 Input port TOB0T1, TOB0B1, 1 TOB0T2 TIB01 to TIB03 1 TOB01 to TOB03 1 Note Note Note A0 ...

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Table 4-13. Output Data and Port Read Value for Each Setting (4/12) Port Name Function PMCmn P16 Output port 0 Input port TOB0OFF/INTP08 1 ADTRG0/INTADT0 1 Note A6 1 P17 Output port 0 Input port TOB00 1 INTP09 1 Note ...

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Table 4-13. Output Data and Port Read Value for Each Setting (5/12) Port Name Function PMCmn P23 to P25 Output port 0 Input port TOB1B2, TOB1T3, 1 TOB1B3 TIB10, EVTB1, 1 TRGB1 P26 Output port 0 Input port TOB10 1 ...

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Table 4-13. Output Data and Port Read Value for Each Setting (6/12) Port Name Function PMCmn P30 Output port 0 Input port RXDA1 1 SCL 1 P31 Output port 0 Input port TXDA1 1 SDA 1 P32 Output port 0 ...

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Table 4-13. Output Data and Port Read Value for Each Setting (7/12) Port Name Function PMCmn P33 Output port 0 Input port SOB1 1 TXDA2 1 P34 Output port 0 Input port SCKB1 1 INTP11 1 Note CS0 1 P35 ...

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Table 4-13. Output Data and Port Read Value for Each Setting (8/12) Port Name Function PMCmn P36 Output port 0 Input port SOB2 1 TXDB 1 P37 Output port 0 Input port SCKB2 1 INTP12 1 Note ASTB 1 P40 ...

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Table 4-13. Output Data and Port Read Value for Each Setting (9/12) Port Name Function PMCmn Note P41 Output port 0 Input port SOB0 1 TXDA0 1 Note P42 Output port 0 Input port SCKB0 1 INTP13 1 Note The ...

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Table 4-13. Output Data and Port Read Value for Each Setting (10/12) Port Name Function PMCmn P43 Output port 0 Input port TECR1/TIT10 1 TOT10 1 INTP14 1 P44 Output port 0 Input port TENC10 1 EVTT1 1 INTP15 1 ...

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Table 4-13. Output Data and Port Read Value for Each Setting (11/12) Port Name Function PMCmn P45 Output port 0 Input port TENC11/TIT11 1 TOT11 1 INTP16 1 Note WR1 1 P46, P47 Output port 0 Input port TOA40, TOA41 ...

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Table 4-13. Output Data and Port Read Value for Each Setting (12/12) Port Name Function PMCmn P70 to P73, Input port 0 Note 1 P74 to P77 ANI20 to ANI23, 1 Note 1 ANI24 to ANI27 PDL0 to PDL9, Output ...

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Port Register Settings When Alternate Function Is Used The following shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P00 TOA20 Output P00 = Setting not required TIA20 Input P00 = Setting not required TOA2OFF Input P00 = Setting not required INTP00 Input P00 = Setting not required ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O Note 1 Note 1 P06 TENC01 Input P06 = Setting not required Note 1 TIT01 Input P06 = Setting not required Note 1 TOT01 Output P06 = Setting not ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P14 TOB0T3 Output P14 = Setting not required EVTB0 Input P14 = Setting not required Note A4 Output P14 = Setting not required P15 TOB0B3 Output P15 = Setting ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P23 TOB1B2 Output P23 = Setting not required TIB10 Input P23 = Setting not required P24 TOB1T3 Output P24 = Setting not required EVTB1 Input P24 = Setting not ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P32 SIB1 Input P32 = Setting not required RXDA2 Input P32 = Setting not required Note CS1 Output P32 = Setting not required P33 SOB1 Output P33 = Setting ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P41 SOB0 Output P41 = Setting not required TXDA0 Output P41 = Setting not required Notes 1, 2 DCK Input P41 = Setting not required P42 SCKB0 I/O P42 ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O P45 TENC11 Input P45 = Setting not required TIT11 Input P45 = Setting not required TOT11 Output P45 = Setting not required INTP16 Input P45 = Setting not required ...

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Pin Name Alternate Pin Pnx Bit of Pn Register Name I/O Note 1 PDL0 AD0 I/O PDL0 = Setting not required Note 1 PDL1 AD1 I/O PDL1 = Setting not required Note 1 PDL2 AD2 I/O PDL2 = Setting not ...

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Noise Eliminator A timing controller used to secure the noise elimination time is provided for the following pins. Input signals that change within the noise elimination time are not internally acknowledged. Target Pin RESET Note 1 DRST FLMD0 P00/TOA20/TIA20/TOA2OFF/INTP00 ...

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Target Pin P16/TOB0OFF/INTP08/ADTRG0/INTADT0/ Note 1 A6 Note 1 P17/TOB00/INTP09/A7 P20/TOB1T1/TIB11/TOB11 P21/TOB1B1/TIB12/TOB12 P22/TOB1T2/TIB13/TOB13 P23/TOB1B2/TIB10 P24/TOB1T3/EVTB1 P25/TOB1B3/TRGB1 P26/TOB10/TOB1OFF/INTP10/ADTRG1/ INTADT1 Note 1 P34/SCKB1/INTP11/CS0 Note 1 P37/SCKB2/INTP12/ASTB Note 2 P42/SCKB0/INTP13/DDI P43/TECR1/TIT10/TOT10/INTP14 Note 1 P44/TENC10/EVTT1/INTP15/WAIT Note 1 P45/TENC11/TIT11/TOT11/INTP16/WR1 Note 1 P46/TOA40/TIA40/INTP17/WR0 Note 1 P47/TOA41/TIA41/INTP18/RD μ ...

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An example of timing of noise elimination by digital filter for INTP14 to INTP16, timer AA input pin, and timer T input pin is shown below. Figure 4-4. Example of Noise Elimination Timing Noise elimination clock Input signal Internal signal ...

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Digital noise elimination 0 control register n (INTNFCn) The INTNFCn register is used to select the sampling clock that is used to eliminate digital noise on the INTPn pin. If the same level is not detected on this pin ...

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Digital noise elimination 1 control register n (TANFCn) The TANFCn register is used to select the sampling clock that is used to eliminate digital noise on the TIAn0 or TIAn1 pin. If the same level is not detected on ...

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Digital noise elimination 2 control register n (TTNFCn) The TTNFCn register is used to select the sampling clock that is used to eliminate digital noise on the TITn0, TITn1, EVTTn, TENCn0, TENCn1, or TECRn pin. If the same level ...

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Cautions 4.7.1 Cautions on setting port pins (1) Set the registers of a port in the following sequence. <1> Set PFCn and PFCEn registers. <2> Set PMCn register. <3> Set INTFn and INTRn registers. If the PMCn register is ...

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Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is ...

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CHAPTER 5 CLOCK GENERATOR 5.1 Overview The features of clock generator are as follows. Oscillator • In PLL mode MHz (f X • In clock-through mode MHz (f X Multiply ...

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Configuration Oscillator PLL X2 Note CLKOUT Port 0 Oscillation stabilization time wait control (OST) μ Note PD70F3454GC-8EA-A and 70F3454F1-DA9-A only Caution Because f and f do not go through PLL immediately after reset, and f CPU ...

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Table 5-1. Operation Clock of Each Function Block Function Block CPU DMA, interrupt controller TAA TAA0, TAA1 TAA2 to TAA4 TAB TMT TMM Watchdog timer UARTA UARTB CSIB Bus control function A/D converters 0, 1 A/D converter ...

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Oscillator The main resonator oscillates the following frequencies (f • In PLL mode (×8 fixed MHz (f X • In clock-through mode MHz (f X (2) IDLE control All ...

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Control Registers The clock generator is controlled by the following six registers. • PLL control register (PLLCTL) • Processor clock control register (PCC) • Power save control register (PSC) • Power save mode register (PSMR) • Oscillation stabilization time ...

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Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit ...

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Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function and specifies the standby mode by setting the STB bit. The PSC register is a special register (see 3.4.8 Special registers). Data ...

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Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation in the software standby mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ...

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Oscillation stabilization time select register (OSTS) The OSTS register selects the oscillation stabilization time until the oscillation stabilizes after the STOP mode is released by interrupt request. This register can be read or written in 8-bit units. Reset sets ...

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Clock monitor mode register (CLM) The CLM register sets clock monitor operation mode. The CLM register is a special register. It can be written only in a combination of specific sequences (see 3.4.8 Special registers). This register can be ...

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PLL Function 5.4.1 Overview The CPU and the operating clock of the peripheral macro can be switched between output of the oscillation frequency multiplied by 8, and clock-through mode. When PLL function is used: Input clock (f Clock-through mode: ...

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Operation 5.5.1 Operation of each clock The following table shows the operation status of each clock. Table 5-2. Operation Status of Each Clock Power Save Mode Normal operation HALT mode IDLE mode In STOP mode and during oscillation stabilization ...

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Operation timing (1) Power on (power-on reset DD0 DD1 RESET (input) <1> OST counter 00H (initialization) PLL output clock Internal reset signal X1 Oscillation stabilization time f CPU <1> The oscillator is activated during the RESET ...

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Reset input with power DD0 DD1 Note <1> Reset OST counter 00H (initialization) PLL output clock Internal reset signal X1 f CPU <1> The oscillator continues operating during the reset period. PLL stops during ...

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When releasing STOP mode by interrupt request DD0 DD1 <1> STOP status In STOP mode OST counter 00H (initialization) PLL output clock X1 f CPU <1> When the STOP mode is set, both the oscillator ...

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Clock Monitor (1) Clock monitor function The clock monitor samples the clock generated by the oscillator, by using the internal oscillation clock. When it detects stop of oscillation, output of the timer for motor control goes into a high-impedance ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer AA (TAA 16-bit timer/event counter. The V850E/IF3 and V850E/IG3 incorporate TAA0 to TAA4. 6.1 Overview The TAAn of channels are outlined below ( 4). Item Clock selection ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.2 Functions The functions of TAAn that can be realized differ from one channel to another, as shown in the table below ( 4). Function Interval timer External event counter ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.3 Configuration TAAn includes the following hardware ( 4). Item 16-bit counter × 1 Timer register Registers TAAn capture/compare registers 0, 1 (TAAnCCR0, TAAnCCR1) TAAn counter read buffer register (TAAnCNT) ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA / / / /128 XX Remark f : Peripheral clock XX Figure 6-1. TAA0 Block ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA / / / /128 XX Remark f : Peripheral clock XX 194 Figure 6-2. TAA1 ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA / / /256 XX f /1024 XX f /2048 XX Edge detection/ TIA20 Noise eliminator Edge detection/ TIA21 Noise ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA / / /256 XX f /1024 XX f /2048 XX Edge detection/ Note TIA30 Noise eliminator Edge detection/ Note ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA / / /256 XX f /1024 XX f /2048 XX Edge detection/ TIA40 Noise eliminator Edge detection/ TIA41 Noise ...

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TAAnCNT register. When the TAAnCTL0.TAAnCE bit = 0, ...

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