UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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www.renesas.com
μPD70F3740
μPD70F3741
μPD70F3742
V850ES/JG3
RENESAS MCU
V850ES/JG3 Microcontrollers
μPD70F3739
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
User’s Manual: Hardware
Rev.3.00 Sep 2010

Related parts for UPD70F3740GC-UEU-AX

UPD70F3740GC-UEU-AX Summary of contents

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V850ES/JG3 32 RENESAS MCU V850ES/JG3 Microcontrollers μPD70F3739 μPD70F3740 μPD70F3741 μPD70F3742 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care to prevent chattering noise ...

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Readers This manual is intended for users who wish to understand the functions of the V850ES/JG3 and design application systems using the V850ES/JG3. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JG3 ...

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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...

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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG3 Documents related to development tools Document Name V850ES Architecture User’s Manual V850ES/JG3 Hardware User’s Manual ...

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Caution: This product uses SuperFlash IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America. ...

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CHAPTER 1 INTRODUCTION....................................................................................................................1 1.1 General .......................................................................................................................................1 1.2 Features......................................................................................................................................3 1.3 Application Fields......................................................................................................................4 1.4 Ordering Information.................................................................................................................4 1.5 Pin Configuration (Top View) ...................................................................................................5 1.6 Function Block Configuration ..................................................................................................7 1.6.1 Internal block diagram..................................................................................................................7 1.6.2 Internal units ................................................................................................................................8 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 11 2.1 ...

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Port DH ....................................................................................................................................101 4.3.11 Port DL.....................................................................................................................................103 4.4 Block Diagrams..................................................................................................................... 106 4.5 Port Register Settings When Alternate Function Is Used ................................................ 136 CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 149 5.1 Features................................................................................................................................. 149 5.2 Bus Control Pins................................................................................................................... 150 5.2.1 Pin status ...

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One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)...............................................234 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) ..............................................................241 7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) ....................................................250 7.5.7 Pulse width measurement mode (TPnMD2 to ...

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Registers ............................................................................................................................... 402 12.4 Operation............................................................................................................................... 404 12.5 Usage ..................................................................................................................................... 405 12.6 Cautions ................................................................................................................................ 405 CHAPTER 13 A/D CONVERTER ......................................................................................................... 406 13.1 Overview................................................................................................................................ 406 13.2 Functions............................................................................................................................... 406 13.3 Configuration ........................................................................................................................ 407 13.4 Registers ............................................................................................................................... 410 13.5 Operation............................................................................................................................... 421 13.5.1 Basic ...

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CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB).................................................... 484 16.1 Mode Switching of CSIB and Other Serial Interfaces ....................................................... 484 16.1.1 CSIB4 and UARTA0 mode switching.......................................................................................484 16.1.2 CSIB0 and I 16.2 Features................................................................................................................................. 485 16.3 Configuration ........................................................................................................................ 486 16.4 Registers ............................................................................................................................... 488 ...

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Operation without communication............................................................................................577 17.7.5 Arbitration loss operation (operation as slave after arbitration loss).........................................577 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ...................579 17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 586 17.9 Address Match ...

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Operation .................................................................................................................................657 19.4.2 Restore ....................................................................................................................................658 19.4.3 EP flag .....................................................................................................................................659 19.5 Exception Trap...................................................................................................................... 660 19.5.1 Illegal opcode definition............................................................................................................660 19.5.2 Debug trap ...............................................................................................................................662 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) ................................... 664 19.6.1 Noise elimination......................................................................................................................664 19.6.2 Edge ...

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Reset function operation flow...................................................................................................701 CHAPTER 23 CLOCK MONITOR ........................................................................................................ 702 23.1 Functions............................................................................................................................... 702 23.2 Configuration ........................................................................................................................ 702 23.3 Register ................................................................................................................................. 703 23.4 Operation............................................................................................................................... 704 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) ............................................................................. 707 24.1 Functions............................................................................................................................... 707 24.2 Configuration ........................................................................................................................ 707 24.3 ...

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Connection circuit example ......................................................................................................747 28.1.2 Interface signals.......................................................................................................................747 28.1.3 Maskable functions ..................................................................................................................749 28.1.4 Register ...................................................................................................................................749 28.1.5 Operation .................................................................................................................................751 28.1.6 Cautions...................................................................................................................................751 28.2 Debugging Without Using DCU........................................................................................... 752 28.2.1 Circuit connection examples ....................................................................................................752 28.2.2 Maskable functions ..................................................................................................................753 28.2.3 Securement of user resources ...

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V850ES/JG3 RENESAS MCU The V850ES/JG3 is one of the products in the Renesas Electronics V850 single-chip microcontrollers designed for low- power operation for real-time control applications. 1.1 General The V850ES/JG3 is a 32-bit single-chip microcontroller that includes the V850ES CPU ...

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V850ES/JG3 Part Number Internal Flash memory memory RAM Memory Logical space space External memory area External bus interface Address bus: 22 bits Data bus: 8/16 bits Multiplex bus mode/separate bus mode 32 bits × 32 registers General-purpose register Main clock ...

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V850ES/JG3 1.2 Features Minimum instruction execution time: 31.25 ns (operating with main clock (f General-purpose registers: CPU features: Memory space: • Internal memory: • External bus interface: Interrupts and exceptions: I/O lines: Timer function: Real-time output port: Serial interface: A/D ...

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V850ES/JG3 1.3 Application Fields Home audio, printers, digital home electronics, other consumer devices 1.4 Ordering Information Part Number μ PD70F3739GC-UEU-AX μ PD70F3740GC-UEU-AX μ PD70F3741GC-UEU-AX μ PD70F3742GC-UEU-AX Remark The V850ES/JG3 microcontrollers are lead-free products. R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Package 100-pin ...

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V850ES/JG3 1.5 Pin Configuration (Top View) 100-pin plastic LQFP (fine pitch) (14 × 14) μ PD70F3739GC-UEU-AX μ PD70F3741GC-UEU- REF0 P10/ANO0 3 P11/ANO1 REF1 PDH4/A20 6 PDH5/A21 7 Note 1 FLMD0 8 V ...

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V850ES/JG3 Pin names A0 to A21: Address bus AD0 to AD15: Address/data bus ADTRG: A/D trigger input ANI0 to ANI11: Analog input ANO0, ANO1: Analog output ASCKA0: Asynchronous serial clock ASTB: Address strobe Analog reference voltage ...

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V850ES/JG3 1.6 Function Block Configuration 1.6.1 Internal block diagram NMI INTC INTP0 to INTP7 16-bit timer/ TIQ00 to TIQ03 counter Q: TOQ00 to TOQ03 1 ch TIP00 to TIP50, 16-bit timer/ TIP01 to TIP51 counter P: TOP00 to TOP50, 6 ...

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V850ES/JG3 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits ...

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V850ES/JG3 (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 ...

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V850ES/JG3 (19) Ports The general-purpose port functions and control pin functions are listed below. Port I/O P0 5-bit I/O P1 2-bit I/O P3 10-bit I/O P4 3-bit I/O P5 6-bit I/O P7 12-bit I/O P9 16-bit I/O PCM 4-bit I/O ...

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V850ES/JG3 2.1 List of Pin Functions The names and functions of the pins in the V850ES/JG3 are described below. There are three types of pin I/O buffer power supplies: AV supplies and the pins is described below. Power Supply AV ...

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V850ES/JG3 Pin Name Pin No. I/O P40 22 I/O Port 4 3-bit I/O port Input/output can be specified in 1-bit units. P41 23 N-ch open-drain output can be specified in 1-bit units tolerant. P42 24 P50 37 I/O ...

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V850ES/JG3 Pin Name Pin No. I/O PCM0 61 I/O Port CM 4-bit I/O port PCM1 62 Input/output can be specified in 1-bit units. PCM2 63 PCM3 64 PCT0 65 I/O Port CT 4-bit I/O port PCT1 66 Input/output can be ...

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V850ES/JG3 (2) Non-port pins Pin Name Pin No. I Output Address bus for external memory (when using separate bus N-ch open-drain output selectable tolerant ...

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V850ES/JG3 Pin Name Pin No. I/O ADTRG 18 Input A/D converter external trigger input tolerant. ANI0 100 Input Analog voltage input for A/D converter ANI1 99 ANI2 98 ANI3 97 ANI4 96 ANI5 95 ANI6 94 ANI7 93 ...

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V850ES/JG3 Pin Name Pin No. I/O INTP0 18 Input External interrupt request input (maskable, analog noise elimination). INTP1 19 Analog noise elimination or digital noise elimination INTP2 20 selectable for INTP3 pin. INTP3 tolerant. INTP4 56 INTP5 ...

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V850ES/JG3 Pin Name Pin No. I/O SCL00 36 I/O Serial clock I/O (I N-ch open-drain output selectable. SCL01 tolerant. SCL02 44 SDA00 35 I/O Serial transmit/receive data I/O (I N-ch open-drain output selectable. SDA01 ...

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V850ES/JG3 Pin Name Pin No. I/O TOP00 27 Output Timer output (TMP0) N-ch open-drain output selectable tolerant. TOP01 28 TOP10 29 Timer output (TMP1) N-ch open-drain output selectable tolerant. TOP11 30 TOP20 50 Timer output (TMP2) ...

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V850ES/JG3 2.2 Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Pin Name When Power Is Turned Note 1 On P05/DRST Pulled down P10/ANO0, P11/ANO1 Hi-Z P53/DDO ...

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V850ES/JG3 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins Pin Alternate Function P02 NMI P03 INTP0/ADTRG P04 INTP1 P05 INTP2/DRST P06 INTP3 P10, P11 ANO0, ANO1 P30 TXDA0/SOB4 P31 RXDA0/INTP7/SIB4 P32 ASCKA0/SCKB4/TIP00 P33 TIP01/TOP01 ...

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V850ES/JG3 Pin Alternate Function P70 to P711 ANI0 to ANI11 P90 A0/KR6/TXDA1/SDA02 P91 A1/KR7/RXDA1/SCL02 P92 A2/TIP41/TOP41 P93 A3/TIP40/TOP40 P94 A4/TIP31/TOP31 P95 A5/TIP30/TOP30 P96 A6/TIP21/TOP21 P97 A7/SIB1/TIP20/TOP20 P98 A8/SOB1 P99 A9/SCKB1 P910 A10/SIB3 P911 A11/SOB3 P912 A12/SCKB3 P913 A13/INTP4 P914 A14/INTP5/TIP51/TOP51 ...

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V850ES/JG3 Pin Alternate Function − AV REF0 − AV REF1 − − − − FLMD0 − REGC − RESET − − − X1 − X2 − XT1 − XT2 R01UH0015EJ0300 ...

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V850ES/JG3 Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5 Data Output disable Input enable Type 10-D Data Open drain Output disable Note Input enable Type 10-G Data Open drain Output disable Input enable Note Hysteresis characteristics are not ...

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V850ES/JG3 2.4 Cautions When the power is turned on, the following pin may output an undefined level temporarily, even during reset. • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 CHAPTER 2 PIN FUNCTIONS Page 24 of 870 ...

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V850ES/JG3 The CPU of the V850ES/JG3 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 31.25 ns (at 32 MHz operation) Memory space Program (physical ...

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V850ES/JG3 3.2 CPU Register Set The registers of the V850ES/JG3 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) ...

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V850ES/JG3 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data ...

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V850ES/JG3 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed ...

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V850ES/JG3 (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved ...

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V850ES/JG3 (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and ...

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V850ES/JG3 (4) Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of ...

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V850ES/JG3 Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when ...

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V850ES/JG3 (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of ...

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V850ES/JG3 3.3 Operation Modes The V850ES/JG3 has the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to ...

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V850ES/JG3 3.4 Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and an internal ROM area, plus an internal RAM area, are supported in a linear address ...

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V850ES/JG3 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore ...

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V850ES/JG3 3.4.3 Memory map The areas shown below are reserved in the V850ES/JG3. Figure 3-2. Data Memory Map (Physical Addresses (64 KB ...

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V850ES/JG3 R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 3-3. Program Memory Map Use prohibited (program fetch prohibited area ...

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V850ES/JG3 3.4.4 Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (384 KB) 384 KB are allocated to addresses 00000000H to 0005FFFFH in the Accessing addresses 00060000H to 000FFFFFH is ...

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V850ES/JG3 (c) Internal ROM (768 KB) 768 KB are allocated to addresses 00000000H to 000BFFFFH in the Accessing addresses 000C0000H to 000FFFFFH is prohibited. (d) Internal ROM (1024 KB) 1024 KB are allocated to addresses 00000000H to 000FFFFFH in the ...

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V850ES/JG3 (2) Internal RAM area are reserved as the internal RAM area. (a) Internal RAM (32 KB are allocated to addresses 03FF7000H to 03FFEFFFH in the Accessing addresses 03FF0000H to 03FF6FFFH is prohibited. Physical ...

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V850ES/JG3 (c) Internal RAM (60 KB are allocated to addresses 03FF0000H to 03FFEFFFH in the Physical address space R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 3-10. Internal RAM Area (60 KB) Logical address space ...

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V850ES/JG3 (3) On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Physical address space Peripheral I/O registers that have functions to specify the operation mode for and monitor the status ...

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V850ES/JG3 3.4.5 Recommended use of address space The architecture of the V850ES/JG3 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this ...

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V850ES/JG3 (a) Application example of wraparound (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, ...

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V850ES/JG3 ...

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V850ES/JG3 3.4.6 Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H FFFFF006H Port DH register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF024H Port DL mode register ...

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V850ES/JG3 Address Function Register Name FFFFF0D2H DMA addressing control register 1 FFFFF0D4H DMA addressing control register 2 FFFFF0D6H DMA addressing control register 3 FFFFF0E0H DMA channel control register 0 FFFFF0E2H DMA channel control register 1 FFFFF0E4H DMA channel control register ...

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V850ES/JG3 Address Function Register Name FFFFF140H Interrupt control register FFFFF142H Interrupt control register FFFFF144H Interrupt control register FFFFF146H Interrupt control register FFFFF148H Interrupt control register FFFFF14AH Interrupt control register FFFFF14CH Interrupt control register FFFFF14EH Interrupt control register FFFFF150H Interrupt control ...

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V850ES/JG3 Address Function Register Name FFFFF210H A/D conversion result register 0 FFFFF211H A/D conversion result register 0H FFFFF212H A/D conversion result register 1 FFFFF213H A/D conversion result register 1H FFFFF214H A/D conversion result register 2 FFFFF215H A/D conversion result register ...

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V850ES/JG3 Address Function Register Name FFFFF406H Port 3 register FFFFF406H Port 3 register L FFFFF407H Port 3 register H FFFFF408H Port 4 register FFFFF40AH Port 5 register FFFFF40EH Port 7 register L FFFFF40FH Port 7 register H FFFFF412H Port 9 ...

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V850ES/JG3 Address Function Register Name FFFFF484H Data wait control register 0 FFFFF488H Address wait control register FFFFF48AH Bus cycle control register FFFFF540H TMQ0 control register 0 FFFFF541H TMQ0 control register 1 FFFFF542H TMQ0 I/O control register 0 FFFFF543H TMQ0 I/O ...

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V850ES/JG3 Address Function Register Name FFFFF5C2H TMP3 I/O control register 0 FFFFF5C3H TMP3 I/O control register 1 FFFFF5C4H TMP3 I/O control register 2 FFFFF5C5H TMP3 option register 0 FFFFF5C6H TMP3 capture/compare register 0 FFFFF5C8H TMP3 capture/compare register 1 FFFFF5CAH TMP3 ...

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V850ES/JG3 Address Function Register Name FFFFF812H DMA trigger factor register 1 FFFFF814H DMA trigger factor register 2 FFFFF816H DMA trigger factor register 3 FFFFF820H Power save mode register FFFFF822H Clock control register FFFFF824H Lock register FFFFF828H Processor clock control register ...

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V850ES/JG3 Address Function Register Name FFFFFC13H External interrupt falling edge specification register 9H INTF9H FFFFFC20H External interrupt rising edge specification register 0 FFFFFC26H External interrupt rising edge specification register 3 FFFFFC33H External interrupt rising edge specification register 9H INTR9H FFFFFC60H ...

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V850ES/JG3 Address Function Register Name FFFFFD36H CSIB3 transmit data register FFFFFD36H CSIB3 transmit data register L FFFFFD40H CSIB4 control register 0 FFFFFD41H CSIB4 control register 1 FFFFFD42H CSIB4 control register 2 FFFFFD43H CSIB4 status register FFFFFD44H CSIB4 receive data register ...

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V850ES/JG3 3.4.7 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JG3 has the following eight special registers. • Power save control register (PSC) • Clock control register ...

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V850ES/JG3 (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared ...

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V850ES/JG3 (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The ...

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V850ES/JG3 (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ...

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V850ES/JG3 3.4.8 Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JG3. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) ...

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V850ES/JG3 (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU ...

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V850ES/JG3 (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request ...

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V850ES/JG3 4.1 Features I/O ports: 84 • tolerant/N-ch open-drain output selectable: 40 (ports Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JG3 features a total of 84 I/O ports consisting of ...

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V850ES/JG3 4.3 Port Configuration Item Control register Port n mode register (PMn CD, CM, CT, DH, DL) Port n mode control register (PMCn CM, ...

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V850ES/JG3 (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can ...

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V850ES/JG3 (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port ...

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V850ES/JG3 (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified ...

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V850ES/JG3 (7) Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate ...

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V850ES/JG3 4.3.1 Port 0 Port 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P02 17 NMI P03 18 INTP0/ADTRG ...

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V850ES/JG3 (2) Port 0 mode register (PM0) After reset: FFH PM0 1 PM0n 0 Output mode 1 Input mode (3) Port 0 mode control register (PMC0) After reset: 00H PMC0 0 PMC06 0 I/O port 1 INTP3 input PMC05 0 ...

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V850ES/JG3 (4) Port 0 function control register (PFC0) After reset: 00H PFC0 0 PFC03 0 INTP0 input 1 ADTRG input (5) Port 0 function register (PF0) After reset: 00H PF0 0 PF0n 0 Normal output (CMOS output) 1 N-ch open ...

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V850ES/JG3 4.3.2 Port 1 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P10 3 ANO0 P11 4 ANO1 ...

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V850ES/JG3 4.3.3 Port 3 Port 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P30 25 TXDA0/SOB4 P31 26 RXDA0/INTP7/SIB4 ...

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V850ES/JG3 (1) Port 3 register (P3) After reset: 0000H (output latch (P3H) 0 (P3L) P37 P3n 0 1 Remarks 1. The P3 register can be read or written in 16-bit units. However, when using the higher 8 bits ...

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V850ES/JG3 (3) Port 3 mode control register (PMC3) After reset: 0000H 15 PMC3 (PMC3H) 0 (PMC3L) 0 PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 PMC30 0 ...

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V850ES/JG3 (4) Port 3 function control register (PFC3) After reset: 0000H 15 PFC3 (PFC3H) 0 (PFC3L) 0 Remarks 1. For details of alternate function specification, see 4.3.3 (6) Port 3 alternate function specifications. 2. The PFC3 register can be read ...

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V850ES/JG3 (6) Port 3 alternate function specifications PFC39 0 RXDA2 input 1 SCL00 input PFC38 0 TXDA2 output 1 SDA00 I/O PFC35 0 TIP11 input 1 TOP11 output PFC34 0 TIP10 input 1 TOP10 output PFC33 0 TIP01 input 1 ...

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V850ES/JG3 (7) Port 3 function register (PF3) After reset: 0000H 15 0 PF3 (PF3H) (PF3L) PF37 PF3n 0 1 Caution When an output pin is pulled Remarks 1. The PF3 register can be read or written in ...

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V850ES/JG3 4.3.4 Port 4 Port 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P40 22 SIB0/SDA01 P41 23 SOB0/SCL01 P42 24 SCKB0 Caution ...

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V850ES/JG3 (3) Port 4 mode control register (PMC4) After reset: 00H PMC4 0 PMC42 0 I/O port 1 SCKB0 I/O PMC41 0 I/O port 1 SOB0 output/SCL01 I/O PMC40 0 I/O port 1 SIB0 input/SDA01 I/O (4) Port 4 function ...

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V850ES/JG3 (5) Port 4 function register (PF4) After reset: 00H PF4 0 PF4n 0 Normal output (CMOS output) 1 N-ch open-drain output Caution When an output pin is pulled R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 R/W Address: FFFFFC68H ...

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V850ES/JG3 4.3.5 Port 5 Port 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P50 37 TIQ01/KR0/TOQ01/RTP00 P51 38 TIQ02/KR1/TOQ02/RTP01 P52 39 TIQ03/KR2/TOQ03/RTP02/DDI P53 ...

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V850ES/JG3 (2) Port 5 mode register (PM5) After reset: FFH PM5 1 PM5n 0 Output mode 1 Input mode (3) Port 5 mode control register (PMC5) After reset: 00H PMC5 0 PMC55 0 I/O port 1 SCKB2 I/O/KR5 input/RTP05 output ...

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V850ES/JG3 (4) Port 5 function control register (PFC5) After reset: 00H PFC5 0 Remark For details of alternate function specification, see 4.3.5 (6) specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H PFCE5 0 Remark For details ...

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V850ES/JG3 PFCE52 PFC52 PFCE51 PFC51 PFCE50 PFC50 Note The KRn pin and TIQ0m pin are alternate-function ...

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V850ES/JG3 4.3.6 Port 7 Port 12-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P70 100 ANI0 P71 99 ANI1 ...

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V850ES/JG3 (1) Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) P7H 0 P77 P7L P7n 0 Outputs 0 1 Outputs 1 Caution Do not read/write the P7H and P7L registers during A/D conversion ...

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V850ES/JG3 4.3.7 Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P90 43 A0/KR6/TXDA1/SDA02 P91 44 A1/KR7/RXDA1/SCL02 ...

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V850ES/JG3 (1) Port 9 register (P9) After reset: 0000H (output latch (P9H) P915 (P9L) P97 P9n 0 1 Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the higher 8 bits ...

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V850ES/JG3 (3) Port 9 mode control register (PMC9) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 1 ...

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V850ES/JG3 PMC98 0 I/O port 1 A8 output/SOB1 output PMC97 0 I/O port 1 A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 0 I/O port 1 A6 output/TIP21 input/TOP21 output PMC95 0 I/O port 1 A5 output/TIP30 input/TOP30 output PMC94 0 I/O ...

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V850ES/JG3 (4) Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 or PFCE9 register to 0000H. After ...

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V850ES/JG3 (6) Port 9 alternate function specifications PFCE915 PFC915 PFCE914 PFC914 PFC913 0 A13 output 1 INTP4 input PFC912 0 A12 output 1 SCKB3 ...

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V850ES/JG3 PFCE96 PFC96 PFCE95 PFC95 PFCE94 PFC94 PFCE93 PFC93 ...

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V850ES/JG3 (7) Port 9 function register (PF9) After reset: 0000H 15 PF9 (PF9H) PF915 (PF9L) PF97 PF9n 0 1 Caution When an output pin is pulled Remarks 1. The PF9 register can be read or written in ...

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V850ES/JG3 4.3.8 Port CM Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PCM0 61 WAIT PCM1 62 CLKOUT ...

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V850ES/JG3 (3) Port CM mode control register (PMCCM) After reset: 00H PMCCM 0 PMCCM3 0 1 PMCCM2 0 1 PMCCM1 0 1 PMCCM0 0 1 R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 R/W Address: FFFFF04CH PMCCM3 PMCCM2 PMCCM1 PMCCM0 ...

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V850ES/JG3 4.3.9 Port CT Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PCT0 65 WR0 PCT1 66 WR1 ...

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V850ES/JG3 (3) Port CT mode control register (PMCCT) After reset: 00H PMCCT 0 PMCCT6 0 1 PMCCT4 0 1 PMCCT1 0 1 PMCCT0 0 1 R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 R/W Address: FFFFF04AH PMCCT6 0 PMCCT4 0 Specification of PCT6 ...

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V850ES/JG3 4.3.10 Port DH Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PDH0 87 A16 PDH1 88 A17 ...

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V850ES/JG3 (3) Port DH mode control register (PMCDH) After reset: 00H PMCDH 0 PMCDHn 0 1 R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 R/W Address: FFFFF046H 0 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 Specification of PDHn pin operation mode ( ...

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V850ES/JG3 4.3.11 Port DL Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PDL0 71 AD0 PDL1 72 AD1 ...

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V850ES/JG3 (1) Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 (PDLL) PDL7 PDLn 0 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 bits ...

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V850ES/JG3 (3) Port DL mode control register (PMCDL) After reset: 0000H 15 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Caution When the SMSEL bit of the EXIMC ...

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V850ES/JG3 4.4 Block Diagrams PORT RD R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 4-3. Block Diagram of Type A-1 PMmn Pmn Address P-ch A/D input signal N-ch CHAPTRER 4 PORT FUNCTIONS Pmn Page 106 of 870 ...

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V850ES/JG3 PORT RD R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 4-4. Block Diagram of Type A-2 PMmn Pmn Address P-ch D/A output signal N-ch CHAPTRER 4 PORT FUNCTIONS Pmn Page 107 of 870 ...

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V850ES/JG3 WR PF PFmn WR PM PMmn WR PORT Pmn Address RD R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 4-5. Block Diagram of Type C-1 CHAPTRER 4 PORT FUNCTIONS EV DD P-ch Pmn N- Page 108 of 870 ...

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V850ES/JG3 WR PMC PORT RD alternate function is used R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 4-6. Block Diagram of Type D-1 PMCmn PMmn Pmn Address Input signal when CHAPTRER 4 PORT FUNCTIONS Pmn Page 109 of 870 ...

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V850ES/JG3 WR PMC PMCmn WR PM Output signal when alternate function is used WR PORT RD R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure 4-7. Block Diagram of Type D-2 PMmn Pmn Address CHAPTRER 4 PORT FUNCTIONS Pmn Page 110 of 870 ...

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V850ES/JG3 WR PMC Output enable signal of address/data bus Output buffer off signal WR PM Output signal when alternate function is used WR PORT Input enable signal of address/data bus Input signal when alternate function is used RD R01UH0015EJ0300 Rev.3.00 ...

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V850ES/JG3 WR PF PFmn Output enable signal when alternate function is used WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics ...

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V850ES/JG3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port ...

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V850ES/JG3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port ...

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V850ES/JG3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD R01UH0015EJ0300 Rev.3.00 Sep 30, 2010 Figure ...

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V850ES/JG3 WR PF PFmn Output enable signal when alternate function is used WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn ...

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V850ES/JG3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal 1 when alternate function is used Input signal 2 when alternate function is ...

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V850ES/JG3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is ...

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V850ES/JG3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used Notes 1. See 19.6 External Interrupt Request ...

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V850ES/JG3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used Input signal 2 when ...

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V850ES/JG3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function ...

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V850ES/JG3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when ...

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V850ES/JG3 WR PF PFmn Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used ...

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V850ES/JG3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal 1-1 when ...

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V850ES/JG3 WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input ...

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V850ES/JG3 WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging ...

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V850ES/JG3 WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input ...

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V850ES/JG3 WR PF PFmn WR OCDM0 OCDM0 Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate ...

Page 145

V850ES/JG3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used ...

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V850ES/JG3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal 1 ...

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V850ES/JG3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when RD ...

Page 148

V850ES/JG3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when RD ...

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V850ES/JG3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal 1 ...

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V850ES/JG3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function ...

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V850ES/JG3 WR PF PFmn External reset signal WR OCDM0 OCDM0 WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when on-chip debugging Input signal when alternate ...

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V850ES/JG3 4.5 Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of ...

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Pin Alternate Function Pnx Bit of Name Pn Register Name I/O P02 NMI Input P02 = Setting not required PM02 = Setting not required P03 INTP0 Input P03 = Setting not required PM03 = Setting not required ADTRG Input P03 ...

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Pin Alternate Function Pnx Bit of Name Pn Register Name I/O P34 TIP10 Input P34 = Setting not required PM34 = Setting not required TOP10 Output P34 = Setting not required PM34 = Setting not required P35 TIP11 Input P35 ...

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Pin Alternate Function Pnx Bit of Name Pn Register Name I/O P53 SIB2 Input P53 = Setting not required PM53 = Setting not required TIQ00 Input P53 = Setting not required PM53 = Setting not required KR3 Input P53 = ...

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Pin Alternate Function Pnx Bit of Name Pn Register Name I/O P90 A0 Output P90 = Setting not required PM90 = Setting not required KR6 Input P90 = Setting not required PM90 = Setting not required TXDA1 Output P90 = ...

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Pin Alternate Function Pnx Bit of Name Pn Register Name I/O P97 A7 Output P97 = Setting not required PM97 = Setting not required SIB1 Input P97 = Setting not required PM97 = Setting not required TIP20 Input P97 = ...

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Pin Alternate Function Pnx Bit of Name Pn Register Name I/O PCM0 WAIT Input PCM0 = Setting not required PMCM0 = Setting not required PCM1 CLKOUT Output PCM1 = Setting not required PMCM1 = Setting not required PCM2 HLDAK Output ...

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Pin Alternate Function Pnx Bit of Name Pn Register Name I/O PDL8 AD8 I/O PDL8 = Setting not required PMDL8 = Setting not required PDL9 AD9 I/O PDL9 = Setting not required PMDL9 = Setting not required PDL10 AD10 I/O ...

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V850ES/JG3 4.6 Cautions 4.6.1 Cautions on setting port pins (1) In the V850ES/JG3, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin ...

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V850ES/JG3 The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order <1> <2> <3> <4> <2> communication may be affected since the ...

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V850ES/JG3 Figure 4-33. Example of Switching from P02 to NMI (Incorrect) PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Remark [Example 2] Switch from external pin (NMI) to ...

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V850ES/JG3 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that ...

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V850ES/JG3 4.6.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST ...

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V850ES/JG3 The V850ES/JG3 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplexed bus with a minimum of 3 bus ...

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V850ES/JG3 5.2 Bus Control Pins The pins used to connect an external device are listed in the table below. Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 A16 to A21 PDH0 to PDH5 WAIT PCM0 CLKOUT PCM1 ...

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V850ES/JG3 5.3 Memory Block Function The 16 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these ...

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V850ES/JG3 5.4 External Bus Interface Mode Control Function The V850ES/JG3 includes the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus ...

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V850ES/JG3 5.5 Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access ...

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V850ES/JG3 5.5.3 Access by bus size The V850ES/JG3 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to ...

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V850ES/JG3 (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n Byte data External data bus (b) 8-bit data bus width <1> Access to even address (2n) 7 ...

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V850ES/JG3 (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n Halfword data External data bus (b) 8-bit data bus width <1> Access to even ...

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V850ES/JG3 (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External data ...

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V850ES/JG3 (a) 16-bit data bus width (2/2) <3> Access to address ( First access Address Word data External data bus ...

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V850ES/JG3 (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External data Word data bus <2> Access ...

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V850ES/JG3 (b) 8-bit data bus width (2/2) <3> Access to address ( First access Address Word data External data Word ...

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V850ES/JG3 5.6 Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/ seven data wait states can be inserted in the bus cycle that is executed ...

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V850ES/JG3 5.6.2 External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is ...

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V850ES/JG3 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the ...

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V850ES/JG3 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each memory block area (memory blocks 0 to 3). ...

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V850ES/JG3 5.7 Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected as the memory block in the ...

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V850ES/JG3 5.8 Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has ...

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V850ES/JG3 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK ...

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V850ES/JG3 5.9 Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch ...

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V850ES/JG3 5.10 Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A21 to A16 A1 ASTB WAIT AD15 to AD0 8-bit access AD15 to AD8 AD7 to AD0 Remark ...

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V850ES/JG3 Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT A21 to A16 A1 ASTB WAIT A1 AD15 to AD0 11 00 WR1, WR0 8-bit access AD15 to AD8 AD7 to AD0 WR1, WR0 ...

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V850ES/JG3 Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT HLDRQ HLDAK A21 to A16 AD15 to AD0 ASTB RD Note This idle state (TI) does not depend on the BCC ...

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V850ES/JG3 Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT WAIT A1 A21 AD15 to AD0 D1 8-bit access Odd address AD15 to AD8 Active AD7 to AD0 Hi-Z Remark The ...

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V850ES/JG3 Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T1 CLKOUT WAIT A1 A21 WR1, WR0 AD15 to AD0 8-bit access AD15 to AD8 AD7 to AD0 WR1, WR0 Remark The broken lines ...

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V850ES/JG3 Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write CLKOUT HLDRQ HLDAK A21 AD7 to AD0 D1 WR1, WR0 Note This idle state (TI) does not depend on the ...

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V850ES/JG3 CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode MHz ( MHz • In PLL mode ...

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V850ES/JG3 6.2 Configuration FRC bit XT1 f Subclock XT oscillator XT2 MCK MFRC PLLON bit bit bit X1 f Main clock X PLL oscillator X2 Main clock oscillator stop control STOP mode SELPLL bit CLKOUT Port CM Note The internal ...

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V850ES/JG3 (1) Main clock oscillator The main resonator oscillates the following frequencies (f • In clock-through mode MHz X • In PLL mode MHz (× 2.5 to ...

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V850ES/JG3 6.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. R01UH0015EJ0300 ...

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V850ES/JG3 After reset: 03H PCC FRC FRC 0 Used 1 Not used MCK 0 Oscillation enabled 1 Oscillation stopped Even if the MCK bit is set (1) while the system is operating with the main clock as • the CPU ...

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V850ES/JG3 (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following <3> MCK bit ← 1: Cautions ...

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V850ES/JG3 (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3> CK3 bit ← 0: <4> ...

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V850ES/JG3 (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to ...

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V850ES/JG3 6.4 Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Register Setting and Operation Status During Reset Target Clock Main clock oscillator ( Subclock oscillator ( CPU clock ...

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V850ES/JG3 6.5 PLL Function 6.5.1 Overview In the V850ES/JG3, an operating clock that times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of ...

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