UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet
UPD70F3771GF-GAT-AX
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V850ES/JG3-H, V850ES/JH3-H 32 RENESAS MCU V850ES/Jx3-H Microcontrollers V850ES/JG3-H μPD70F3760 μPD70F3761 μPD70F3762 μPD70F3770 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care to prevent chattering noise ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/JG3-H and V850ES/JH3-H and design application systems using the V850ES/JG3-H and V850ES/JH3-H. Purpose This manual is intended to give users an understanding of the hardware ...
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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG3-H and V850ES/JH3-H Documents related to development tools Document Name V850ES Architecture User’s Manual V850ES/JG3-H, V850ES/JH3-H ...
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Caution: This product uses SuperFlash EEPROM is a trademark of Renesas Electronics Corporation. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or ...
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CHAPTER 1 INTRODUCTION................................................................................................................. 19 1.1 General ...................................................................................................................................... 19 1.2 Features .................................................................................................................................... 22 1.3 Application Fields .................................................................................................................... 24 1.4 Ordering Information ............................................................................................................... 24 1.5 Pin Configuration (Top View).................................................................................................. 25 1.6 Function Block Configuration................................................................................................. 28 1.6.1 Internal block diagram.....................................................................................................................28 1.6.2 Internal units ...
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Cautions on setting port pins.........................................................................................................172 4.5.2 Cautions on bit manipulation instruction for port n register (Pn)....................................................175 4.5.3 Cautions on on-chip debug pins (V850ES/JG3-H only) ................................................................176 4.5.4 Cautions on P56/INTP05/DRST pin..............................................................................................176 4.5.5 Cautions on P10, P11, and P53 pins when ...
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Timer output operations ................................................................................................................308 7.6 Timer-Tuned Operation Function ......................................................................................... 309 7.6.1 Free-running timer mode (during timer-tuned operation) ..............................................................311 7.6.2 PWM output mode (during timer-tuned operation) ........................................................................318 7.7 Simultaneous-Start Function ................................................................................................ 320 7.7.1 PWM output mode (simultaneous-start operation) ........................................................................321 7.8 ...
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Control Registers ................................................................................................................... 581 11.4 Operation ................................................................................................................................ 591 11.4.1 System outline ..............................................................................................................................591 11.4.2 Dead-time control (generation of negative-phase wave signal).....................................................596 11.4.3 Interrupt culling function ................................................................................................................603 11.4.4 Operation to rewrite register with transfer function........................................................................610 11.4.5 TAA4 tuning operation for A/D ...
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Operation ................................................................................................................................ 718 16.4.1 Operation in normal mode.............................................................................................................718 16.4.2 Operation in real-time output mode...............................................................................................718 16.4.3 Cautions........................................................................................................................................719 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ............................................. 720 17.1 Features .................................................................................................................................. 720 17.2 Configuration.......................................................................................................................... 721 17.3 Mode Switching Between UARTC and Other ...
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CHAPTER BUS .......................................................................................................................... 814 19.1 Mode Switching of I 19.1.1 UARTC3 and I 19.1.2 UARTC4, CSIF0, and I 19.1.3 UARTC1 and I 19.2 Features .................................................................................................................................. 817 19.3 Configuration.......................................................................................................................... 818 19.4 Registers ................................................................................................................................. 822 2 19.5 I ...
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CAN sleep mode/CAN stop mode function ...................................................................................907 20.3.6 Error control function.....................................................................................................................907 20.3.7 Baud rate control function .............................................................................................................914 20.4 Connection with Target System ........................................................................................... 918 20.5 Internal Registers of CAN Controller ................................................................................... 919 20.5.1 CAN controller configuration .........................................................................................................919 20.5.2 Register ...
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Register Configuration ........................................................................................................ 1058 21.6.1 USB control registers ..................................................................................................................1058 21.6.2 USB function controller register list .............................................................................................1060 21.6.3 EPC control registers ..................................................................................................................1076 21.6.4 Data hold registers......................................................................................................................1128 21.6.5 EPC request data registers .........................................................................................................1151 21.6.6 Bridge register.............................................................................................................................1166 21.6.7 DMA register ...............................................................................................................................1170 21.6.8 ...
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External Interrupt Request Input Pins (NMI and INTP00 to INTP18)............................... 1294 23.6.1 Noise elimination.........................................................................................................................1294 23.6.2 Edge detection ............................................................................................................................1294 23.7 Interrupt Acknowledge Time of CPU.................................................................................. 1302 23.8 Periods in Which Interrupts Are Not Acknowledged by CPU ......................................... 1303 23.9 Cautions ...
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To use for interrupt......................................................................................................................1346 28.5 RAM Retention Voltage Detection Operation.................................................................... 1346 CHAPTER 29 CRC FUNCTION.......................................................................................................... 1348 29.1 Functions .............................................................................................................................. 1348 29.2 Configuration........................................................................................................................ 1348 29.3 Registers ............................................................................................................................... 1349 29.4 Operation .............................................................................................................................. 1350 29.5 Usage Method....................................................................................................................... 1351 CHAPTER 30 REGULATOR ............................................................................................................... ...
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Subclock oscillator characteristics ..............................................................................................1414 33.4.3 PLL characteristics......................................................................................................................1416 33.4.4 Internal oscillator characteristics .................................................................................................1416 33.5 DC Characteristics ............................................................................................................... 1417 33.5.1 I/O level.......................................................................................................................................1417 33.5.2 Supply current.............................................................................................................................1419 33.6 Data Retention Characteristics........................................................................................... 1420 33.7 AC Characteristics ............................................................................................................... 1421 33.7.1 CLKOUT output timing................................................................................................................1422 33.7.2 Bus ...
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V850ES/JG3-H, V850ES/JH3-H RENESAS MCU The V850ES/JG3-H and V850ES/JH3-H are products in the low-power series of Renesas Electronics’ V850 single-chip microcontrollers designed for real-time control applications. 1.1 General The V850ES/JG3-H and V850ES/JH3-H are 32-bit single-chip microcontrollers that use the V850ES CPU ...
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V850ES/JG3-H, V850ES/JH3-H Generic Name Part Number Internal Flash memory memory Note 1 RAM Memory Logical space 64 MB space External memory area 64 KB External bus interface Address data bus: 16 Multiplexed bus 32 bits × 32 registers General-purpose register ...
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V850ES/JG3-H, V850ES/JH3-H Generic Name Part Number Internal Flash memory memory Note 1 RAM Memory Logical space 64 MB space External memory area 13 MB External bus interface Address bus: 24 Address data bus: 16 Separate bus/Multiplexed bus 32 bits × ...
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V850ES/JG3-H, V850ES/JH3-H 1.2 Features Minimum instruction execution time: 20.8 ns (main clock (f General-purpose registers: CPU features: Memory space: • Internal memory: • External bus interface: Separate bus/multiplexed bus output selectable Interrupts and exceptions: V850ES/JG3-H V850ES/JH3-H Software exceptions: 32 sources ...
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V850ES/JG3-H, V850ES/JH3-H Real-time output port: Serial interface: A/D converter: D/A converter: DMA controller: DCU (debug control unit): Clock generator: Internal oscillation clock: Power-save functions: Package: R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 Watchdog timer: 6 bits × 1 channel Asynchronous serial interface ...
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V850ES/JG3-H, V850ES/JH3-H 1.3 Application Fields Equipment requiring a USB interface such as home audio systems, printers, and scanners. 1.4 Ordering Information • V850ES/JG3-H Part Number μ 100-pin plastic LQFP (fine pitch) (14 × 14) PD70F3760GC-UEU-AX μ 100-pin plastic LQFP (fine ...
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V850ES/JG3-H, V850ES/JH3-H 1.5 Pin Configuration (Top View) • V850ES/JH3-H 100-pin plastic LQFP (fine pitch) (14 × 14) μ PD70F3760GC-UEU-AX μ PD70F3770GC-UEU-AX 100 REF0 ...
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V850ES/JG3-H, V850ES/JH3-H • V850ES/JH3-H 128-pin plastic LQFP (fine pitch) (14 × 20) μ PD70F3765GF-GAT-AX μ PD70F3771GF-GAT-AX AV REF0 AV SS P10/ANO0 P11/ANO1 AV REF1 P02/NMI P03/INTP02/ADTRG/UCLK P00/INTP00 P01/INTP01 PCM2/HLDAK PCM3/HLDRQ Note 1 FLMD0 V DD Note 2 REGC V SS ...
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V850ES/JG3-H, V850ES/JH3-H Pin names A0 to A23: Address bus AD0 to AD15: Address/data bus ADTRG: A/D trigger input ANI0 to ANI11: Analog input ANO0, ANO1: Analog output Asynchronous serial clock ASCKC0: ASTB: Address strobe Analog reference ...
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V850ES/JG3-H, V850ES/JH3-H 1.6 Function Block Configuration 1.6.1 Internal block diagram • V850ES/JG3-H NMI INTP02 to INTP05 , INTP07 to INTP18 TIAB00 to TIAB03, TIAB10 to TIAB13, EVTAB1, TRGAB1, 16-bit timer/ TOAB1OFF counter AB: TOAB00 to TOAB03, TOAB10 to TOAB13 TOAB1T1 ...
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V850ES/JG3-H, V850ES/JH3-H • V850ES/JH3-H NMI INTP00 to INTP18 TIAB00 to TIAB03, TIAB10 to TIAB13, EVTAB1, TRGAB1, 16-bit timer/ TOAB1OFF counter AB: TOAB00 to TOAB03, TOAB10 to TOAB13 TOAB1T1 to TOAB1T3, TOAB1B1 to TOAB1B3 TIAA00 to TIAA30, TIAA50, TIAA01 to TIAA31, ...
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V850ES/JG3-H, V850ES/JH3-H 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 ...
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V850ES/JG3-H, V850ES/JH3-H (9) Real-time counter (for watch) The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768 kHz) or main clock. This can simultaneously be used as the interval timer based on the ...
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V850ES/JG3-H, V850ES/JH3-H (18) DCU (debug control unit) An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input ...
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V850ES/JG3-H, V850ES/JH3-H 2.1 List of Pin Functions The names and functions of the pins of the V850ES/JG3-H and V850ES/JH3-H are described below. There are four types of pin I/O buffer power supplies: AV power supplies and the pins is described ...
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V850ES/JG3-H, V850ES/JH3-H (1) Port pins Pin Name I/O P00 I/O Port 0 6-bit I/O port (V850ES/JH3-H) P01 4-bit I/O port (V850ES/JG3-H) P02 Input/output can be specified in 1-bit units. P03 P04 P05 P10 I/O Port 1 2-bit I/O port P11 ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O P60 I/O Port 6 6-bit I/O port Input/output can be specified in 1-bit units. P61 P62 P63 P64 P65 P70 I/O Port 7 12-bit I/O port P71 Input/output can be specified in 1-bit units. P72 ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O P98 I/O Port 9 16-bit I/O port Input/output can be specified in 1-bit units. P99 P910 P911 P912 P913 P914 P915 PCM0 I/O Port CM 4-bit I/O port (V850ES/JH3-H) PCM1 1-bit I/O port (V850ES/JG3-H) PCM2 ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O PDL0 I/O Port DL 16-bit I/O port PDL1 Input/output can be specified in 1-bit units. PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 Remark JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H R01UH0042EJ0400 ...
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V850ES/JG3-H, V850ES/JH3-H (2) Non-port Pins Pin Name I/O A0 Output Address bus for external memory (when using separate bus A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O ANI0 Input Analog voltage input for A/D converter ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANO0 Output Analog voltage output for D/A converter ANO1 ASCKC0 Input UARTC0 baud rate clock input ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O − EV Positive power supply for external devices DD (same potential as V EVTT0 Input External event count input of TMT0 EVTAB1 Input External event count input of TAB1 FLMD0 Input Flash memory programming mode ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O KR0 Input Key interrupt input (on-chip analog noise eliminator) KR1 KR2 KR3 KR4 KR5 KR6 KR7 NMI Input External interrupt input (non-maskable, analog noise elimination) − NC Non-Connection (Leave open.) RD Output Read strobe signal ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O RXDC0 Input Serial receive data input (UARTC0 to UARTC4) RXDC1 RXDC2 RXDC3 RXDC4 SCKF0 I/O Serial clock I/O (CSIF0 to CSIF4) N-ch open-drain output selectable SCKF1 SCKF2 SCKF3 SCKF4 SCL00 I/O Serial clock I/O (I ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O TECR0 Input TMT0 encoder clear input TENC00 TMT0 encoder input TENC01 TIAA00 Input External event count input/capture trigger input/external trigger input (TAA0) TIAA01 Capture trigger input (TAA0) TIAA10 External event count input/capture trigger input/external trigger ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O TIT00 Input TMT0 external trigger input/capture trigger input TIT01 Input TMT0 capture trigger input TOAA00 Output Timer output (TAA0) N-ch open-drain output selectable TOAA01 TOAA10 Timer output (TAA1) N-ch open-drain output selectable TOAA11 TOAA1OFF Input ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O TOAB1B1 Output Pulse signal output for 6-phase PWM low-arm of TAB1 TOAB1B2 TOAB1B3 TOAB1T1 Output Pulse signal output for 6-phase PWM high-arm of TAB1 TOAB1T2 TOAB1T3 TOT00 Output TMT0 timer output TOT01 TRGAB1 Input External ...
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V850ES/JG3-H, V850ES/JH3-H Pin Name I/O WAIT Input External wait input WR0 Output Write strobe for external memory (lower 8 bits) WR1 Write strove for external memory (higher 8 bits) X1 Input Connection of resonator for main clock − X2 XT1 ...
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V850ES/JG3-H, V850ES/JH3-H 2.2 Pin States The operation states of pins in the various operation modes are described below. Table 2-2. Pin Operation States in Various Modes Pin Name When Power Is Turned Note 1 On DRST Pull down P10/ANO0, P11/ANO1 ...
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V850ES/JG3-H, V850ES/JH3-H 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/4) Pin Alternate Function Name P00 INTP00 P01 INTP01 ...
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V850ES/JG3-H, V850ES/JH3-H Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (2/4) Pin Alternate Function Name P60 TOAB1T1/TIAB11/TOAB11/WAIT TOAB1T1/TIAB11/TOAB11 P61 TOAB1B1/TIAB10/TOAB10/RD TOAB1B1/TIAB10/TOAB10 P62 TOAB1T2/TIAB12/TOAB12/ASTB TOAB1T2/TIAB12/TOAB12 P63 TOAB1B2/TRGAB1/CS0 TOAB1B2/TRGAB1 P64 TOAB1T3/TIAB13/TOAB13/CS2 TOAB1T3/TIAB13/TOAB13 P65 TOAB1B3/EVTAB1/CS3 TOAB1B3/EVTAB1 ...
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V850ES/JG3-H, V850ES/JH3-H Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (3/4) Pin Alternate Function Name P913 TOAB1OFF/INTP16 TOAB1OFF/INTP16/A13 P914 TIAA51/TOAA51/INTP17 TIAA51/TOAA51/INTP17/A14 P915 TIAA50/TOAA50/INTP18 TIAA50/TOAA50/INTP18/A15 PCM0 WAIT PCM1 CLKOUT PCM2 HLDAK PCM3 HLDRQ PCS0 ...
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V850ES/JG3-H, V850ES/JH3-H Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (4/4) Pin Alternate Function Name − REGC − RESET − UDMF − UDPF − − − − ...
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V850ES/JG3-H, V850ES/JH3-H Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5 Data Output disable Input enable Type 10-D Data Open drain Output disable Note Input enable Type 10-N Data Open drain Output disable Note Input enable OCDM0 bit Note ...
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V850ES/JG3-H, V850ES/JH3-H 2.4 Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P10/ANO0 pin • P11/ANO1 pin • DDO pin (V850ES/JH3-H only) • P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO pin (V850ES/JG3-H only) R01UH0042EJ0400 Rev.4.00 ...
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V850ES/JG3-H, V850ES/JH3-H The CPU of the V850ES/JG3-H and V850ES/JH3-H is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 20.8 ns (operating with main clock (f ...
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V850ES/JG3-H, V850ES/JH3-H 3.2 CPU Register Set The registers of the V850ES/JG3-H and V850ES/JH3-H can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture ...
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V850ES/JG3-H, V850ES/JH3-H 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a ...
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V850ES/JG3-H, V850ES/JH3-H 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers ...
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V850ES/JG3-H, V850ES/JH3-H (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are ...
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V850ES/JG3-H, V850ES/JH3-H (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, ...
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V850ES/JG3-H, V850ES/JH3-H (4) Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit ...
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V850ES/JG3-H, V850ES/JH3-H Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 ...
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V850ES/JG3-H, V850ES/JH3-H (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those ...
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V850ES/JG3-H, V850ES/JH3-H 3.3 Operation Modes The V850ES/JG3-H and V850ES/JH3-H have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. ...
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V850ES/JG3-H, V850ES/JH3-H 3.4 Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.3 Memory map The areas shown below are reserved in the V850ES/JG3-H and V850ES/JH3-H. Figure 3-2. Data Memory Map (Physical Addresses) 03FFFFFFH (80 KB) 03FEC000H 03FEBFFFH Use prohibited 01000000H 00FFFFFFH External memory area (8 MB) 00800000H 007FFFFFH External ...
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V850ES/JG3-H, V850ES/JH3-H R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 Figure 3-3. Program Memory Map Use prohibited (program fetch prohibited area ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.4 Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (256 KB) 256 KB are allocated to addresses 00000000H to 0003FFFFH in the following products. Accessing addresses 00040000H ...
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V850ES/JG3-H, V850ES/JH3-H (c) Internal ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the following products. Accessing addresses 00080000H to 000FFFFFH is prohibited. μ • PD70F3762, 70F3767 R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 Figure 3-6. Internal ROM ...
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V850ES/JG3-H, V850ES/JH3-H (2) Internal RAM area are reserved as the internal RAM area. The V850ES/JG3-H and V850ES/JH3-H include a data-only RAM addition to the internal RAM. The RAM capacity of V850ES/JG3-H and ...
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V850ES/JG3-H, V850ES/JH3-H (b) Internal RAM (40 KB are allocated to addresses 03FF5000H to 03FFEFFFH in the following products. Accessing addresses 03FF0000H to 03FF4FFFH is prohibited. μ • PD70F3761, 70F3766 Physical address space (c) Internal RAM (48 KB) 48 ...
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V850ES/JG3-H, V850ES/JH3-H (d) Data-only RAM (8 KB) A data-only RAM allocated to addresses 00280000H to 00281FFFH in the V850ES/JG3-H and V850ES/JH3-H. Caution If using the data-only RAM area, the following two register setting are needed. • ...
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V850ES/JG3-H, V850ES/JH3-H (3) On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Physical address space Peripheral I/O registers that have functions to specify the operation mode for and monitor the ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.5 Recommended use of address space The architecture of the V850ES/JG3-H and V850ES/JH3-H requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address ...
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V850ES/JG3-H, V850ES/JH3-H (2) Data space With the V850ES/JG3-H and V850ES/JH3-H, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25 26-bit address is sign-extended ...
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V850ES/JG3-H, V850ES/JH3 ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.6 Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H Note 2 FFFFF006H Port DH register Note 2 FFFFF008H Port CS register FFFFF00AH Port CT register ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF09EH DMA destination address register 3H FFFFF0C0H DMA transfer count register 0 FFFFF0C2H DMA transfer count register 1 FFFFF0C4H DMA transfer count register 2 FFFFF0C6H DMA transfer count register 3 FFFFF0D0H DMA addressing control ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF126H Interrupt control register FFFFF128H Interrupt control register FFFFF12AH Interrupt control register FFFFF12CH Interrupt control register FFFFF12EH Interrupt control register FFFFF130H Interrupt control register FFFFF132H Interrupt control register FFFFF134H Interrupt control register FFFFF136H Interrupt ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF17CH Interrupt control register FFFFF17EH Interrupt control register FFFFF180H Interrupt control register FFFFF182H Interrupt control register FFFFF184H Interrupt control register FFFFF186H Interrupt control register FFFFF188H Interrupt control register FFFFF18AH Interrupt control register FFFFF18CH Interrupt ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF202H A/D converter channel specification register FFFFF203H A/D converter mode register 2 FFFFF204H Power-fail compare mode register FFFFF205H Power-fail compare threshold value register FFFFF210H A/D conversion result register 0 FFFFF211H A/D conversion result register ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF400H Port 0 register FFFFF402H Port 1 register Note 2 FFFFF404H Port 2 register FFFFF406H Port 3 register FFFFF408H Port 4 register FFFFF40AH Port 5 register FFFFF40CH Port 6 register FFFFF40EH Port 7 register ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF472H Port 9 function control register FFFFF472H Port 9 function control register L FFFFF473H Port 9 function control register H FFFFF484H Data wait control register 0 FFFFF488H Address wait control register FFFFF48AH Bus cycle ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF607H TMT0 option register 0 FFFFF608H TMT0 option register 1 FFFFF609H TMT0 option register 2 FFFFF60AH TMT0 capture/compare register 0 FFFFF60CH TMT0 capture/compare register 1 FFFFF60EH TMT0 counter read buffer register FFFFF610H TMT0 counter ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF664H TAA3 I/O control register 2 FFFFF665H TAA3 option register 0 FFFFF666H TAA3 capture/compare register 0 FFFFF668H TAA3 capture/compare register 1 FFFFF66AH TAA3 counter read buffer register FFFFF66CH TAA3 I/O control register4 FFFFF670H TAA4 ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFF80CH Internal oscillation mode register FFFFF810H DMA trigger factor register 0 FFFFF812H DMA trigger factor register 1 FFFFF814H DMA trigger factor register 2 FFFFF820H Power save mode register FFFFF822H Clock control register FFFFF824H Lock ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFFA24H UARTC2 status register FFFFFA26H UARTC2 receive data register FFFFFA26H UARTC2 receive data register L FFFFFA28H UARTC2 transmit data register FFFFFA28H UARTC2 transmit data register L FFFFFA2AH UARTC2 option control register 1 FFFFFA30H UARTC3 ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFFADAH Alarm minute set register FFFFFADBH Alarm time set register FFFFFADCH Alarm week set register FFFFFADDH RTC control register 0 FFFFFADEH RTC control register 1 FFFFFADFH RTC control register 2 FFFFFAE0H RTC control register ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFFD14H CSIF1 receive data register FFFFFD14H CSIF1 receive data register L FFFFFD16H CSIF1 transmit data register FFFFFD16H CSIF1 transmit data register L FFFFFD20H CSIF2 control register 0 FFFFFD21H CSIF2 control register 1 FFFFFD22H CSIF2 ...
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V850ES/JG3-H, V850ES/JH3-H Address Function Register Name FFFFFDA2H IIC control register 2 FFFFFDA3H Slave address register 2 FFFFFDA4H IIC clock select register 2 FFFFFDA5H IIC function expansion register 2 FFFFFDA6H IIC status register 2 FFFFFDAAH IIC flag register 2 FFFFFF40H USB ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.7 Programmable peripheral I/O registers The BPC register is used to select the programmable peripheral I/O register area. μ The BPC register is valid only PD70F3770, 70F3771. (1) Peripheral I/O area select control register (BPC) This register can ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.8 Special registers Special registers are registers that are protected from being written with illegal data due to a program loop. The V850ES/JG3-H and V850ES/JH3-H have the following eight special registers. • Power save control register (PSC) • ...
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V850ES/JG3-H, V850ES/JH3-H (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data ...
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V850ES/JG3-H, V850ES/JH3-H (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. ...
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V850ES/JG3-H, V850ES/JH3-H (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to ...
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V850ES/JG3-H, V850ES/JH3-H 3.4.9 Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JG3-H and V850ES/JH3-H. • System wait control register (VSWC) • On-chip debug mode register (OCDM) (V850ES/JG3-H only) • Watchdog ...
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V850ES/JG3-H, V850ES/JH3-H (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the ...
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V850ES/JG3-H, V850ES/JH3-H Peripheral Function C00 to I C02 IICS0 to IICS2 CRC CRCD CAN controller C0GMABT 31 C0GMABTD, C0MASKaL, C0MASKaH, C0LEC, C0INFO, C0ERC, C0IE, C0INTS, C0BRP, C0BTR, C0TS ...
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V850ES/JG3-H, V850ES/JH3-H (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt ...
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V850ES/JG3-H, V850ES/JH3-H 4.1 Features I/O ports • V850ES/JG3- tolerant/N-ch open-drain output selectable: 22 • V850ES/JH3- tolerant/N-ch open-drain output selectable: 25 Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JG3-H features a total ...
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V850ES/JG3-H, V850ES/JH3-H Figure 4-1. Port Configuration Diagram (V850ES/JG3-H) Port 0 Port 1 Port 3 Port 4 Port 5 Figure 4-2. Port Configuration Diagram (V850ES/JH3-H) Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 ...
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V850ES/JG3-H, V850ES/JH3-H 4.3 Port Configuration Item Control register Port n mode register (PMn CM, CT, DL) Port n mode control register (PMCn CM, CT, DL) ...
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V850ES/JG3-H, V850ES/JH3-H (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that ...
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V850ES/JG3-H, V850ES/JH3-H (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode ...
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V850ES/JG3-H, V850ES/JH3-H (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of ...
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V850ES/JG3-H, V850ES/JH3-H (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be ...
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V850ES/JG3-H, V850ES/JH3-H (7) Port setting Set a port as illustrated below. Figure 4-3. Setting of Each Register and Pin Function Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.1 Port 0 Port 0 is 4-bit (V850ES/JG3-H)/6-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H − P00 8 ...
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V850ES/JG3-H, V850ES/JH3-H (2) Port 0 mode register (PM0) (a) V850ES/JG3-H After reset: FFH 7 PM0 1 PM0n 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH 7 PM0 1 PM0n 0 Output mode 1 Input mode R01UH0042EJ0400 Rev.4.00 ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port 0 mode control register (PMC0) (a) V850ES/JG3-H After reset: 00H R/W 7 PMC0 0 PMC05 0 I/O port 1 INTP04 input PMC04 0 I/O port 1 INTP03 input PMC03 0 I/O port 1 INTP02 input/ADTRG input/UCLK ...
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V850ES/JG3-H, V850ES/JH3-H (b) V850ES/JH3-H After reset: 00H 7 PMC0 0 PMC05 0 I/O port 1 INTP04 input PMC04 0 I/O port 1 INTP03 input PMC03 0 I/O port 1 INTP02 input/ADTRG input/UCLK input PMC02 0 I/O port 1 NMI input ...
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V850ES/JG3-H, V850ES/JH3-H (5) Port 0 function control expansion register (PFCE0) After reset: 00H 7 PFCE0 0 Remark For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function specifications. (6) Port 0 alternate function specifications PFCE03 PFC03 0 ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.2 Port 1 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H P10 3 3 P11 ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.3 Port 2 (V850ES/JH3-H only) Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port 2 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H − P20 ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port 2 mode control register (PMC2) After reset: 00H 7 PMC2 0 PMC25 0 I/O port 1 INTP06 input PMC24 0 I/O port 1 INTP05 input PMC23 0 I/O port 1 SCKF2 I/O/KR5 input/RTP05 output PMC22 0 ...
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V850ES/JG3-H, V850ES/JH3-H (5) Port 2 function control expansion register (PFCE2) After reset: 00H 7 PFCE2 0 Remark For details of alternate function specification, see 4.3.3 (6) Port 2 alternate function specifications. (6) Port 2 alternate function specifications PFCE23 PFC23 0 ...
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V850ES/JG3-H, V850ES/JH3-H (7) Port 2 function register (PF2) After reset: 00H R/W 7 PF2 0 PF2n 0 Normal output 1 N-ch open-drain output R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 Address: FFFFFC64H PF25 PF24 PF23 Control of ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.4 Port 3 Port 10-bit port that controls I/O in 1-bit units. Port 3 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H P30 25 37 P31 26 38 P32 27 ...
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V850ES/JG3-H, V850ES/JH3-H After reset: 00H PMC3 PMC37 PMC37 0 I/O port 1 RXDC3 input/SDA00 I/O/CRXD input PMC36 0 I/O port 1 TXDC3 output/SCL00 I/O/CTXD0 output PMC35 0 I/O port 1 TIAA11 input/TOAA11 output/RTC1HZ output PMC34 0 I/O port 1 TIAA10 ...
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V850ES/JG3-H, V850ES/JH3-H (4) Port 3 function control register (PFC3) After reset: 00H PFC3 PFC37 Remark For details of alternate function specification, see 4.3.4 (6) Port 3 alternate function specifications. (5) Port 3 function control expansion register (PFCE3) After reset: 00H ...
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V850ES/JG3-H, V850ES/JH3-H PFCE34 PFC34 Note TOAA1OFF and INTP09 are alternate functions. When using the pin as the TOAA1OFF pin, disable INTP09 pin edge detection, which is the alternate function. Also, when using ...
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V850ES/JG3-H, V850ES/JH3-H (7) Port 3 function register (PF3) After reset: 00H PF3 PF37 PF3n 0 Normal output (CMOS output) 1 N-ch open-drain output R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 R/W Address: FFFFFC66H PF36 PF35 PF34 PF33 Control of normal output or ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.5 Port 4 Port 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H P40 22 29 P41 23 30 P42 24 ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port 4 mode control register (PMC4) After reset: 00H PMC4 0 PMC42 0 I/O port 1 SCKF0 I/O/INTP10 input PMC41 0 I/O port 1 SOF0 output/RXDC4 input/SCL01 I/O PMC40 0 I/O port 1 SIF0 input/TXDC4 output/SDA01 I/O ...
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V850ES/JG3-H, V850ES/JH3-H (6) Port 4 alternate function specifications PFC42 0 1 PFCE41 PFC41 PFCE40 PFC40 (7) Port 4 function register (PF4) After reset: 00H ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.6 Port 5 Port 5 is 6-bit (V850ES/JG3-H)/2-bit (V850ES/JH3-H) port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H P50 35 47 P51 36 48 − ...
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V850ES/JG3-H, V850ES/JH3-H (1) Port 5 register (P5) (a) V850ES/JG3-H After reset: 00H (output latch P5n 0 Outputs 0. 1 Outputs 1. (b) V850ES/JH3-H After reset: 00H (output latch P5n 0 Outputs 0. 1 Outputs 1. R01UH0042EJ0400 ...
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V850ES/JG3-H, V850ES/JH3-H (2) Port 5 mode register (PM5) (a) V850ES/JG3-H After reset: FFH PM5 1 PM5n 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH PM5 1 PM5n 0 Output mode 1 Input mode R01UH0042EJ0400 Rev.4.00 Sep 30, ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port 5 mode control register (PMC5) (a) V850ES/JG3-H After reset: 00H PMC5 0 PMC56 0 I/O port 1 INTP05 input PMC55 0 I/O port 1 SCKF2 I/O/KR5 input/RTP05 output PMC54 0 I/O port 1 SOF2 output/KR4 input/RTP04 ...
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V850ES/JG3-H, V850ES/JH3-H (4) Port 5 function control register (PFC5) (a) V850ES/JG3-H After reset: 00H PFC5 0 (b) V850ES/JH3-H After reset: 00H PFC5 0 Remark For details of alternate function specification, see 4.3.6 (6) Port 5 alternate function specifications. (5) Port ...
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V850ES/JG3-H, V850ES/JH3-H Note 1 Note 1 PFCE54 PFC54 Note 1 Note 1 PFCE53 PFC53 Note1 Note1 PFCE52 PFC52 ...
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V850ES/JG3-H, V850ES/JH3-H (7) Port 5 function register (PF5) (a) V850ES/JG3-H After reset: 00H PF5 0 PF5n 0 Normal output (CMOS output) 1 N-ch open-drain output (b) V850ES/JH3-H After reset: 00H PF5 0 PF5n 0 Normal output (CMOS output) 1 N-ch ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.7 Port 6 Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H P60 65 90 P61 ...
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V850ES/JG3-H, V850ES/JH3-H (2) Port 6 mode register (PM6) After reset: FFH PM6 1 PM6n 0 Output mode 1 Input mode (3) Port 6 mode control register (PMC6) After reset: 00H PMC6 0 PMC65 0 I/O port 1 TOAB1B3 output/EVTAB1 input/CS3 ...
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V850ES/JG3-H, V850ES/JH3-H (4) Port 6 function control register (PFC6) After reset: 00H PFC6 0 Remark For details of alternate function specification, see 4.3.7 (6) Port 6 alternate function specifications. (5) Port 6 function control expansion register (PFCE6) (a) V850ES/JG3-H After ...
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V850ES/JG3-H, V850ES/JH3-H Note PFCE63 PFC63 Note PFCE62 PFC62 PFCE61 PFC61 Note PFCE60 PFC60 ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.8 Port 7 Port 12-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H P70 100 128 P71 ...
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V850ES/JG3-H, V850ES/JH3-H (2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L) After reset: FFH PM7H 1 PM7L PM77 PM7n 0 Output mode 1 Input mode Caution When using the P7n pin as its alternate function (ANIn ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.9 Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H P90 42 54 P91 ...
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V850ES/JG3-H, V850ES/JH3-H (1) Port 9 register (P9) After reset: 0000H (output latch (P9H) P915 (P9L) P97 P9n 0 1 Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the higher 8 ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port 9 mode control register (PMC9) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 ...
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V850ES/JG3-H, V850ES/JH3-H PMC97 0 I/O port 1 SIF1 input/TIAA20 input/TOAA20 output/A7 output PMC96 0 I/O port 1 TIAA21 input/TOAA21 output/INTP11 input/A6 output PMC95 0 I/O port 1 TIAA30 input/TOAA30 output/A5 output PMC94 0 I/O port 1 TIAA31 input/TOAA31 output/TENC00 input/EVTT0 ...
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V850ES/JG3-H, V850ES/JH3-H (4) Port 9 function control register (PFC9) <R> Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after setting the PFC9 register to the FCDFH ...
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V850ES/JG3-H, V850ES/JH3-H (5) Port 9 function control expansion register (PFCE9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for <R> all 16 bits at once after setting the PFC9 register to FCDFH ...
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V850ES/JG3-H, V850ES/JH3-H (6) Port 9 alternate function specifications PFCE915 PFC915 PFCE914 PFC914 Note PFC913 0 TOAB1OFF input/INTP16 input Note 1 A13 output Note PFC912 ...
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V850ES/JG3-H, V850ES/JH3-H Note PFCE98 PFC98 PFCE97 PFC97 PFCE96 PFC96 Note PFCE95 PFC95 ...
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V850ES/JG3-H, V850ES/JH3-H PFCE92 PFC92 PFCE91 PFC91 PFCE90 PFC90 Note V850ES/JH3-H only R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 ...
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V850ES/JG3-H, V850ES/JH3-H (7) Port 9 function register (PF9) After reset: 0000H 15 0 PF9 (PF9L) 0 PF9n 0 Normal output (CMOS output) 1 N-ch open-drain output Caution When output pins P90, P91 are pulled bit to 1. ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.10 Port CM Port CM is 1-bit (V850ES/JG3-H)/4-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H − PCM0 89 ...
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V850ES/JG3-H, V850ES/JH3-H (2) Port CM mode register (PMCM) (a) V850ES/JG3-H After reset: FFH PMCM 1 PMCM1 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH PMCM 1 PMCMn 0 Output mode 1 Input mode R01UH0042EJ0400 Rev.4.00 Sep 30, ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port CM mode control register (PMCCM) (a) V850ES/JG3-H After reset: 00H PMCCM 0 PMCCM1 0 1 (b) V850ES/JH3-H After reset: 00H PMCCM 0 PMCCM3 0 1 PMCCM2 0 1 PMCCM1 0 1 PMCCM0 0 1 R01UH0042EJ0400 Rev.4.00 ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.11 Port CS (V850ES/JH3-H only) Port 3-bit port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H − PCS0 ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port CS mode control register (PMCCS) After reset: 00H PMCCS 0 PMCCS3 0 1 PMCCS2 0 1 PMCCS0 0 1 R01UH0042EJ0400 Rev.4.00 Sep 30, 2010 R/W Address: FFFFF048H PMCCS3 PMCCS2 Specification of PCS3 pin ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.12 Port CT Port 2-bit (V850ES/JG3-H)/4-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H PCT0 58 ...
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V850ES/JG3-H, V850ES/JH3-H (2) Port CT mode register (PMCT) (a) V850ES/JG3-H After reset: FFH PMCT 1 PMCTn 0 Output mode 1 Input mode (b) V850ES/JH3-H After reset: FFH PMCT 1 PMCTn 0 Output mode 1 Input mode R01UH0042EJ0400 Rev.4.00 Sep 30, ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port CT mode control register (PMCCT) (a) V850ES/JG3-H After reset: 00H PMCCT 0 PMCCT1 0 1 PMCCT0 0 1 (b) V850ES/JH3-H After reset: 00H PMCCT 0 PMCCT6 0 1 PMCCT4 0 1 PMCCT1 0 1 PMCCT0 0 ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.13 Port DH (V850ES/JH3-H only) Port 8-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H − PDH0 ...
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V850ES/JG3-H, V850ES/JH3-H (1) Port DH register (PDH) After reset: 00H (output latch) PDH PDH7 PDHn 0 Outputs 0. 1 Outputs 1. (2) Port DH mode register (PMDH) After reset: FFH PMDH PMDH7 PMDHn 0 Output mode 1 Input mode (3) ...
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V850ES/JG3-H, V850ES/JH3-H 4.3.14 Port DL Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JG3-H JH3-H PDL0 71 98 PDL1 ...
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V850ES/JG3-H, V850ES/JH3-H (1) Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 (PDLL) PDL7 PDLn 0 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 ...
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V850ES/JG3-H, V850ES/JH3-H (3) Port DL mode control register (PMCDL) After reset: 0000H 15 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 (PMCDLL) PMCDLn 0 1 Remarks 1. The PMCDL register can be ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Note 1 P00 INTP00 Input P00 = Setting not required PM00 = Setting not required PMC00 = 1 Note 1 P01 INTP01 Input P01 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Note P22 SOF2 Output P22 = Setting not required PM22 = Setting not required PMC22= 1 KR4 Input P22 = Setting not required PM22 = Setting not required PMC22= ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P34 TIAA10 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 TOAA10 Output P34 = Setting not required PM34 = Setting not required PMC34 ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P50 TIAB01 Input P50 = Setting not required PM50 = Setting not required PMC50 = 1 KR0 Input P50 = Setting not required PM50 = Setting not required PMC50 ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Note P55 SCKF2 I/O P55 = Setting not required PM55 = Setting not required PMC55 = 1 KR5 Input P55 = Setting not required PM55 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P70 ANI0 Input P70 = Setting not required PM70 = 1 P71 ANI1 Input P71 = Setting not required PM71 = 1 P72 ANI2 Input P72 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P93 TECR0 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 TIT00 Input P93 = Setting not required PM93 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P99 SCKF1 I/O P99 = Setting not required PM99 = Setting not required PMC99 = 1 INTP14 Input P99 = Setting not required PM99 = Setting not required PMC99 ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Note PCM0 WAIT Input PCM0 = Setting not required PMCM0 = Setting not required PMCCM0 = 1 PCM1 CLKOUT Output PCM1 = Setting not required PMCM1 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PDL5 AD5 I/O PDL5 = Setting not required PMDL5 = Setting not required Note FLMD1 Input PDL5 = Setting not required PMDL5 = Setting not required PDL6 AD6 I/O ...
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V850ES/JG3-H, V850ES/JH3-H 4.5 Cautions 4.5.1 Cautions on setting port pins (1) In the V850ES/JG3-H and V850ES/JH3-H, the general-purpose port functions share pins with several peripheral function I/O pins. Switch between the general-purpose port (port mode) and the peripheral function I/O ...
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V850ES/JG3-H, V850ES/JH3-H The setting procedure that may cause malfunction on switching from the P41 pin to the SCL01 pin is shown below. Setting Procedure <1> <2> <3> <4> <2> communication may be affected since the alternate-function ...
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V850ES/JG3-H, V850ES/JH3-H Figure 4-4. Example of Switching from P02 to NMI (Incorrect) PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Remark [Example 2] Switching from external pin (NMI) ...
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V850ES/JG3-H, V850ES/JH3-H 4.5.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port ...
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V850ES/JG3-H, V850ES/JH3-H 4.5.3 Cautions on on-chip debug pins (V850ES/JG3-H only) The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P56/INTP05/DRST pin is initialized to function as an on-chip debug pin ...
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V850ES/JG3-H, V850ES/JH3-H The V850ES/JG3-H and V850ES/JH3-H are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from multiplexed bus output with a minimum ...
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V850ES/JG3-H, V850ES/JH3-H 5.2 Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. V850ES/JH3-H Bus Control Pins (Multiplexed Bus) Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 A16 ...
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V850ES/JG3-H, V850ES/JH3-H 5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows. Table 5-4. Pin Statuses ...
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V850ES/JG3-H, V850ES/JH3-H 5.3 Memory Block Function The 16 MB external memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB from the lowest of the memory space. The programmable wait function and bus cycle operation ...
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V850ES/JG3-H, V850ES/JH3-H 5.4 Bus Access 5.4.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data ...
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V850ES/JG3-H, V850ES/JH3-H 5.4.3 Access by bus size The V850ES/JG3-H and V850ES/JH3-H access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32- bit units. The bus size is as follows. • The bus size of the on-chip peripheral ...
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V850ES/JG3-H, V850ES/JH3-H (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n Byte data External data bus (b) 8-bit data bus width <1> Access to even address (2n) ...
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V850ES/JG3-H, V850ES/JH3-H (3) Halfword access (16 bits) (a) 16-bit data bus width <1> Access to even address (2n Halfword data External data bus (b) 8-bit data bus width <1> Access to even ...
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V850ES/JG3-H, V850ES/JH3-H (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External ...
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V850ES/JG3-H, V850ES/JH3-H (a) 16-bit data bus width (2/2) <3> Access to address ( First access Address Word data External data ...
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V850ES/JG3-H, V850ES/JH3-H (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External data Word data bus <2> ...
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V850ES/JG3-H, V850ES/JH3-H (b) 8-bit data bus width (2/2) <3> Access to address ( First access Address Word data External data ...
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V850ES/JG3-H, V850ES/JH3-H 5.5 Wait Function 5.5.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/ seven data wait states can be inserted in the bus cycle that is ...
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V850ES/JG3-H, V850ES/JH3-H 5.5.2 External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Note 1 Note 2 ...
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V850ES/JG3-H, V850ES/JH3-H 5.5.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by ...
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V850ES/JG3-H, V850ES/JH3-H 5.5.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS0, CS2, CS3). If ...
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V850ES/JG3-H, V850ES/JH3-H 5.6 Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select. By ...
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V850ES/JG3-H, V850ES/JH3-H 5.7 Bus Hold Function (V850ES/JH3-H only) 5.7.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to their alternate function. When the HLDRQ pin is asserted (low level), indicating that ...
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V850ES/JG3-H, V850ES/JH3-H 5.7.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status <5> ...
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V850ES/JG3-H, V850ES/JH3-H 5.8 Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction ...
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V850ES/JG3-H, V850ES/JH3-H 5.9 Bus Timing Figure 5-4. Multiplexed/Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access CLKOUT Note 1 A23 ASTB Note 2 CS3, CS2, CS0 WAIT AD15 to AD0 8-bit ...
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V850ES/JG3-H, V850ES/JH3-H Figure 5-6. Multiplexed/Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T1 CLKOUT Note 1 A23 to A0 ASTB Note 2 CS3, CS2, CS0 WAIT A1 AD15 to AD0 WR1, WR0 11 8-bit Access AD15 to AD8 ...
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V850ES/JG3-H, V850ES/JH3-H Figure 5-8. Multiplexed/Separate Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) (V850ES/JH3-H only) T1 CLKOUT HLDRQ HLDAK A23 to A0 AD15 to AD0 A1 ASTB RD Note 2 CS3, CS2, CS0 Notes 1. This idle state (TI) ...
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode f = 3.0 to 6.0 MHz (f = 3.0 to 6.0 MHz • In PLL ...