UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet
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UPD70F3744GJ-GAE-AX Summary of contents
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V850ES/JJ3 32 RENESAS MCU V850ES/JJ3 Microcontrollers μPD70F3743 μPD70F3744 μPD70F3745 μPD70F3746 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care to prevent chattering noise ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/JJ3 and design application systems using the V850ES/JJ3. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JJ3 ...
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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JJ3 Documents related to development tools Document Name V850ES Architecture User’s Manual V850ES/JJ3 Hardware User’s Manual ...
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Caution:This product uses SuperFlash IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America. EEPROM ...
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CHAPTER 1 INTRODUCTION....................................................................................................................1 1.1 General .......................................................................................................................................1 1.2 Features......................................................................................................................................3 1.3 Application Fields......................................................................................................................4 1.4 Ordering Information.................................................................................................................4 1.5 Pin Configuration (Top View) ...................................................................................................5 1.6 Function Block Configuration ..................................................................................................7 1.6.1 Internal block diagram..................................................................................................................7 1.6.2 Internal units ................................................................................................................................8 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 11 2.1 ...
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Port CS ....................................................................................................................................111 4.3.13 Port CT ....................................................................................................................................113 4.3.14 Port DH ....................................................................................................................................115 4.3.15 Port DL.....................................................................................................................................117 4.4 Block Diagrams..................................................................................................................... 120 4.5 Port Register Settings When Alternate Function Is Used ................................................ 152 4.6 Cautions ................................................................................................................................ 161 4.6.1 Cautions on setting port pins....................................................................................................161 ...
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Overview................................................................................................................................ 205 7.2 Functions............................................................................................................................... 205 7.3 Configuration ........................................................................................................................ 206 7.4 Registers ............................................................................................................................... 208 7.5 Operation............................................................................................................................... 220 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) .............................................................221 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) .................................................231 ...
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Configuration ........................................................................................................................ 412 11.3 Registers ............................................................................................................................... 413 11.4 Operation............................................................................................................................... 415 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 416 12.1 Function................................................................................................................................. 416 12.2 Configuration ........................................................................................................................ 417 12.3 Registers ............................................................................................................................... 419 12.4 Operation............................................................................................................................... 421 12.5 Usage 422 12.6 Cautions ................................................................................................................................ 422 CHAPTER ...
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UART reception .......................................................................................................................487 15.6.8 Reception errors ......................................................................................................................488 15.6.9 Parity types and operations......................................................................................................490 15.6.10 Receive data noise filter...........................................................................................................491 15.7 Dedicated Baud Rate Generator ......................................................................................... 492 15.8 Cautions ................................................................................................................................ 500 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB).................................................... 501 16.1 Mode Switching ...
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Stop condition ..........................................................................................................................579 17.6.6 Wait state.................................................................................................................................580 17.6.7 Wait state cancellation method ................................................................................................582 2 17 Interrupt Request Signals (INTIICn) .............................................................................. 583 17.7.1 Master device operation...........................................................................................................583 17.7.2 Slave device operation (when receiving slave address data (address match)) ........................586 17.7.3 ...
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Priorities of maskable interrupts...............................................................................................664 19.3.4 Interrupt control register (xxICn) ..............................................................................................668 19.3.5 Interrupt mask registers (IMR0 to IMR4) ........................................................................670 19.3.6 In-service priority register (ISPR) .............................................................................................672 19.3.7 ID flag ......................................................................................................................................673 19.3.8 Watchdog timer mode register 2 (WDTM2) .............................................................................673 ...
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Registers to Check Reset Source....................................................................................... 712 22.3 Operation............................................................................................................................... 713 22.3.1 Reset operation via RESET pin ...............................................................................................713 22.3.2 Reset operation by watchdog timer 2.......................................................................................715 22.3.3 Reset operation by low-voltage detector ..................................................................................717 22.3.4 Operation after reset release ...................................................................................................718 22.3.5 Reset function ...
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Pin processing .........................................................................................................................762 27.5.6 Internal resources used ...........................................................................................................763 CHAPTER 28 ON-CHIP DEBUG FUNCTION ..................................................................................... 764 28.1 Debugging with DCU ............................................................................................................ 765 28.1.1 Connection circuit example.........................................................................................................765 28.1.2 Interface signals .........................................................................................................................765 28.1.3 Maskable functions .....................................................................................................................767 28.1.4 Register ......................................................................................................................................767 28.1.5 Operation....................................................................................................................................769 28.1.6 ...
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V850ES/JJ3 RENESAS MCU The V850ES/JJ3 is one of the products in the Renesas Electronics V850 single-chip microcontrollers designed for low- power operation for real-time control applications. 1.1 General The V850ES/JJ3 is a 32-bit single-chip microcontroller that includes the V850ES CPU ...
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V850ES/JJ3 Part Number Internal Flash memory memory RAM Memory Logical space space External memory area External bus interface Address bus: 24 bits Data bus: 8/16 bits Multiplex bus mode/separate bus mode Chip select signal bits × 32 registers ...
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V850ES/JJ3 1.2 Features Minimum instruction execution time: 31.25 ns (operating with main clock (f General-purpose registers: CPU features: Memory space: • Internal memory: • External bus interface: Interrupts and exceptions: I/O lines: Timer function: Real-time output port: Serial interface: A/D ...
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V850ES/JJ3 Package: 1.3 Application Fields Home audio, printers, digital home electronics, other consumer devices 1.4 Ordering Information Part Number μ PD70F3743GJ-GAE-AX μ PD70F3744GJ-GAE-AX μ PD70F3745GJ-GAE-AX μ PD70F3746GJ-GAE-AX Remark The V850ES/JJ3 microcontrollers are lead-free products. R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 144-pin ...
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V850ES/JJ3 1.5 Pin Configuration (Top View) 144-pin plastic LQFP (fine pitch) (20 × 20) μ PD70F3743GJ-GAE-AX μ PD70F3745GJ-GAE- REF0 P10/ANO0 3 P11/ANO1 REF1 P00/TIP61/TOP61 6 P01/TIP60/TOP60 7 Note 1 FLMD0 8 V ...
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V850ES/JJ3 Pin names A0 to A23: Address bus AD0 to AD15: Address/data bus ADTRG: A/D trigger input ANI0 to ANI15: Analog input ANO0, ANO1: Analog output ASCKA0: Asynchronous serial clock ASTB: Address strobe Analog reference voltage ...
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V850ES/JJ3 1.6 Function Block Configuration 1.6.1 Internal block diagram NMI INTC INTP0 to INTP8 16-bit timer/ TIQ00 to TIQ03 counter Q: TOQ00 to TOQ03 1 ch TIP00 to TIP80, 16-bit timer/ TIP01 to TIP81 counter P: TOP00 to TOP80, 9 ...
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V850ES/JJ3 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits ...
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V850ES/JJ3 (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 ...
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V850ES/JJ3 (19) Ports The general-purpose port functions and control pin functions are listed below. Port I/O P0 7-bit I/O P1 2-bit I/O P3 10-bit I/O P4 3-bit I/O P5 6-bit I/O P6 16-bit I/O P7 16-bit I/O P8 2-bit I/O ...
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V850ES/JJ3 2.1 List of Pin Functions The names and functions of the pins of the V850ES/JJ3 are described below. There are three types of pin I/O buffer power supplies: AV power supplies and the pins is described below. Power Supply ...
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V850ES/JJ3 (1) Port pins Pin Name Pin No. I/O P00 6 I/O P01 7 P02 17 P03 18 P04 19 Note P05 20 P06 21 P10 3 I/O P11 4 P30 25 I/O P31 26 P32 27 P33 28 P34 ...
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V850ES/JJ3 Pin Name Pin No. I/O P60 43 I/O P61 44 P62 45 P63 46 P64 47 P65 48 P66 49 P67 50 P68 51 P69 52 P610 53 P611 54 P612 55 P613 56 P614 57 P615 58 P70 ...
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V850ES/JJ3 Pin Name Pin No. I/O P90 61 I/O P91 62 P92 63 P93 64 P94 65 P95 66 P96 67 P97 68 P98 69 P99 70 P910 71 P911 72 P912 73 P913 74 P914 75 P915 76 PCD0 ...
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V850ES/JJ3 Pin Name Pin No. I/O PCT0 95 I/O PCT1 96 PCT2 97 PCT3 98 PCT4 99 PCT5 100 PCT6 101 PCT7 102 PDH0 121 I/O PDH1 122 PDH2 123 PDH3 124 PDH4 125 PDH5 126 PDH6 127 PDH7 128 ...
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V850ES/JJ3 (2) Non-port pins Pin Name Pin No. I Output A10 71 A11 72 A12 73 A13 74 A14 75 ...
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V850ES/JJ3 Pin Name Pin No. I/O ANI0 144 Input ANI1 143 ANI2 142 ANI3 141 ANI4 140 ANI5 139 ANI6 138 ANI7 137 ANI8 136 ANI9 135 ANI10 134 ANI11 133 ANI12 132 ANI13 131 ANI14 130 ANI15 129 ANO0 ...
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V850ES/JJ3 Pin Name Pin No. I/O HLDAK 87 Output HLDRQ 88 Input INTP0 18 Input INTP1 19 INTP2 20 INTP3 21 INTP4 74 INTP5 75 INTP6 76 INTP7 26 INTP8 59 Note 1 KR0 37 Input Note 1 KR1 38 ...
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V850ES/JJ3 Pin Name Pin No. I/O RXDA0 26 Input RXDA1 62 RXDA2 36 RXDA3 59 SCKB0 24 I/O SCKB1 70 SCKB2 42 SCKB3 73 SCKB4 27 SCKB5 51 SCL00 36 I/O SCL01 23 SCL02 62 SDA00 35 I/O SDA01 22 ...
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V850ES/JJ3 Pin Name Pin No. I/O TIP41 63 Input TIP50 76 TIP51 75 TIP60 7 TIP61 6 TIP70 52 TIP71 53 TIP80 55 TIP81 56 TIQ00 40 TIQ01 37 TIQ02 38 TIQ03 39 TOP00 27 Output TOP01 28 TOP10 29 ...
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V850ES/JJ3 Pin Name Pin No. I/O − − WAIT 85 Input WR0 95 Output WR1 Input − XT1 15 Input − XT2 16 R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Function ...
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V850ES/JJ3 2.2 Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Pin Name When Power Is Turned Note 1 On P05/DRST Pulled down P10/ANO0, P11/ANO1 Hi-Z P53/DDO ...
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V850ES/JJ3 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Pin Alternate Function P00 TIP61/TOP61 P01 TIP60/TOP60 P02 NMI P03 INTP0/ADTRG P04 INTP1 P05 INTP2/DRST P06 INTP3 ANO0, ANO1 P10, P11 P30 TXDA0/SOB4 P31 RXDA0/INTP7/SIB4 ...
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V850ES/JJ3 Pin Alternate Function P60 to P65 RTP10 to RTP15 P66 SIB5 P67 SOB5 P68 SCKB5 P69 TIP70/TOP70 P610 TIP71 P611 TOP71 P612 TIP80/TOP80 P613 TIP81/TOP81 P614, P615 P70 to P715 ANI0 to ANI15 P80 RXDA3, INTP8 P81 TXDA3 P90 ...
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V850ES/JJ3 Pin Alternate Function PCT0, PCT1 WR0, WR1 PCT2, PCT3 PCT4 RD PCT5 PCT6 ASTB PCT7 PDH0 to PDH7 A16 to A23 PDL0 to PDL4 AD0 to AD4 PDL5 AD5/FLMD1 PDL6 to AD6 to AD15 PDL15 AV REF0 AV REF1 ...
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V850ES/JJ3 Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5 Data Output disable Input enable Type 10-D Data Open drain Output disable Note Input enable Type 10-G Data Open drain Output disable Input enable Note Hysteresis characteristics are not ...
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V850ES/JJ3 2.4 Cautions When the power is turned on, the following pin may output an undefined level temporarily, even during reset. • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 CHAPTER 2 PIN FUNCTIONS Page 27 of 892 ...
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V850ES/JJ3 The CPU of the V850ES/JJ3 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 31.25 ns (at 32 MHz operation) Memory space Program (physical ...
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V850ES/JJ3 3.2 CPU Register Set The registers of the V850ES/JJ3 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User's Manual. (1) ...
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V850ES/JJ3 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data ...
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V850ES/JJ3 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed ...
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V850ES/JJ3 (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved ...
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V850ES/JJ3 (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and ...
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V850ES/JJ3 (4) Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of ...
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V850ES/JJ3 Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when ...
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V850ES/JJ3 (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of ...
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V850ES/JJ3 3.3 Operation Modes The V850ES/JJ3 has the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to ...
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V850ES/JJ3 3.4 Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and an internal ROM area, plus an internal RAM area, are supported in a linear address ...
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V850ES/JJ3 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore ...
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V850ES/JJ3 3.4.3 Memory map The areas shown below are reserved in the V850ES/JJ3. Figure 3-2. Data Memory Map (Physical Addresses (64 KB ...
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V850ES/JJ3 R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 3-3. Program Memory Map Use prohibited (program fetch prohibited area ...
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V850ES/JJ3 3.4.4 Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (384 KB) 384 KB are allocated to addresses 00000000H to 0005FFFFH in the Accessing addresses 00060000H to 000FFFFFH is ...
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V850ES/JJ3 (c) Internal ROM (768 KB) 768 KB are allocated to addresses 00000000H to 000BFFFFH in the Accessing addresses 000C0000H to 000FFFFFH is prohibited. (d) Internal ROM (1024 KB) 1024 KB are allocated to addresses 00000000H to 000FFFFFH in the ...
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V850ES/JJ3 (2) Internal RAM area are reserved as the internal RAM area. (a) Internal RAM (32 KB are allocated to addresses 03FF7000H to 03FFEFFFH in the Accessing addresses 03FF0000H to 03FF6FFFH is prohibited. Physical ...
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V850ES/JJ3 (c) Internal RAM (60 KB are allocated to addresses 03FF0000H to 03FFEFFFH in the Physical address space R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 3-10. Internal RAM Area (60 KB) Logical address space ...
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V850ES/JJ3 (3) On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Physical address space Peripheral I/O registers that have functions to specify the operation mode for and monitor the status ...
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V850ES/JJ3 3.4.5 Recommended use of address space The architecture of the V850ES/JJ3 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this ...
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V850ES/JJ3 (a) Application example of wraparound (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, ...
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V850ES/JJ3 ...
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V850ES/JJ3 3.4.6 Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DLL register FFFFF005H Port DLH register FFFFF006H Port DH register FFFFF008H Port CS register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF00EH Port CD ...
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V850ES/JJ3 Address Function Register Name FFFFF0C2H DMA transfer count register 1 FFFFF0C4H DMA transfer count register 2 FFFFF0C6H DMA transfer count register 3 FFFFF0D0H DMA addressing control register 0 FFFFF0D2H DMA addressing control register 1 FFFFF0D4H DMA addressing control register ...
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V850ES/JJ3 Address Function Register Name FFFFF132H Interrupt control register FFFFF134H Interrupt control register FFFFF136H Interrupt control register FFFFF138H Interrupt control register FFFFF13AH Interrupt control register FFFFF13CH Interrupt control register FFFFF13EH Interrupt control register FFFFF140H Interrupt control register FFFFF142H Interrupt control ...
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V850ES/JJ3 Address Function Register Name FFFFF198H Interrupt control register FFFFF19AH Interrupt control register FFFFF19CH Interrupt control register FFFFF19EH Interrupt control register FFFFF1A0H Interrupt control register FFFFF1A2H Interrupt control register FFFFF1A4H Interrupt control register FFFFF1A6H Interrupt control register FFFFF1A8H Interrupt control ...
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V850ES/JJ3 Address Function Register Name FFFFF228H A/D conversion result register 12 FFFFF229H A/D conversion result register 12H FFFFF22AH A/D conversion result register 13 FFFFF22BH A/D conversion result register 13H FFFFF22CH A/D conversion result register 14 FFFFF22DH A/D conversion result register ...
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V850ES/JJ3 Address Function Register Name FFFFF422H Port 1 mode register FFFFF426H Port 3 mode register FFFFF426H Port 3 mode register L FFFFF427H Port 3 mode register H FFFFF428H Port 4 mode register FFFFF42AH Port 5 mode register FFFFF42CH Port 6 ...
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V850ES/JJ3 Address Function Register Name FFFFF540H TMQ0 control register 0 FFFFF541H TMQ0 control register 1 FFFFF542H TMQ0 I/O control register 0 FFFFF543H TMQ0 I/O control register 1 FFFFF544H TMQ0 I/O control register 2 FFFFF545H TMQ0 option register 0 FFFFF546H TMQ0 ...
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V850ES/JJ3 Address Function Register Name FFFFF5C5H TMP3 option register 0 FFFFF5C6H TMP3 capture/compare register 0 FFFFF5C8H TMP3 capture/compare register 1 FFFFF5CAH TMP3 counter read buffer register FFFFF5D0H TMP4 control register 0 FFFFF5D1H TMP4 control register 1 FFFFF5D2H TMP4 I/O control ...
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V850ES/JJ3 Address Function Register Name FFFFF612H TMP8 I/O control register 0 FFFFF613H TMP8 I/O control register 1 FFFFF614H TMP8 I/O control register 2 FFFFF615H TMP8 option register 0 FFFFF616H TMP8 capture/compare register 0 FFFFF618H TMP8 capture/compare register 1 FFFFF61AH TMP8 ...
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V850ES/JJ3 Address Function Register Name FFFFF891H Low-voltage detection level select register FFFFF892H Internal RAM data status register FFFFF8B0H Prescaler mode register 0 FFFFF8B1H Prescaler compare register 0 FFFFF9FCH On-chip debug mode register FFFFF9FEH Peripheral emulation register 1 FFFFFA00H UARTA0 control ...
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V850ES/JJ3 Address Function Register Name FFFFFC60H Port 0 function register FFFFFC66H Port 3 function register FFFFFC66H Port 3 function register L FFFFFC67H Port 3 function register H FFFFFC68H Port 4 function register FFFFFC6AH Port 5 function register FFFFFC6CH Port 6 ...
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V850ES/JJ3 Address Function Register Name FFFFFD36H CSIB3 transmit data register FFFFFD36H CSIB3 transmit data register L FFFFFD40H CSIB4 control register 0 FFFFFD41H CSIB4 control register 1 FFFFFD42H CSIB4 control register 2 FFFFFD43H CSIB4 status register FFFFFD44H CSIB4 receive data register ...
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V850ES/JJ3 3.4.7 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JJ3 has the following eight special registers. • Power save control register (PSC) • Clock control register ...
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V850ES/JJ3 (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared ...
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V850ES/JJ3 (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The ...
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V850ES/JJ3 (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ...
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V850ES/JJ3 3.4.8 Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JJ3. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) ...
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V850ES/JJ3 (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU ...
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V850ES/JJ3 (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request ...
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V850ES/JJ3 4.1 Features I/O ports: 128 • tolerant/N-ch open-drain output switchable: 60 (ports Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JJ3 features a total of 128 I/O ports consisting ...
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V850ES/JJ3 4.3 Port Configuration Item Control register Port n mode register (PMn CD, CM, CS, CT, DH, DL) Port n mode control register (PMCn CM, ...
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V850ES/JJ3 (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can ...
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V850ES/JJ3 (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port ...
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V850ES/JJ3 (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified ...
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V850ES/JJ3 (7) Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate ...
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V850ES/JJ3 4.3.1 Port 0 Port 7-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P00 6 TIP61/TOP61 P01 7 TIP60/TOP60 ...
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V850ES/JJ3 (2) Port 0 mode register (PM0) After reset: FFH PM0 1 PM0n 0 Output mode 1 Input mode R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 R/W Address: FFFFF420H PM06 PM05 PM04 PM03 I/O mode control ( CHAPTER ...
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V850ES/JJ3 (3) Port 0 mode control register (PMC0) After reset: 00H PMC0 0 PMC06 0 I/O port 1 INTP3 input PMC05 0 I/O port 1 INTP2 input PMC04 0 I/O port 1 PMC03 0 I/O port 1 INTP0 input/ADTRG input ...
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V850ES/JJ3 (4) Port 0 function control register (PFC0) After reset: 00H PFC0 0 PFC03 0 INTP0 input 1 ADTRG input PFC01 0 TIP60 input 1 TOP60 output PFC00 0 TIP61 input 1 TOP61 output (5) Port 0 function register (PF0) ...
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V850ES/JJ3 4.3.2 Port 1 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P10 3 ANO0 P11 4 ANO1 ...
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V850ES/JJ3 4.3.3 Port 3 Port 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P30 25 TXDA0/SOB4 P31 26 RXDA0/INTP7/SIB4 ...
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V850ES/JJ3 (1) Port 3 register (P3) After reset: 0000H (output latch (P3H) 0 (P3L) P37 P3n 0 1 Remarks 1. The P3 register can be read or written in 16-bit units. However, when using the higher 8 bits ...
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V850ES/JJ3 (3) Port 3 mode control register (PMC3) After reset: 0000H 15 PMC3 (PMC3H) 0 (PMC3L) 0 PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 PMC30 0 ...
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V850ES/JJ3 (4) Port 3 function control register (PFC3) After reset: 0000H 15 PFC3 (PFC3H) 0 (PFC3L) 0 Remarks 1. For details of alternate function specification, see 4.3.3 (6) specifications. 2. The PFC3 register can be read or written in 16-bit ...
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V850ES/JJ3 (6) Port 3 alternate function specifications PFC39 0 RXDA2 input 1 SCL00 input PFC38 0 TXDA2 output 1 SDA00 I/O PFC35 0 TIP11 input 1 TOP11 output PFC34 0 TIP10 input 1 TOP10 output PFC33 0 TIP01 input 1 ...
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V850ES/JJ3 (7) Port 3 function register (PF3) After reset: 0000H 15 0 PF3 (PF3H) (PF3L) PF37 PF3n 0 1 Caution When an output pin is pulled Remarks 1. The PF3 register can be read or written in ...
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V850ES/JJ3 4.3.4 Port 4 Port 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P40 22 SIB0/SDA01 P41 23 SOB0/SCL01 P42 24 SCKB0 Caution ...
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V850ES/JJ3 (3) Port 4 mode control register (PMC4) After reset: 00H PMC4 0 PMC42 0 I/O port 1 SCKB0 I/O PMC41 0 I/O port 1 SOB0 output/SCL01 I/O PMC40 0 I/O port 1 SIB0 input/SDA01 I/O (4) Port 4 function ...
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V850ES/JJ3 4.3.5 Port 5 Port 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P50 37 TIQ01/KR0/TOQ01/RTP00 P51 38 TIQ02/KR1/TOQ02/RTP01 P52 39 TIQ03/KR2/TOQ03/RTP02/DDI P53 ...
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V850ES/JJ3 (3) Port 5 mode control register (PMC5) After reset: 00H PMC5 0 PMC55 0 I/O port 1 SCKB2 I/O/KR5 input/RTP05 output PMC54 0 I/O port 1 SOB2 output/KR4 input/RTP04 output PMC53 0 I/O port 1 SIB2 input/KR3 input/TIQ00 input/TOQ00 ...
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V850ES/JJ3 (5) Port 5 function control expansion register (PFCE5) After reset: 00H PFCE5 0 Remark For details of alternate function specification, see 4.3.5 (6) specifications. (6) Port 5 alternate function specifications PFCE55 PFC55 ...
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V850ES/JJ3 PFCE50 PFC50 Note The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as the TIQ0m pin, disable KRn pin key return detection, which is the alternate function. ...
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V850ES/JJ3 4.3.6 Port 6 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P60 43 RTP10 P61 44 RTP11 ...
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V850ES/JJ3 (1) Port 6 register (P6) After reset: 0000H (output latch (P6H) P615 (P6L) P67 P6n 0 1 Remarks 1. The P6 register can be read or written in 16-bit units. However, when using the higher 8 bits ...
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V850ES/JJ3 (3) Port 6 mode control register (PMC6) After reset: 0000H 15 PMC6 (PMC6H) 0 PMC67 (PMC6L) PMC613 0 1 PMC612 0 1 PMC611 0 1 PMC610 0 1 PMC69 0 1 PMC68 0 1 PMC67 0 1 PMC66 0 ...
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V850ES/JJ3 (4) Port 6 function control register H (PFC6H) After reset: 00H 15 PFC6H 0 PFC613 0 1 PFC612 0 1 PFC69 0 1 (5) Port 6 function register (PF6) After reset: 0000H 15 PF6 (PF6H) PF615 PF67 (PF6L) PF6n ...
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V850ES/JJ3 4.3.7 Port 7 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P70 144 ANI0 P71 143 ANI1 ...
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V850ES/JJ3 (1) Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) P7H P715 P77 P7L P7n 0 Outputs 0 1 Outputs 1 Caution Do not read or write the P7H and P7L registers during ...
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V850ES/JJ3 4.3.8 Port 8 Port 2-bit port for which I/O settings can be controlled in 1-bit units. Port 8 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P80 59 RXDA3/INTP8 P81 60 TXDA3 ...
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V850ES/JJ3 (3) Port 8 mode control register (PMC8) After reset: 00H PMC8 0 PMC81 0 I/O port 1 TXDA3 output PMC80 0 I/O port 1 RXDA3 input/INTP8 Note The INTP8 and RXDA3 pins are alternate-function pins. When using the RXDA3 ...
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V850ES/JJ3 4.3.9 Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name P90 61 A0/KR6/TXDA1/SDA02 P91 62 A1/KR7/RXDA1/SCL02 ...
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V850ES/JJ3 (1) Port 9 register (P9) After reset: 0000H (output latch (P9H) P915 (P9L) P97 P9n 0 1 Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the higher 8 bits ...
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V850ES/JJ3 (3) Port 9 mode control register (PMC9) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 1 ...
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V850ES/JJ3 PMC97 0 I/O port 1 A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 0 I/O port 1 A6 output/TIP21 input/TOP21 output PMC95 0 I/O port 1 A5 output/TIP30 input/TOP30 output PMC94 0 I/O port 1 A4 output/TIP31 input/TOP31 output PMC93 0 ...
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V850ES/JJ3 (4) Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 or PFCE9 register to 0000H. After ...
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V850ES/JJ3 (6) Port 9 alternate function specifications PFCE915 PFC915 PFCE914 PFC914 PFC913 0 A13 output 1 INTP4 input PFC912 0 A12 output 1 SCKB3 ...
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V850ES/JJ3 PFCE96 PFC96 PFCE95 PFC95 PFCE94 PFC94 PFCE93 PFC93 ...
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V850ES/JJ3 (7) Port 9 function register (PF9) After reset: 0000H 15 PF9 (PF9H) PF915 (PF9L) PF97 PF9n 0 1 Caution When an output pin is pulled Remarks 1. The PF9 register can be read or written in ...
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V850ES/JJ3 4.3.10 Port CD Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CD includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PCD0 77 PCD1 78 PCD2 79 ...
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V850ES/JJ3 4.3.11 Port CM Port 6-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PCM0 85 WAIT PCM1 86 CLKOUT ...
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V850ES/JJ3 (3) Port CM mode control register (PMCCM) After reset: 00H PMCCM 0 PMCCM3 0 1 PMCCM2 0 1 PMCCM1 0 1 PMCCM0 0 1 R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 R/W Address: FFFFF04CH PMCCM3 PMCCM2 PMCCM1 PMCCM0 ...
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V850ES/JJ3 4.3.12 Port CS Port 8-bit port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PCS0 81 CS0 PCS1 82 CS1 ...
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V850ES/JJ3 (3) Port CS mode control register (PMCCS) After reset: 00H PMCCS 0 PMCCS3 0 1 PMCCS2 0 1 PMCCS1 0 1 PMCCS0 0 1 R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 R/W Address: FFFFF048H PMCCS3 PMCCS2 PMCCS1 PMCCS0 ...
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V850ES/JJ3 4.3.13 Port CT Port 8-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PCT0 95 WR0 PCT1 96 WR1 ...
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V850ES/JJ3 (3) Port CT mode control register (PMCCT) After reset: 00H PMCCT 0 PMCCT6 0 1 PMCCT4 0 1 PMCCT1 0 1 PMCCT0 0 1 R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 R/W Address: FFFFF04AH PMCCT6 0 PMCCT4 0 Specification of PCT6 ...
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V850ES/JJ3 4.3.14 Port DH Port 8-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PDH0 121 A16 PDH1 122 A17 ...
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V850ES/JJ3 (3) Port DH mode control register (PMCDH) After reset: 00H PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn 0 1 R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 R/W Address: FFFFF046H Specification of PDHn pin operation mode ( ...
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V850ES/JJ3 4.3.15 Port DL Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name PDL0 105 AD0 PDL1 106 AD1 ...
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V850ES/JJ3 (1) Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 (PDLL) PDL7 PDLn 0 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 bits ...
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V850ES/JJ3 (3) Port DL mode control register (PMCDL) After reset: 0000H 15 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Caution When the SMSEL bit of the EXIMC ...
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V850ES/JJ3 4.4 Block Diagrams PORT RD R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 4-3. Block Diagram of Type A-1 PMmn Pmn Address P-ch A/D input signal N-ch CHAPTRER 4 PORT FUNCTIONS Pmn Page 120 of 892 ...
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V850ES/JJ3 PORT PORT RD R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 4-4. Block Diagram of Type A-2 PMmn Pmn Address P-ch D/A output signal N-ch Figure 4-5. Block Diagram of Type B-1 PMmn Pmn ...
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V850ES/JJ3 WR PF PFmn WR PM PMmn WR PORT Pmn Address RD R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 4-6. Block Diagram of Type C-1 CHAPTRER 4 PORT FUNCTIONS EV DD P-ch Pmn N- Page 122 of 892 ...
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V850ES/JJ3 WR PMC PORT RD alternate function is used R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 4-7. Block Diagram of Type D-1 PMCmn PMmn Pmn Address Input signal when CHAPTRER 4 PORT FUNCTIONS Pmn Page 123 of 892 ...
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V850ES/JJ3 WR PMC PMCmn WR PM Output signal when alternate function is used WR PORT RD R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 4-8. Block Diagram of Type D-2 PMmn Pmn Address CHAPTRER 4 PORT FUNCTIONS Pmn Page 124 of 892 ...
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V850ES/JJ3 WR PMC Output enable signal of address/data bus Output buffer off signal WR PM Output signal when alternate function is used WR PORT Input enable signal of address/data bus Input signal when alternate function is used RD R01UH0016EJ0400 Rev.4.00 ...
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V850ES/JJ3 WR PF PFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 4-10. Block Diagram ...
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V850ES/JJ3 WR PF PFmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure 4-11. Block Diagram of Type E-2 CHAPTRER 4 PORT FUNCTIONS EV DD ...
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V850ES/JJ3 WR PF PFmn Output enable signal when alternate function is used WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics ...
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V850ES/JJ3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port ...
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V850ES/JJ3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port ...
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V850ES/JJ3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD R01UH0016EJ0400 Rev.4.00 Sep 30, 2010 Figure ...
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V850ES/JJ3 WR PF PFmn Output enable signal when alternate function is used WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn ...
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V850ES/JJ3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address Input signal 1 RD when alternate function is used Input signal 2 when alternate function is ...
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V850ES/JJ3 WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when RD alternate function is ...
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V850ES/JJ3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used Notes 1. See 19.6 External Interrupt Request ...
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V850ES/JJ3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is ...
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V850ES/JJ3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used Input signal 2 when ...
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V850ES/JJ3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal when alternate function is used WR PORT Pmn Address RD Input signal when alternate function ...
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V850ES/JJ3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when ...
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V850ES/JJ3 WR PF PFmn Output enable signal when alternate WR PFCE function is used PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used ...
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V850ES/JJ3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal 1-1 when ...
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V850ES/JJ3 WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input ...
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V850ES/JJ3 WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging ...
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V850ES/JJ3 WR PF PFmn WR OCDM0 OCDM0 WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input ...
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V850ES/JJ3 WR PF PFmn WR OCDM0 OCDM0 Output enable signal when alternate function is used WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate ...
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V850ES/JJ3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used ...
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V850ES/JJ3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal 1 ...
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V850ES/JJ3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when alternate ...
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V850ES/JJ3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address Input signal when alternate ...
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V850ES/JJ3 WR PF PFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used WR PORT Pmn Address RD Input signal 1 ...
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V850ES/JJ3 WR PF PFmn WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function ...
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V850ES/JJ3 WR PF PFmn External reset signal WR OCDM0 OCDM0 WR INTR Note 1 INTRmn WR INTF Note 1 INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal when on-chip debugging Input signal when alternate ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P00 TIP61 Input P00 = Setting not required TOP61 Output P00 = Setting not required P01 TIP60 Input P01 = Setting not required TOP60 Output P01 = Setting not ...
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Table 4-19. Using Port Pins as Alternate-Function Pins (2/8) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P33 TIP01 Input P33 = Setting not required PM33 = Setting not required TOP01 Output P33 = Setting not required ...
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Table 4-19. Using Port Pins as Alternate-Function Pins (3/8) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P53 SIB2 Input P53 = Setting not required PM53 = Setting not required TIQ00 Input P53 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P612 TIP80 Input P612 = Setting not required PM612 = Setting not required TOP80 Output P612 = Setting not required PM612 = Setting not required P613 TIP81 Input P613 ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P90 A0 Output P90 = Setting not required KR6 Input P90 = Setting not required TXDA1 Output P90 = Setting not required SDA02 I/O P90 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P97 A7 Output P97 = Setting not required SIB1 Input P97 = Setting not required TIP20 Input P97 = Setting not required TOP20 Output P97 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PCM0 WAIT Input PCM0 = Setting not required PCM1 CLKOUT Output PCM1 = Setting not required PCM2 HLDAK Output PCM2 = Setting not required PCM3 HLDRQ Input PCM3 = ...
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Table 4-19. Using Port Pins as Alternate-Function Pins (8/8) Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PDL8 AD8 I/O PDL8 = Setting not required PMDL8 = Setting not required PDL9 AD9 I/O PDL9 = Setting not ...
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V850ES/JJ3 4.6 Cautions 4.6.1 Cautions on setting port pins (1) In the V850ES/JJ3, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin ...
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V850ES/JJ3 The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order <1> <2> <3> <4> <2> communication may be affected since the ...
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V850ES/JJ3 Figure 4-37. Example of Switching from P02 to NMI (Incorrect) PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Remark [Example 2] Switch from external pin (NMI) to ...
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V850ES/JJ3 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that ...
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V850ES/JJ3 4.6.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST ...
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V850ES/JJ3 The V850ES/JJ3 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplexed bus with a minimum of 3 bus ...
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V850ES/JJ3 5.2 Bus Control Pins The pins used to connect an external device are listed in the table below. Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 A16 to A23 PDH0 to PDH7 WAIT PCM0 CLKOUT PCM1 ...
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V850ES/JJ3 5.3 Memory Block Function The 16 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these ...
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V850ES/JJ3 5.4 External Bus Interface Mode Control Function The V850ES/JJ3 includes the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus ...
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V850ES/JJ3 5.5 Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access ...
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V850ES/JJ3 5.5.3 Access by bus size The V850ES/JJ3 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to ...
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V850ES/JJ3 (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n Byte data External data bus (b) 8-bit data bus width <1> Access to even address (2n) 7 ...
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V850ES/JJ3 (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n Halfword data External data bus (b) 8-bit data bus width <1> Access to even ...
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V850ES/JJ3 (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External data ...
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V850ES/JJ3 (a) 16-bit data bus width (2/2) <3> Access to address ( First access Address Word data External data bus ...
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V850ES/JJ3 (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Address Word data External data Word data bus <2> Access ...
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V850ES/JJ3 (b) 8-bit data bus width (2/2) <3> Access to address ( First access Address Word data External data Word ...
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V850ES/JJ3 5.6 Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/ seven data wait states can be inserted in the bus cycle that is executed ...
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V850ES/JJ3 5.6.2 External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is ...
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V850ES/JJ3 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the ...
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V850ES/JJ3 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS0 to CS3 ...
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V850ES/JJ3 5.7 Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in ...
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V850ES/JJ3 5.8 Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has ...
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V850ES/JJ3 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK ...