SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet
SAF-TC1130-L150EB-G BB
Specifications of SAF-TC1130-L150EB-G BB
SAF-TC1130-L150EB-GBB
SAF-TC1130-L150EB-GBBINTR
SAF-TC1130-L150EB-GBBTR
SAF-TC1130-L150EB-GBBTR
SAFTC1130L150EBBBXT
SP000106119
SP000106538
SP000743584
Related parts for SAF-TC1130-L150EB-G BB
SAF-TC1130-L150EB-G BB Summary of contents
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TC1130 ...
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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TC1130 ...
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TC1130 Data Sheet Revision History: Previous Version: Page Subjects (major changes since last revision) 77, 78, 79 Added “Operating Conditons apply” statement ,81, 82 Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Single-Chip Microcontroller TriCore™ Family 1 Summary of Features • High Performance 32-bit TriCore™ V1.3 CPU with 4-Stage Pipeline • Floating Point Unit (FPU) • Dual Issue super-scalar implementation – MAC Instruction maximum triple issue • Circular Buffer and bit-reverse ...
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One MultiCAN module with four CAN nodes and 128 message buffers for high efficiency data handling • Fast Ethernet Controller with 10/100 Mbit/sec MII-Based physical devices support • USB module with compliance to USB Specification Revision 1.1, with support ...
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General Device Information 2.1 Block Diagram Figure 2-1 TC1130 Block Diagram Data Sheet General Device Information 3 TC1130 V1.1, 2008-12 ...
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Logic Symbol PORST HDRST General Control CFG[0: AIT M R/W BFCLKI BFCLKO ALE BAA ADV CS[0:3] CSCOM B EBU Control CKE RAS CAS SDCLKI SDCLKO BC[0:3] A[0:23] AD[0:31 ...
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Pin Configuration Reser 16 P3.10 P3.11 P3.12 P2.15 ved 15 P3.0 P3.1 P3.8 P3.2 P3.3 14 P1.9 P1.10 P1.11 P1.14 P1. P1.8 P1.7 P1.5 DDP 12 P1.6 P1.3 P1.1 P1.2 P1.0 11 BAA ...
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Pin Definitions and Functions Table 2-1 Pin Definitions and Functions Symbol Pin In Out P0 I/O P0.0 N11 I/O I/O P0.1 P15 I/O O P0.2 P10 I/O I/O P0.3 M15 I/O O P0.4 R11 I P0.5 R12 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P0. P0. P0. P0. Data Sheet PU/ Functions 1) PD PUC RXDCAN2 CAN ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P1 I/O P1.0 D11 P1.1 C12 P1.2 D12 P1.3 B12 P1.4 C11 O ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P1.7 B13 P1.8 A13 P1.9 A14 P1.10 B14 P1.11 C14 P1.12 F13 I ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P2 I/O P2.0 P12 I/O O P2.1 P11 O I P2.2 P13 I/O P2.3 P14 I/O P2.4 N15 I/O P2.5 N14 O I/O P2.6 N12 I/O I/O P2.7 K16 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P2.13 K14 I P2.14 F16 I I/O O P2.15 E16 I I/O O Data Sheet PU/ Functions 1) PD ⎯ SCL0 IIC clock line 0 CCPOS0_0 CCU60 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P3 I/O P3.0 A15 O O P3.1 B15 O I/O P3.2 D15 O O P3.3 E15 O I/O P3.4 G14 O O P3.5 G15 O I/O P3.6 F15 O ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P3.11 C16 P3.12 D16 P3.13 K13 O O I/O P3.14 J14 O I I/O P3.15 J15 O I I/O Data Sheet ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out P4 I ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out TRST T11 I TCK T12 I TDI T13 I TDO T10 O TMS T9 I TRCLK T8 O HWCFG0 M14 I HWCFG1 L14 I HWCFG2 T6 I BRKIN T5 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out D- T15 I/O CS0 D9 O CS1 D8 O CS2 C9 O CS3 B8 O CSCOMB N3 O SDCLKI J1 I SDCLKO H1 O RAS D6 O CAS D5 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out AD0 C8 I/O AD1 C7 I/O AD2 B6 I/O AD3 C6 I/O AD4 C5 I/O AD5 A3 I/O AD6 A2 I/O AD7 C3 I/O AD8 C2 I/O AD9 D2 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out ...
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Table 2-1 Pin Definitions and Functions (cont’d) Symbol Pin In Out ⎯ V L15 SSOSC ⎯ G10 G13 K7,K8 K9 K10 ⎯ DDP D13 H4 J13 M4 N13 ⎯ E13 ...
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Functional Description 3.1 On-Chip Memories The TC1130 provides the following on-chip memories: • Program Memory Interface (PMI) with – 32-Kbyte Scratch-pad Code RAM (SPRAM) – 16-Kbyte Instruction Cache Memory (ICACHE) • Data Memory Interface (DMI) with – 28-Kbyte Scratch-pad ...
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Address Map Table 3-1 defines the specific segment oriented address blocks of the TC1130 with its address range, size, and PMI/DMI access view. of the Segment 15 which includes on-chip peripheral units and ports. Table 3-1 TC1130 Block Address ...
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Table 3-1 TC1130 Block Address Map (cont’d) Seg- Address Size ment Range D000 0000 – D000 6FFF H D000 7000 – Reserved H D3FF FFFF H D400 0000 – D400 7FFF ...
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Table 3-1 TC1130 Block Address Map (cont’d) Seg- Address Size ment Range 14 E860 0000 – 122 MB Reserved H EFFF FFFF H 15 F000 0000 – 256 MB See H FFFF FFFF H Table 3-2 Block Address Map of ...
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Table 3-2 Block Address Map of Segment 15 (cont’d) Symbol Description – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved CCU60 Capture/Compare Unit 0 CCU61 Capture/Compare Unit 1 – Reserved DMA Direct Memory ...
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Table 3-2 Block Address Map of Segment 15 (cont’d) Symbol Description MCHK Memory Checker – Reserved MLI0_ MLI0 Small Transfer Window 0 SP0 MLI0_ MLI0 Small Transfer Window 1 SP1 MLI0_ MLI0 Small Transfer Window 2 SP2 MLI0_ MLI0 Small ...
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Table 3-2 Block Address Map of Segment 15 (cont’d) Symbol Description MLI1_ MLI1 Large Transfer Window 3 LP3 – Reserved ECU Ethernet Controller Unit – Reserved CPU (Part of System Peripheral Bus) CPU CPU Slave Interface SFRs Reserved MMU Reserved ...
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Memory Protection System The TC1130 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It ...
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Mode Register) which determines the memory access modes which apply to the specified range. 3.3.2 Protection for PTE based translation Memory protection for addresses that undergo PTE based translation is enforced using the PTE used for the address translation. The ...
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On-Chip Bus System The TC1130 includes two bus systems: • Local Memory Bus (LMB) • Flexible Peripheral Interface Bus (FPI) The LMB-to-FPI (LFI) bridge interconnects the FPI bus and LMB Bus. 3.4.1 Local Memory Bus (LMB) The Local Memory ...
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Features: The FPI Bus is designed with the requirements of high-performance systems in mind. The features are: • Core independent • Multimaster capability ( masters) • Demultiplexed operation • Clock synchronous • Peak transfer rate ...
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LMB External Bus Unit The LMB External Bus Control Unit (EBU) of the TC1130 is the interface between external resources, like memories and peripheral units, and the internal resources connected to on-chip buses if enabled. The basic structure and ...
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The EBU is used primarily for any Local Memory Bus (LMB) master accessing external memories. The EBU controls all transactions required for this operation and in particular handles the arbitration between the internal EBU master and the external EBU master. ...
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Direct Memory Access (DMA) The Direct Memory Access Controller executes DMA transactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DMA channel. Each DMA channel ...
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The basic structure and external interconnections of the DMA are shown Clock Control Address Decoder 4 MultiCAN 2 ASC0 2 ASC1 2 ASC2 2 8 SSC0 2 SSC1 DMA 1 Request CCU60 Wiring Matrix 1 CCU61 ...
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Interrupt System An interrupt request can be serviced by the CPU, which is called “Service Provider”. Interrupt requests are referred to as “Service Requests” in this document. Each peripheral in the TC1130 can generate service requests. Additionally, the Bus ...
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Service Service Req. Requestors 4 ASC0 4 ASC1 4 ASC2 3 SSC0 3 SSC1 4 MLI0 2 MLI1 16 M ultiCAN 16 SRNs 8 USB 8 GPTU 9 ETHERNET 2 STM 1 FPU 1 O CDS BUS ...
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Parallel Ports The TC1130 has 72 digital input/output port lines, which are organized into four parallel 16-bit ports and one parallel 8-bit port, Port P0 to Port P4 with 3.3 V nominal voltage. The digital parallel ports can be ...
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Asynchronous/Synchronous Serial Interface (ASC) Figure 3-5 shows a global view of the functional blocks of three Asynchronous/ Synchronous Serial interfaces (ASC0, ASC1 and ASC2). Each ASC module (ASC0/ASC1/ASC2) communicates with the external world via one pair of I/O lines. ...
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Clock ASC0 Control Address Decoder EIR TBIR Interrupt TIR Control RIR to DMA f Clock ASC1 Control Address Decoder EIR TBIR Interrupt TIR Control RIR to DMA f Clock ASC1 Control Address Decoder EIR TBIR Interrupt TIR Control RIR ...
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Features: • Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity bit generation/checking – One or two stop bits – Baud rate from 4.6875 MBaud to 1.1 Baud (@ 75 MHz clock) • Multiprocessor mode ...
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High-Speed Synchronous Serial Interface (SSC) Figure 3-6 shows a global view of the functional blocks of two High-Speed Synchronous Serial interfaces (SSC0 and SSC1). Each SSC supports full-duplex and half-duplex serial synchronous communication up to 37.5 MBaud (@ 75 ...
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SSC0 Clock f Control CLC0 Address Decoder SSC0 Module (Kernel) EIR TIR Interrupt Control RIR to DMA f SSC1 Clock f Control CLC1 Address Decoder SSC1 Module (Kernel) EIR TIR Interrupt Control RIR to DMA 1) M/S Select 1) ...
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Inter IC Serial Interface (IIC) Figure 3-7 shows a global view of the functional blocks of the Inter IC Serial interface (IIC). The IIC module has four I/O lines, located at Port 2. The IIC module is further supplied ...
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Evaluation of the device address in slave mode • Bus access arbitration in multimaster mode Features: • Extended buffer allows send/receive data bytes to be stored • Selectable baud rate generation • Support of standard 100 ...
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Universal Serial Bus Interface (USB) Figure 3-8 shows a global view of the functional blocks of the Universal Serial Bus interface (USB). The USB module is further supplied with clock control, interrupt control, address decoding, and port control logic. ...
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Features: • USB1.1 Device Standard Interface • On-chip transceiver • Differential I/O allow cable length without additional hardware at target’s end. • Hot attach • USB1.1 full speed device • USB protocol handling in hardware • Clock ...
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MultiCAN Figure 3-9 shows a global view of the functional blocks of the MultiCAN module. f CAN Clock f Control CLC Address Decoder Message Object Buffer 128 Objects DMA INT_O [3:0] Interrupt Control INT_O [15:4] INT_O15 CAN Control Figure ...
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The bit timings for the CAN nodes are derived from the peripheral clock ( programmable data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. Features: • ...
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Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based. • Advanced Interrupt Handling: – interrupt output lines are available. Most interrupt requests can be individually routed to one of the 16 interrupt ...
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Micro Link Serial Bus Interface (MLI) Figure 3-10 shows a global view of the functional blocks of two Micro Link Serial Bus interfaces (MLI0 and MLI1). Clock f MLI0 Control Address Decoder INT_O Interrupt Control [3:0] INT_O DMA [7:4] ...
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The Micro Link Serial Bus Interface is dedicated to the serial communication between the other Infineon 32-bit controllers with MLI. The communication is intended to be fast due to an address translation system, and it is not necessary to have ...
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General Purpose Timer Unit (GPTU) Figure 3-11 shows a global view of the functional blocks of the General Purpose Timer Unit (GPTU). f Clock GPTU0 Control Address Decoder SR0 SR1 SR2 SR3 Interrupt SR4 Control SR5 SR6 SR7 Figure ...
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Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events • Two input pins can define a count option Features of T2: • Count up or down is selectable • Operating modes: – ...
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Capture/Compare Unit 6 (CCU6) Figure 3-12 shows a global view of the functional blocks of two Capture/Compare Units (CCU60 and CCU61). Both of the CCU6 modules are further supplied with clock control, interrupt control, address decoding, and port control ...
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Clock CCU Control Address Decoder To DMA SRC0 SRC1 SRC2 SRC3 Interrupt Control SRC0 SRC1 SRC2 SRC3 To DMA Figure 3-12 General Block Diagram of the CCU6 Interfaces Data Sheet /CTRAP CCPOS0 CCPOS1 CCPOS2 CC60 COUT60 CC61 CCU60 Port ...
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Ethernet Controller The MAC controller implements the IEEE 802.3 and operates either at 100 Mbit/sec or 10 Mbit/sec. Figure 3-13 module specific interface connections. Ethernet Controller DMUR FPI (M/S) DMUT Figure 3-13 General Block Diagram of the Ethernet Controller ...
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RB and TB provide on-chip data buffering whereas DMUR and DMUT perform data transfer from/to the shared memory. Two interfaces are provided by the Ethernet Controller module: • MII interface for connection of Ethernet PHYs via 18 Input/Output lines • ...
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System Timer The STM within the TC1130 is designed for global system timing applications requiring both high precision and long range. The STM provides the following features: • Free-running 56-bit counter • All 56 bits can be read synchronously ...
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STMIR1 Interrupt Control STMIR0 Enable / Disable Clock f Control STM Address Decoder PORST Figure 3-14 Block Diagram of the STM Module Data Sheet Compare Register CMP0 56-Bit System Timer ...
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Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1130 in a user-specified time period. When ...
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Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a ...
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System Control Unit The System Control Unit (SCU) of the TC1130 handles the system control tasks. All of these system functions are tightly coupled; thus, they are conveniently handled by one unit, the SCU. The system tasks of the ...
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Boot Options The TC1130 booting schemes provides a number of different boot options for the start of code execution. Table 3-3 Table 3-3 Boot Selections 1) 1) BRKIN TM HWCFG [2: 000 001 010 011 100 101 ...
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Power Management System The TC1130 power management system allows software to configure the various processing units to adjust automatically in order to draw the minimum necessary power for the application. There are four power management modes: • Run Mode ...
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On-Chip Debug Support The On-Chip Debug Support of the TC1130 consists of the following building blocks: • OCDS L1 module of TriCore™ • OCDS L2 interface of TriCore™ • OCDS L1 module in the BCU of the FPI Bus ...
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OCDS2[15:0] TDO TDI TMS TCK TRST BRKIN BRKOUT Figure 3-15 OCDS Support Basic Block Diagram Data Sheet OCDS OCDS OCDS TM TriCore L2 L1 Watch- dog timer OSCU JTAG Controller JDI Debug I/F MCBS Break Switch 66 TC1130 ...
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... Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it looses the lock on the external clock ...
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The oscillator circuit, which is designed to work with an external crystal oscillator or an external stable clock source, consists of an inverting amplifier with XTAL1 as input and XTAL2 as output. Figure 3-17 shows the recommended external oscillator circuitries ...
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Table 3-5 Load Capacitors Select Fundamental Mode Crystal Frequency (approx., MHz block capacitor between recommended, too. Data Sheet (cont’d) Load Capacitors C1, C2 (pF and V , DDOSC3 SSOSC 69 TC1130 Functional Description V ...
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Power Supply The TC1130 provides an ingenious power supply concept in order to improve the EMI behavior as well as to minimize the crosstalk within on-chip modules. Figure 3-18 shows the TC1130’s power supply concept, where certain logic modules ...
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Power Sequencing During power-up, reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the power-up time (rising of the supply voltages from 0 to their regular operating ...
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Identification Register Values Table 3-6 TC1130 Identification Registers Short Name SCU_ID MANID CHIPID RTID SBCU_ID STM_ID CBS_JDPID GPTU_ID CCU60_ID CCU61_ID DMA_ID CAN_ID USB_ID SSC0_ID SSC1_ID ASC0_ID ASC1_ID ASC2_ID IIC_ID MLI0_ID MLI1_ID MCHK_ID CPS_ID MMU_ID CPU_ID EBU_ID DMU_ID DMI_ID PMI_ID ...
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Table 3-6 TC1130 Identification Registers (cont’d) Short Name LBCU_ID LFI_ID Data Sheet Address F87F FE08 H F87F FF08 H 73 TC1130 Functional Description Value 000F C005 H 000C C005 H V1.1, 2008-12 ...
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Electrical Parameters 4.1 General Parameters 4.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the TC1130 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for design ...
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Absolute Maximum Rating Parameter Ambient temperature Storage temperature Junction temperature Voltage at 1.5 V power supply 1) V pins with respect to SS Voltage at 3.3 V power supply 2) V pins with respect to SS Voltage on any ...
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Operating Condition The following operating conditions must be complied with in order to ensure correct operation of the TC1130. All parameters specified in the following table refer to these operating conditions, unless otherwise indicated. Parameter Digital supply voltage Digital ...
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DC Parameters 4.2.1 Input/Output Characteristics Table 4-1 Input/Output DC-Characteristics (Operating Conditions apply) Parameter GPIO pins, Dedicated pins and EBU pins Input low voltage Input high voltage Output low voltage Output high voltage 1) Pull-up current 2) Pull-down current 3) ...
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Oscillator Characteristics Table 4-2 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Oscillator Pins Input low voltage at XTAL1 Input high voltage at XTAL1 Quartz oscillation peak-peak amplitude at oscillator Input Input low voltage at XTAL1 Input high voltage at ...
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USB Characteristics 4.2.3.1 DC Electrical Characteristics Table 4-3 USB Electrical Characteristics (Operating Conditions apply) Parameter Symbol Input Level V Differential Input DI Level V Differential Common DCM Mode Range Single Ended V SE Receiver Threshold Output Levels V Static ...
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Parameter Symbol Driver Output R DO Impedance R Termination T Impedance USB Interface Figure 4-1 USB Interface Data Sheet Limit Values min. typ. max. 28 – 44 1.425 1.5 1.575 V V DDP DDP 1.5kΩ V DDP 80 TC1130 Electrical ...
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IIC Characteristics Each IIC Pin is an open drain output pin with different characteristics than other pins. The related characteristics are given in the following table. Table 4-5 IIC Pin Characteristics (Operating Conditions Apply) Parameter Output low voltage 1) ...
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Power Supply Current Table 4-6 Power Supply Currents (Operating Conditions apply) Parameter Active mode supply current Idle mode supply current Deep sleep mode supply current 1) Typical values are measured at 25°C, CPU clock at 150 MHz, and nominal ...
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AC Parameters 4.3.1 Power, Pad and Reset Timing Parameter Min. V voltage to ensure defined pad DDP 1) states 2) Oscillator start-up time Minimum PORST active time after power supplies are stable at operating levels HDRST pulse width Ports ...
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V DDPPA VDDP VDD t oscs OSC t POA t POA PORST HDRST 2) Pads Pad- state undefined Figure 4-2 Power and Reset Timing Data Sheet programmed 2) Tri-state, pull device ...
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PLL Parameters When PLL operation is configured (PLL_CLC.LOCK = 1), the on-chip phase locked loop is enabled and provides the master clock. The PLL multiplies the input frequency by the × F) which results from the input divider, the ...
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Acc. jitter D N K=15 ns ±8 ±7 ±6 ±5 ±4 ±3 ±2 ± Figure 4-3 Approximated Accumulated PLL Jitter Note: The bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum ...
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AC Characteristics (Operating Conditions apply) 2.4V 0.4V AC inputs during testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”. Timing measurements are made at V Figure 4-4 Input/Output Waveforms for AC Tests - ...
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Input Clock Timing (Operating Conditions apply) Parameter Oscillator clock frequency Input clock frequency driving at XTAL1 t Input Clock Duty Cycle ( 0 Input Clock at XTAL1 Figure 4-5 Input Clock Timing Data Sheet with PLL with ...
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Port Timing (Operating Conditions apply; C Parameter Port data valid from TRCLK 1) Port data is output with respect to the FPI clock. The TRCLK is used as a reference here since the FPI clock is not available as ...
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Timing for JTAG Signals (Operating Conditions apply; C Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time 0 TCK Figure 4-7 TCK Clock Timing Data Sheet =50pF) L ...
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Parameter TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK TDO high impedance to valid output from TCK TDO valid output to high impedance from TCK TCK TMS ...
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Timing for OCDS Trace and Breakpoint Signals (Operating Conditions apply; C Parameter BRK_OUT valid from TRCLK OCDS2_STATUS[4:0] valid from TRCLK OCDS2_INDIR_PC[7:0] valid from TRCLK OCDS2_BRKPT[2:0] valid from TRCLK TRCLK CPU Trace Signals Note: CPU Trace OCDS2_INDIR_PC[7:0] and OCDS_BRKPT[2:0]. Figure ...
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EBU Timings 4.3.8.1 SDCLKO Output Clock Timing (Operating Conditions apply pF) Parameter SDCLKO period SDCLKO high time SDCLKO low time SDCLKO rise time SDCLKO fall time 1) The parameters are applicable for PC100 SDRAM access and ...
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V DD BFCLKO / SDCLKO Figure 4-10 EBU Clock Output Timing 4.3.8.3 Timing for SDRAM Access Signals (Operating Conditions apply; C Parameter SDCLKO period CKE output valid time from SDCLKO CKE output hold time from SDCLKO Address output valid ...
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Write Access SDCLKO t 1 CKE t 3 Address ROW t CSx t 5 RAS CAS RD/WR BC[3:0] AD[31:0] Read Access SDCLKO t 1 CKE t 3 Address ROW t CSx t 5 RAS CAS RD/WR BC[3:0] AD[31:0] Figure 4-11 ...
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Timing for Burst Flash Access Signals (Operating Conditions apply; C Parameter Address output valid time from BFCLKO Address output hold time from BFCLKO CSx output valid time from BFCLKO RD output valid time from BFCLKO ADV output valid time ...
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Command Address Delay Phase(s) Phase(s) BFCLKO t 1 Address Address t CSx ADV BAA D[31:0] WAIT Figure 4-12 Burst Flash Access Timing Note: Output delays are always referenced to BFCLKO. The reference ...
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Timing for Demultiplexed Access Signals (Operating Conditions apply; C Parameter CSx, RD/WR, RD, MR/W, BC(3:0) output valid time from output clock CSx, RD/WR, RD, MR/W, BC(3:0) output hold time from output clock Address output valid time from output clock ...
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Write Access Address Phase(s) SDCLKO Address Address t 1 CSx RD/ MR/W CMDELAY WAIT t 1 BC[3:0] AD[31:0] Read Access Address Phase(s) SDCLKO/ SDCLKI Address Address t 1 CSx RD ...
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Timing for Multiplexed Access Signals (Operating Conditions apply; C Parameter ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output valid time from output clock ALE, CSx, RD/WR, RD, MR/W, BC(3:0) output hold time from output clock AD(31:0) output valid time from ...
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Write Access Address Phase(s) SDCLKO AD[31:0] Address t 1 CSx RD/ MR/W CMDELAY WAIT t 1 BC[3:0] Read Access Address Phase(s) SDCLKO/ SDCLKI AD[31:0] Address t 1 CSx RD t ...
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Peripheral Timings 4.3.9.1 Timing for Ethernet Signals (Operating Conditions apply; C Parameter ETXCLK period (10 Mbit/sec Ethernet) ETXCLK high time (10 Mbit/sec Ethernet) ETXCLK low time (10 Mbit/sec Ethernet) ETXCLK period (100 Mbit/sec Ethernet) ETXCLK high time (100 Mbit/sec ...
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Parameter EMDIO input hold from EMDC (sourced by STA) EMDIO output valid from EMDC (sourced by PHY) Note: Any other parameters which are not stated here, please refer to ANSI/IEEE Std 802.3, Section 22.3. ETXCLK ERXCLK ERXD(3:0) ERXDV ERXER ETXD(3:0) ...
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SSC Master Mode Timing (Operating Conditions apply; C Parameter SCLK clock period MTSR/SLSOx delay from SCLK MRST setup to SCLK MRST hold from SCLK 1/f . When f SSCmin SYS SYS 1)2) SCLK 1) ...
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MLI Interface Timing (Operating Conditions apply; C Parameter TCLK/RCLK clock period MLI outputs delay from TCLK MLI inputs setup to RCLK MLI inputs hold to RCLK RREADY output delay from TCLK 1/f . When ...
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Timing for USB Transceiver Signals (Operating Conditions apply; C Parameter Full speed mode rise time Full speed mode fall time Figure 4-18 AC Testing: Input, Output Waveforms Data Sheet = 50 pF) L 90% ...
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Package Outline Plastic Package, P-LBGA-208-2 (SMD) (Low Profile Ball Grid Array Package) Figure 4-19 P-LBGA-208-2 Package You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted ...
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... Published by Infineon Technologies AG ...