C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 181

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F023R
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Bits7-0:
Note:
Bits7-0:
Note:
P6.7
P7.7
R/W
R/W
Bit7
Bit7
P6.[7:0]: Port6 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P6.n pin is logic low.
1: P6.n pin is logic high.
P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See
ORY INTERFACE AND ON-CHIP XRAM” on page 145
Memory Interface.
P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or
as D[7:0] in Non-multiplexed mode). See
FACE AND ON-CHIP XRAM” on page 145
Interface.
P6.6
P7.6
R/W
R/W
Bit6
Bit6
P6.5
P7.5
R/W
R/W
Bit5
Bit5
Figure 17.23. P6: Port6 Data Register
Figure 17.24. P7: Port7 Data Register
P6.4
P7.4
R/W
R/W
Bit4
Bit4
P6.3
P7.3
Section “16. EXTERNAL DATA MEMORY INTER-
R/W
R/W
Bit3
Bit3
Rev. 1.4
for more information about the External Memory
P6.2
P7.2
R/W
R/W
Bit2
Bit2
Section “16. EXTERNAL DATA MEM-
for more information about the External
P6.1
P7.1
C8051F020/1/2/3
R/W
R/W
Bit1
Bit1
P6.0
P7.0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
Reset Value
11111111
Reset Value
11111111
0x86
0x96
181

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