C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 193

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2
18.4.3. Data Register
The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.
Software can read or write to this register while the SI flag is set to logic 1; software should not attempt to access the
SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0 since the hardware may be in the
process of shifting a byte of data in or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in.
Therefore, SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transi-
tion from master transmitter to slave receiver is made with the correct data in SMB0DAT.
Figure 18.10. SMB0DAT: SMBus0 Data Register
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bits7-0:
SMB0DAT: SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial interface or a
byte that has just been received on the SMBus0 serial interface. The CPU can read from or write to
this register whenever the SI serial interrupt flag (SMB0CN.3) is set to logic 1. When the SI flag is
not set, the system may be in the process of shifting data in/out and the CPU should not attempt to
access this register.
18.4.4. Address Register
The SMB0ADR Address register holds the slave address for the SMBus0 interface. In slave mode, the seven most-
significant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the recognition of the
general call address (0x00). If Bit0 is set to logic 1, the general call address will be recognized. Otherwise, the general
call address is ignored. The contents of this register are ignored when SMBus0 is operating in master mode.
Figure 18.11. SMB0ADR: SMBus0 Address Register
R/W
R/W
R/W
SLV6
SLV5
SLV4
Bit7
Bit6
Bit5
Bits7-1:
SLV6-SLV0: SMBus0 Slave Address.
These bits are loaded with the 7-bit slave address to which SMBus0 will respond when operating as a
slave transmitter or slave receiver. SLV6 is the most significant bit of the address and corresponds to
the first bit of the address byte received.
Bit0:
GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.
C8051F020/1/2/3
R/W
R/W
R/W
R/W
Bit4
Bit3
Bit2
R/W
R/W
R/W
R/W
SLV3
SLV2
SLV1
SLV0
Bit4
Bit3
Bit2
Rev. 1.4
R/W
Reset Value
00000000
Bit1
Bit0
SFR Address:
0xC2
R/W
Reset Value
GC
00000000
Bit1
Bit0
SFR Address:
0xC3
193

Related parts for C8051F023R