IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part NumberC8051F023R
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F023R datasheets
 


Specifications of C8051F023R

Core Processor8051Core Size8-Bit
Speed25MHzConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDTNumber Of I /o32
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size4.25K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Data ConvertersA/D 8x8b, 8x10b; D/A 2x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case64-TQFP, 64-VQFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Other names336-1035-2  
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20.
UART0
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate
in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully sup-
ported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data
byte before software has finished reading the previous data byte. A Receive Overrun bit indicates when new received
data is latched into the receive buffer before the previous received byte is read.
UART0 is accessed via its associated SFRs, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The single
SBUF0 location provides access to both transmit and receive registers. Reads access the Receive register and writes
access the Transmit register automatically.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit Interrupt flag,
TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI0 (SCON0.0) set
when reception of a data byte is complete. UART0 interrupt flags are not cleared by hardware when the CPU vectors
to the interrupt service routine; they must be cleared manually by software. This allows software to determine the
cause of the UART0 interrupt (transmit complete or receive complete).
Figure 20.1. UART0 Block Diagram
Write to
SBUF
Stop Bit
Gen.
Start
Tx Clock
UART
Baud Rate
Generation
Logic
Rx Clock
Start
Frame Error
Detection
SFR Bus
TB8
SET
SBUF
D
Q
(Transmit Shift)
CLR
Zero Detector
Shift
Data
Tx Control
Send
Tx IRQ
SCON
TI
S
S
S
R
T
R
T
R
M
M
M
E
B
B
I
I
0
1
2
N
8
8
RI
EN
Rx IRQ
Load
SBUF
Rx Control
Address
Match
Shift
0x1FF
Input Shift Register
(9 bits)
Load SBUF
RB8
SADDR
SBUF
Match Detect
(Receive Latch)
SADEN
Read
SBUF
SFR Bus
Rev. 1.4
C8051F020/1/2/3
TX
Crossbar
Serial Port
(UART0/1)
Interrupt
Port I/O
RX
Crossbar
205