C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 205

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2
20.
UART0
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate
in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully sup-
ported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data
byte before software has finished reading the previous data byte. A Receive Overrun bit indicates when new received
data is latched into the receive buffer before the previous received byte is read.
UART0 is accessed via its associated SFRs, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The single
SBUF0 location provides access to both transmit and receive registers. Reads access the Receive register and writes
access the Transmit register automatically.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit Interrupt flag,
TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI0 (SCON0.0) set
when reception of a data byte is complete. UART0 interrupt flags are not cleared by hardware when the CPU vectors
to the interrupt service routine; they must be cleared manually by software. This allows software to determine the
cause of the UART0 interrupt (transmit complete or receive complete).
Figure 20.1. UART0 Block Diagram
Write to
SBUF
Stop Bit
Gen.
Start
Tx Clock
UART
Baud Rate
Generation
Logic
Rx Clock
Start
Frame Error
Detection
SFR Bus
TB8
SET
SBUF
D
Q
(Transmit Shift)
CLR
Zero Detector
Shift
Data
Tx Control
Send
Tx IRQ
SCON
TI
S
S
S
R
T
R
T
R
M
M
M
E
B
B
I
I
0
1
2
N
8
8
RI
EN
Rx IRQ
Load
SBUF
Rx Control
Address
Match
Shift
0x1FF
Input Shift Register
(9 bits)
Load SBUF
RB8
SADDR
SBUF
Match Detect
(Receive Latch)
SADEN
Read
SBUF
SFR Bus
Rev. 1.4
C8051F020/1/2/3
TX
Crossbar
Serial Port
(UART0/1)
Interrupt
Port I/O
RX
Crossbar
205

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