C8051F023R Silicon Laboratories Inc, C8051F023R Datasheet - Page 224

IC 8051 MCU 64K FLASH 64TQFP

C8051F023R

Manufacturer Part Number
C8051F023R
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F023R

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1035-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F023R
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F020/1/2/3
224
Bits7-0:
Bits7-0:
Bits7-0:
R/W
R/W
R/W
Bit7
Bit7
Bit7
SBUF1.[7:0]: UART1 Buffer Bits 7-0 (MSB-LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When data is
written to SBUF1, it goes to the transmit shift register and is held for serial transmission. Writing a
byte to SBUF1 is what initiates the transmission. A read of SBUF1 returns the contents of the receive
latch.
SADDR1.[7:0]: UART1 Slave Address
The contents of this register are used to define the UART1 slave address. Register SADEN1 is a bit
mask to determine which bits of SADDR1 are checked against a received address: corresponding bits
set to logic 1 in SADEN1 are checked; corresponding bits set to logic 0 are “don’t cares”.
SADEN1.[7:0]: UART1 Slave Address Enable
Bits in this register enable corresponding bits in register SADDR1 to determine the UART1 slave
address.
0: Corresponding bit in SADDR1 is a “don’t care”.
1: Corresponding bit in SADDR1 is checked against a received address.
Figure 21.11. SADEN1: UART1 Slave Address Enable Register
R/W
R/W
R/W
Bit6
Bit6
Bit6
Figure 21.10. SADDR1: UART1 Slave Address Register
Figure 21.9. SBUF1: UART1 Data Buffer Register
R/W
R/W
R/W
Bit5
Bit5
Bit5
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.4
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
00000000
00000000
Reset Value
Reset Value
Reset Value
0xAE
0xF2
0xF3

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