SAF-C167CS-L16M 3V CA+ Infineon Technologies, SAF-C167CS-L16M 3V CA+ Datasheet
SAF-C167CS-L16M 3V CA+
Specifications of SAF-C167CS-L16M 3V CA+
F167CSL16M3VCAZXT
SAFC167CSL16M3VCAT
SP000017109
SP000103470
Related parts for SAF-C167CS-L16M 3V CA+
SAF-C167CS-L16M 3V CA+ Summary of contents
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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C167CS-3V Revision History: Previous Version: Page Subjects (major changes) Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback ...
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Single-Chip Microcontroller C166 Family C167CS-3V • High Performance 16-bit CPU with 4-Stage Pipeline – 125 ns Instruction Cycle Time at 16 MHz CPU Clock – 625 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to ...
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... Table 1 C167CS-3V Derivative Synopsis 1) Derivative SAB-C167CS-L16M3V SAF-C167CS-L16M3V 1) This Data Sheet is valid for devices starting with and including design step BA. For simplicity all versions are referred to by the term C167CS-3V throughout this document. Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product ...
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Introduction The C167CS-3V derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance ( million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also ...
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P6.0/CS0 1 P6.1/CS1 2 P6.2/CS2 3 P6.3/CS3 4 P6.4/CS4 5 P6.5/HOLD 6 P6.6/HLDA 7 P6.7/BREQ 8 *P8.0/CC16IO 9 *P8.1/CC17IO 10 *P8.2/CC18IO 11 *P8.3/CC19IO 12 P8.4/CC20IO 13 P8.5/CC21IO 14 P8.6/CC22IO 15 P8.7/CC23IO P7.0/POUT0 19 ...
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Table 2 Pin Definitions and Functions Symbol Pin Input Num. Outp P6.6 7 I/O P6 P8.0 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P7.4 23 I/O P7.5 24 I/O P7.6 25 I/O P7 ...
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... CAPCOM1: CC15 Capture Inp./Compare Outp., EX7IN Fast External Interrupt 7 Input, T7IN CAPCOM2: Timer T7 Count Input Note: During Sleep Mode a spike filter on the EXnIN interrupt inputs suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. 7 C167CS-L16M3V Low Power V1.0, 2001-10 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P3.8 75 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P4.7 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. ALE PORT0 IO P0L.0-7 100- 107 P0H.0-7 108, 111- 117 Data Sheet Function Address Latch Enable Output. Can be used for latching the ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. PORT1 IO P1L.0-7 118- 125 P1H.0-7 128- 135 P1L.0 118 I P1L.1 119 I P1L.2 120 I P1L.3 121 I P1L.4 122 I P1L.5 123 I P1L.6 124 ...
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... An internal pullup resistor permits power-on reset using only a capacitor connected to A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. V 17, 46, – DD 56, 72, 82, 93, 109, 126, 136, 144 V 18, 45, – SS 55, 71, 83, 94, 110, 127, 139, 143 1) The ...
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Functional Description The architecture of the C167CS-3V combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. ...
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Memory Organization The memory space of the C167CS-3V is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire ...
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...
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Note: When one or both of the on-chip CAN Modules are used with the interface lines assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to ...
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The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...
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Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C167CS-3V is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...
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Table 3 C167CS-3V Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...
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Table 3 C167CS-3V Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...
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The C167CS-3V also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse ...
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Table 5 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only ...
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CPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 16 Capture Inputs 16 Compare Outputs CCxIO CPU GPT2 Timer T6 Over/Underflow ...
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of ...
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This allows the C167CS-3V to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN ...
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Real Time Clock The Real Time Clock (RTC) module of the C167CS-3V consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). ...
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A/D Converter For analog signal measurement, a 10-bit A/D converter with 24 multiplexed input channels (16 standard channels and 8 extension channels) and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The ...
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...
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... Port 4 cannot be used. This will limit the external address space. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’ ...
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Parallel Ports The C167CS-3V provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction ...
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Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on ...
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Power Management The C167CS-3V provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the C167CS-3V into ...
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Instruction Set Summary Table 6 lists the instructions of the C167CS- condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the ...
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Table 6 Instruction Set Summary (cont’d) Mnemonic Description MOV(B) Move word (byte) data MOVBS Move byte operand to word operand with sign extension MOVBZ Move byte operand to word operand. with zero extension JMPA, JMPI, Jump absolute/indirect/relative ...
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Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C167CS-3V in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address C1UAR EFn2 H C1UGML EF08 H C1UMLM EF0C H C2BTR EE04 H C2CSR EE00 H C2GMS EE06 H C2PCIR EE02 H C2LGML EE0A H C2LMLM EE0E H C2UAR EEn2 ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address CC17 FE62 H CC17IC b F162 H CC18 FE64 H CC18IC b F164 H CC19 FE66 H CC19IC b F166 H CC1IC b FF7A H CC2 FE84 H CC20 ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address CC30 FE7C H CC30IC b F18C H CC31 FE7E H CC31IC b F194 H CC3IC b FF7E H CC4 FE88 H CC4IC b FF80 H CC5 FE8A H CC5IC ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address DP1L b F104 H DP1H b F106 H DP2 b FFC2 H DP3 b FFC6 H DP4 b FFCA H DP6 b FFCE H DP7 b FFD2 H DP8 ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address ONES b FF1E H P0H b FF02 H P0L b FF00 H P1DIDIS FEA4 H P1H b FF06 H P1L b FF04 FFC0 ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address POCON4 F08C H POCON6 F08E H POCON7 F090 H POCON8 F092 H PP0 F038 H PP1 F03A H PP2 F03C H PP3 F03E H PSW b FF10 H PT0 ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C H S0TBUF FEB0 H S0TIC b FF6C H SP FE12 H SSCBR F0B4 H SSCCON b FFB2 H SSCEIC ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address T14 F0D2 H T14REL F0D0 H T2 FE40 H T2CON b FF40 H T2IC b FF60 H T3 FE42 H T3CON b FF42 H T3IC b FF62 H T4 ...
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Table 7 C167CS-3V Registers, Ordered by Name (cont’d) Name Physical Address XP3IC b F19E H XPERCON F024 H ZEROS b FF1C H 1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source. ...
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Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature Voltage on V pins with DD V respect to ground ( ) SS Voltage on any pin with respect to ground ( Input ...
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... DD V > < C167CS-L16M3V Low Power Unit Notes V Active mode MHz CPUmax V PowerDown mode V Reference voltage 2)3) mA Per pin Pin drivers in fast edge mode C SAB-C167CS-3V … C SAF-C167CS-3V … C SAK-C167CS-3V … -0.5 V). The absolute sum of input overload V1.0, 2001-10 4) ...
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CS- 3V and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in ...
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DC Characteristics (cont’d) (Operating Conditions apply) Parameter 5) RSTIN active current READY/RD/WR inact. current READY/RD/WR active current 8) ALE inactive current 8) ALE active current 8) Port 6 inactive current 8) Port 6 active current PORT0 configuration current XTAL1 input ...
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Table 10 Current Limits for Port Output Drivers Port Output Driver Maximum Output Current I ( (PORT0, PORT1, ----- Port 2, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT, 2) RSTIN ) All other outputs ----- 1) An output current ...
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3000 2000 1000 10 Figure 9 Idle and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet C167CS-L16M3V Low Power I IDOmax I IDOtyp I PDRmax I PDOmax 40 f [MHz] ...
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I [mA] 140 120 100 Figure 10 Supply/Idle Current as a Function of Operating Frequency Data Sheet C167CS-L16M3V Low Power I DD3max I DD3typ I IDX3max I IDX3typ 40 f [MHz] CPU ...
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AC Characteristics Definition of Internal Timing The internal operation of the C167CS-3V is controlled by the internal CPU clock Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the ...
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P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Table 11 C167CS-3V Clock Generation Modes CLKCFG CPU ...
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The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As ...
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Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the ...
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AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 12 External Clock Drive Characteristics Parameter Symbol Oscillator period OSC 2) t High time Low time Rise ...
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A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source ...
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Not 100% tested, guaranteed by design and characterization. 7) During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach its final voltage level within After the end of the sample ...
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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at Figure 14 Input Output Waveforms V + 0.1 V ...
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AC Characteristics Table 15 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle time is influenced by the PLL jitter (given value applies to For a ...
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Table 17 External Bus Cycle Timing (Operating Conditions apply) Parameter Output delay from CLKOUT falling edge Valid for: address (MUX on PORT0), write data out Output delay from CLKOUT edge Valid for: latched CS, ALE (normal) Output delay from CLKOUT ...
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Some of these interdependencies are described as relative timing (see below additional notes (see standard timing). Table 18 External Bus Relative Timing (Operating Conditions apply) Parameter Output hold time after WR rising edge Valid ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A0, BHE WRL, WRH, WR, WrCS D15-D0 Note: Write data is deactivated 1 TCL earlier if early write is enabled (same timing). Figure 17 Demultiplexed Bus, Write ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A0, BHE RD, RdCS D15-D0 Figure 18 Demultiplexed Bus, Read Access Data Sheet Normal ALE Cycle Extended ALE Cycle ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A16, BHE WRL, WRH, WR, WrCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Note: Write data is deactivated 2 TCL earlier if early write ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A16, BHE RD, RdCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Figure 20 Multiplexed Bus, Read Access Data Sheet Normal ALE Cycle tc 11 ...
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... These timings are given for test purposes only, in order to assure recognition at a specific clock edge. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT must fulfill in order to be safely synchronized. 27 Proper deactivation of READY is guaranteed if READY is deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). ...
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Running Cycle CLKOUT D15-D0 D15-D0 Command (RD, WR) Synchronous READY tc 25 Asynchronous 4) 3) READY Figure 21 READY Timing Data Sheet ...
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External Bus Arbitration Table 20 Bus Arbitration Timing (Operating Conditions apply) Parameter HOLD input setup time to CLKOUT falling edge CLKOUT to BREQ delay CLKOUT to HLDA delay 1) CSx release CSx drive 1) Other signals release 1) Other signals ...
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CLKOUT tc 28 HOLD HLDA BREQ CS Other Signals Figure 22 External Bus Arbitration, Releasing the Bus Notes 1) The C167CS-3V will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ ...
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CLKOUT HOLD HLDA BREQ CS Other Signals Figure 23 External Bus Arbitration, (Regaining the Bus) Notes 4) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by ...
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External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CS-3V can be accessed (during hold states external master like an asynchronous SRAM. Table 21 XRAM Access Timing (Operating Conditions apply) Parameter Address setup time ...
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Package Outlines P-MQFP-144-6 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet C167CS-L16M3V 76 Low Power Dimensions in mm V1.0, ...
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