MICRO CTRL 4K 4MHZ OTP 44PLCC

 

PIC16C74-04/L

Manufacturer Part NumberPIC16C74-04/L
DescriptionMICRO CTRL 4K 4MHZ OTP 44PLCC
ManufacturerMicrochip Technology
SeriesPIC® 16C
PIC16C74-04/L datasheets

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Specifications of PIC16C74-04/L

Core ProcessorPICCore Size8-Bit
Speed4MHzConnectivityI²C, SPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o33
Program Memory Size7KB (4K x 14)Program Memory TypeOTP
Ram Size192 x 8Voltage - Supply (vcc/vdd)4 V ~ 6 V
Data ConvertersA/D 8x8bOscillator TypeExternal
Operating Temperature0°C ~ 70°CPackage / Case44-PLCC
For Use WithDVA16XL441 - ADAPTER DEVICE ICE 44PLCCLead Free Status / RoHS StatusRequest inventory verification / Request inventory verification
Eeprom Size-  
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PIC16C7X
12.3
USART Synchronous Master Mode
Applicable Devices
72 73 73A 74 74A 76 77
In Synchronous Master mode, the data is transmitted in
a half-duplex manner i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RC6/TX/CK and RC7/RX/DT I/O pins to
CK (clock) and DT (data) lines respectively. The Master
mode indicates that the processor transmits the master
clock on the CK line. The Master mode is entered by
setting bit CSRC (TXSTA<7>).
12.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 12-7. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 12-13). This is advantageous when slow
baud rates are selected, since the BRG is kept in reset
when bits TXEN, CREN, and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
DS30390E-page 110
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If either bit CREN or bit SREN is set, during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
reset although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from hi-impedance
receive mode to transmit and start driving. To avoid
this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3.
If interrupts are desired, then set enable bit
TXIE.
4.
If 9-bit transmission is desired, then set bit TX9.
5.
Enable the transmission by setting bit TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the
TXREG register.
1997 Microchip Technology Inc.

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