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PIC16C74-04/L
PIC16C74-04/L | |
|---|---|
| Manufacturer Part Number | PIC16C74-04/L |
| Description | MICRO CTRL 4K 4MHZ OTP 44PLCC |
| Manufacturer | Microchip Technology |
| Series | PIC® 16C |
| PIC16C74-04/L datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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Specifications of PIC16C74-04/L | |||
|---|---|---|---|
| Core Processor | PIC | Core Size | 8-Bit |
| Speed | 4MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | POR, PWM, WDT | Number Of I /o | 33 |
| Program Memory Size | 7KB (4K x 14) | Program Memory Type | OTP |
| Ram Size | 192 x 8 | Voltage - Supply (vcc/vdd) | 4 V ~ 6 V |
| Data Converters | A/D 8x8b | Oscillator Type | External |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 44-PLCC |
| For Use With | DVA16XL441 - ADAPTER DEVICE ICE 44PLCC | Lead Free Status / RoHS Status | Request inventory verification / Request inventory verification |
| Eeprom Size | - | ||
PrevNext
14.4.5
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 14-10,
Figure 14-11,
and
Figure 14-12
depict
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 14-11). This is useful for testing purposes or to
synchronize more than one PIC16CXX device operat-
ing in parallel.
Table 14-7 shows the reset conditions for some special
function registers, while Table 14-8 shows the reset
conditions for all the registers.
TABLE 14-3:
TIME-OUT IN VARIOUS SITUATIONS, PIC16C73/74
Oscillator Configuration
XT, HS, LP
RC
TABLE 14-4:
TIME-OUT IN VARIOUS SITUATIONS, PIC16C72/73A/74A/76/77
Oscillator Configuration
PWRTE = 0
XT, HS, LP
72 ms + 1024T
RC
72 ms
TABLE 14-5:
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C73/74
POR
TO
PD
0
1
1
0
0
x
0
x
0
1
0
1
1
0
0
1
u
u
1
1
0
Legend: u = unchanged, x = unknown
1997 Microchip Technology Inc.
14.4.6
POWER CONTROL/STATUS REGISTER
(PCON)
Applicable Devices
72 73 73A 74 74A 76 77
The Power Control/Status Register, PCON has up to
two bits, depending upon the device. Bit0 is not imple-
mented on the PIC16C73 or PIC16C74.
time-out
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable
if the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Power-up
PWRTE = 1
PWRTE = 0
72 ms + 1024T
1024T
OSC
OSC
72 ms
—
Power-up
Brown-out
PWRTE = 1
1024T
72 ms + 1024T
OSC
OSC
—
72 ms
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
PIC16C7X
Wake-up from SLEEP
1024 T
OSC
—
Wake-up from SLEEP
1024T
OSC
OSC
—
DS30390E-page 135
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