MICRO CTRL 4K 4MHZ OTP 44PLCC

 

PIC16C74-04/L

Manufacturer Part NumberPIC16C74-04/L
DescriptionMICRO CTRL 4K 4MHZ OTP 44PLCC
ManufacturerMicrochip Technology
SeriesPIC® 16C
PIC16C74-04/L datasheets

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Warranty: 60 days

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Specifications of PIC16C74-04/L

Core ProcessorPICCore Size8-Bit
Speed4MHzConnectivityI²C, SPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o33
Program Memory Size7KB (4K x 14)Program Memory TypeOTP
Ram Size192 x 8Voltage - Supply (vcc/vdd)4 V ~ 6 V
Data ConvertersA/D 8x8bOscillator TypeExternal
Operating Temperature0°C ~ 70°CPackage / Case44-PLCC
For Use WithDVA16XL441 - ADAPTER DEVICE ICE 44PLCCLead Free Status / RoHS StatusRequest inventory verification / Request inventory verification
Eeprom Size-  
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PIC16C7X
14.7
Watchdog Timer (WDT)
Applicable Devices
72 73 73A 74 74A 76 77
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
by
clearing
configuration
(Section 14.1).
14.7.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
and process variations from part to part (see
DD
DC specs). If longer time-out periods are desired, a
FIGURE 14-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-6)
WDT Timer
WDT
Enable Bit
Note: PSA and PS2:PS0 are bits in the OPTION register.
FIGURE 14-19: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
2007h
Config. bits
(1)
81h,181h
OPTION
RBPU
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 14-1, and Figure 14-2 for operation of these bits.
DS30390E-page 144
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET con-
dition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
14.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (V
max. WDT prescaler) it may take several seconds
bit
WDTE
before a WDT time-out occurs.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
0
Postscaler
M
1
U
X
8
8 - to - 1 MUX
PSA
0
1
MUX
WDT
Time-out
Bit 6
Bit 5
Bit 4
Bit 3
(1)
CP1
CP0
BODEN
PWRTE
INTEDG
T0CS
T0SE
PSA
= Min., Temperature = Max., and
DD
PS2:PS0
To TMR0 (Figure 7-6)
PSA
Bit 2
Bit 1
Bit 0
(1)
WDTE
FOSC1
FOSC0
PS2
PS1
PS0
1997 Microchip Technology Inc.