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PIC16C74-04/L
PIC16C74-04/L | |
|---|---|
| Manufacturer Part Number | PIC16C74-04/L |
| Description | MICRO CTRL 4K 4MHZ OTP 44PLCC |
| Manufacturer | Microchip Technology |
| Series | PIC® 16C |
| PIC16C74-04/L datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
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Specifications of PIC16C74-04/L | |||
|---|---|---|---|
| Core Processor | PIC | Core Size | 8-Bit |
| Speed | 4MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | POR, PWM, WDT | Number Of I /o | 33 |
| Program Memory Size | 7KB (4K x 14) | Program Memory Type | OTP |
| Ram Size | 192 x 8 | Voltage - Supply (vcc/vdd) | 4 V ~ 6 V |
| Data Converters | A/D 8x8b | Oscillator Type | External |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 44-PLCC |
| For Use With | DVA16XL441 - ADAPTER DEVICE ICE 44PLCC | Lead Free Status / RoHS Status | Request inventory verification / Request inventory verification |
| Eeprom Size | - | ||
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PrevNext
2
FIGURE 19-11: I
C BUS DATA TIMING
103
SCL
90
91
SDA
In
109
SDA
Out
Note: Refer to Figure 19-1 for load conditions
2
TABLE 19-10: I
C BUS DATA REQUIREMENTS
Parameter
Sym
Characteristic
No.
100
T
Clock high time
HIGH
101
T
Clock low time
LOW
102
T
SDA and SCL rise
R
time
103
T
SDA and SCL fall time 100 kHz mode
F
90
T
:
START condition
SU
STA
setup time
91
T
:
START condition hold
HD
STA
time
106
T
:
Data input hold time
HD
DAT
107
T
:
Data input setup time
SU
DAT
92
T
:
STOP condition setup
SU
STO
time
109
T
Output valid from
AA
clock
110
T
Bus free time
BUF
Cb
Bus capacitive loading
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2: A fast-mode (400 kHz) I
C-bus device can be used in a standard-mode (100 kHz) I
tsu;DAT
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
T
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
R
released.
1997 Microchip Technology Inc.
Applicable Devices 72 73 73A 74 74A 76 77
100
101
106
107
109
Min
Max
100 kHz mode
4.0
—
400 kHz mode
0.6
—
SSP Module
1.5T
—
CY
100 kHz mode
4.7
—
400 kHz mode
1.3
—
SSP Module
1.5T
—
CY
100 kHz mode
—
1000
400 kHz mode
20 + 0.1Cb
300
—
300
400 kHz mode
20 + 0.1Cb
300
100 kHz mode
4.7
—
400 kHz mode
0.6
—
100 kHz mode
4.0
—
400 kHz mode
0.6
—
100 kHz mode
0
—
400 kHz mode
0
0.9
100 kHz mode
250
—
400 kHz mode
100
—
100 kHz mode
4.7
—
400 kHz mode
0.6
—
100 kHz mode
—
3500
400 kHz mode
—
—
100 kHz mode
4.7
—
400 kHz mode
1.3
—
—
400
2
C bus specification) before the SCL line is
PIC16C7X
102
92
110
Units
Conditions
s
Device must operate at a mini-
mum of 1.5 MHz
s
Device must operate at a mini-
mum of 10 MHz
s
Device must operate at a mini-
mum of 1.5 MHz
s
Device must operate at a mini-
mum of 10 MHz
ns
ns
Cb is specified to be from
10 to 400 pF
ns
ns
Cb is specified to be from
10 to 400 pF
s
Only relevant for repeated
START condition
s
s
After this period the first clock
pulse is generated
s
ns
s
ns
Note 2
ns
s
s
ns
Note 1
ns
s
Time the bus must be free
before a new transmission can
s
start
pF
2
C-bus system, but the requirement
DS30390E-page 215
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