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PIC16C74-04/L
PIC16C74-04/L | |
|---|---|
| Manufacturer Part Number | PIC16C74-04/L |
| Description | MICRO CTRL 4K 4MHZ OTP 44PLCC |
| Manufacturer | Microchip Technology |
| Series | PIC® 16C |
| PIC16C74-04/L datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
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Specifications of PIC16C74-04/L | |||
|---|---|---|---|
| Core Processor | PIC | Core Size | 8-Bit |
| Speed | 4MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | POR, PWM, WDT | Number Of I /o | 33 |
| Program Memory Size | 7KB (4K x 14) | Program Memory Type | OTP |
| Ram Size | 192 x 8 | Voltage - Supply (vcc/vdd) | 4 V ~ 6 V |
| Data Converters | A/D 8x8b | Oscillator Type | External |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 44-PLCC |
| For Use With | DVA16XL441 - ADAPTER DEVICE ICE 44PLCC | Lead Free Status / RoHS Status | Request inventory verification / Request inventory verification |
| Eeprom Size | - | ||
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PrevNext
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt ser-
vice routine (if interrupts are used).
EXAMPLE 4-1:
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BSF
PCLATH,3
;Select page 1 (800h-FFFh)
BCF
PCLATH,4
;Only on >4K devices
CALL
SUB1_P1
;Call subroutine in
:
;page 1 (800h-FFFh)
:
:
ORG 0x900
SUB1_P1:
;called subroutine
:
;page 1 (800h-FFFh)
:
RETURN
;return to Call subroutine
;in page 0 (000h-7FFh)
FIGURE 4-18: DIRECT/INDIRECT ADDRESSING
Direct Addressing
from opcode
RP1:RP0
6
bank select
location select
00h
Data
Memory
7Fh
Bank 0
For register file map detail see Figure 4-4, and Figure 4-5.
1997 Microchip Technology Inc.
4.5
Indirect Addressing, INDF and FSR
Registers
Applicable Devices
72 73 73A 74 74A 76 77
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-18.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2:
movlw
movwf
NEXT
clrf
incf
btfss
goto
CONTINUE
:
0
IRP
bank select
00
01
10
11
80h
100h
180h
not used
FFh
17Fh
1FFh
Bank 1
Bank 2
Bank 3
PIC16C7X
INDIRECT ADDRESSING
0x20
;initialize pointer
FSR
;to RAM
INDF
;clear INDF register
FSR,F
;inc pointer
FSR,4
;all done?
NEXT
;no clear next
;yes continue
Indirect Addressing
7
0
FSR register
location select
DS30390E-page 41
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