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- Integrated Circuits (ICs)/
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PIC16C74-04/L
PIC16C74-04/L | |
|---|---|
| Manufacturer Part Number | PIC16C74-04/L |
| Description | MICRO CTRL 4K 4MHZ OTP 44PLCC |
| Manufacturer | Microchip Technology |
| Series | PIC® 16C |
| PIC16C74-04/L datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
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Specifications of PIC16C74-04/L | |||
|---|---|---|---|
| Core Processor | PIC | Core Size | 8-Bit |
| Speed | 4MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | POR, PWM, WDT | Number Of I /o | 33 |
| Program Memory Size | 7KB (4K x 14) | Program Memory Type | OTP |
| Ram Size | 192 x 8 | Voltage - Supply (vcc/vdd) | 4 V ~ 6 V |
| Data Converters | A/D 8x8b | Oscillator Type | External |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 44-PLCC |
| For Use With | DVA16XL441 - ADAPTER DEVICE ICE 44PLCC | Lead Free Status / RoHS Status | Request inventory verification / Request inventory verification |
| Eeprom Size | - | ||
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PrevNext
PIC16C7X
8.5
Resetting Timer1 using a CCP Trigger
Output
Applicable Devices
72 73 73A 74 74A 76 77
The CCP2 module is not implemented on the
PIC16C72 device.
If the CCP1 or CCP2 module is configured in compare
mode
to
generate
a
“special
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Note:
The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 8-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address
Name
Bit 7
Bit 6
0Bh,8Bh,
INTCON
GIE
PEIE
10Bh,18Bh
(1,2)
0Ch
PIR1
PSPIF
ADIF
(1,2)
8Ch
PIE1
PSPIE
ADIE
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
—
—
Legend:
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
DS30390E-page 68
8.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
Applicable Devices
72 73 73A 74 74A 76 77
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 and CCP2
special event triggers.
event
trigger"
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
8.7
Timer1 Prescaler
Applicable Devices
72 73 73A 74 74A 76 77
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Bit 5
Bit 4
Bit 3
Bit 2
T0IE
INTE
RBIE
T0IF
(2)
(2)
RCIF
TXIF
SSPIF
CCP1IF
(2)
(2)
RCIE
TXIE
SSPIE
CCP1IE
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Value on:
Value on
Bit 1
Bit 0
POR,
all other
BOR
resets
0000 000x 0000 000u
INTF
RBIF
0000 0000 0000 0000
TMR2IF
TMR1IF
0000 0000 0000 0000
TMR2IE
TMR1IE
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1997 Microchip Technology Inc.
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