- Components/
- Integrated Circuits (ICs)/
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PIC16C74-04/L
PIC16C74-04/L | |
|---|---|
| Manufacturer Part Number | PIC16C74-04/L |
| Description | MICRO CTRL 4K 4MHZ OTP 44PLCC |
| Manufacturer | Microchip Technology |
| Series | PIC® 16C |
| PIC16C74-04/L datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of PIC16C74-04/L | |||
|---|---|---|---|
| Core Processor | PIC | Core Size | 8-Bit |
| Speed | 4MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | POR, PWM, WDT | Number Of I /o | 33 |
| Program Memory Size | 7KB (4K x 14) | Program Memory Type | OTP |
| Ram Size | 192 x 8 | Voltage - Supply (vcc/vdd) | 4 V ~ 6 V |
| Data Converters | A/D 8x8b | Oscillator Type | External |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 44-PLCC |
| For Use With | DVA16XL441 - ADAPTER DEVICE ICE 44PLCC | Lead Free Status / RoHS Status | Request inventory verification / Request inventory verification |
| Eeprom Size | - | ||
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PrevNext
To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear enable bit SSPEN, re-initialize SSPCON
register, and then set enable bit SSPEN. This config-
ures the SDI, SDO, SCK, and SS pins as serial port
pins. For the pins to behave as the serial port function,
they must have their data direction bits (in the TRIS reg-
ister) appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set (if implemented)
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
Figure 11-4 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
FIGURE 11-4: SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF register)
Shift Register
(SSPSR)
MSb
PROCESSOR 1
1997 Microchip Technology Inc.
Applicable Devices
72 73 73A 74 74A 76 77
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched interrupt flag bit SSPIF (PIR1<3>) is
set.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 11-5 and Figure 11-6 where the MSB is trans-
mitted first. In master mode, the SPI clock rate (bit rate)
is user programmable to be one of the following:
• Fosc/4 (or T
• Fosc/16 (or 4 T
• Fosc/64 (or 16 T
• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.
In sleep mode, the slave can transmit and receive data
and wake the device from sleep.
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
SDI
SDO
LSb
Serial Clock
SCK
SCK
PIC16C7X
)
CY
)
CY
)
CY
Serial Input Buffer
(SSPBUF register)
Shift Register
(SSPSR)
MSb
LSb
PROCESSOR 2
DS30390E-page 81
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