MICRO CTRL 4K 4MHZ OTP 44PLCC

 

PIC16C74-04/L

Manufacturer Part NumberPIC16C74-04/L
DescriptionMICRO CTRL 4K 4MHZ OTP 44PLCC
ManufacturerMicrochip Technology
SeriesPIC® 16C
PIC16C74-04/L datasheets

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Warranty: 60 days

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Specifications of PIC16C74-04/L

Core ProcessorPICCore Size8-Bit
Speed4MHzConnectivityI²C, SPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o33
Program Memory Size7KB (4K x 14)Program Memory TypeOTP
Ram Size192 x 8Voltage - Supply (vcc/vdd)4 V ~ 6 V
Data ConvertersA/D 8x8bOscillator TypeExternal
Operating Temperature0°C ~ 70°CPackage / Case44-PLCC
For Use WithDVA16XL441 - ADAPTER DEVICE ICE 44PLCCLead Free Status / RoHS StatusRequest inventory verification / Request inventory verification
Eeprom Size-  
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Page 84/289

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PIC16C7X
FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C76/77)
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
bit7
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even
if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each
new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
2
In I
C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I
C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
2
In I
C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = F
0001 = SPI master mode, clock = F
0010 = SPI master mode, clock = F
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
2
0110 = I
C slave mode, 7-bit address
2
0111 = I
C slave mode, 10-bit address
2
1011 = I
C firmware controlled master mode (slave idle)
2
1110 = I
C slave mode, 7-bit address with start and stop bit interrupts enabled
2
1111 = I
C slave mode, 10-bit address with start and stop bit interrupts enabled
DS30390E-page 84
Applicable Devices
72 73 73A 74 74A 76 77
R/W-0
R/W-0
R/W-0
R/W-0
SSPM3
SSPM2
SSPM1
SSPM0
bit0
/4
OSC
/16
OSC
/64
OSC
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
1997 Microchip Technology Inc.