MICRO CTRL 4K 4MHZ OTP 44PLCC

 

PIC16C74-04/L

Manufacturer Part NumberPIC16C74-04/L
DescriptionMICRO CTRL 4K 4MHZ OTP 44PLCC
ManufacturerMicrochip Technology
SeriesPIC® 16C
PIC16C74-04/L datasheets

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Specifications of PIC16C74-04/L

Core ProcessorPICCore Size8-Bit
Speed4MHzConnectivityI²C, SPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o33
Program Memory Size7KB (4K x 14)Program Memory TypeOTP
Ram Size192 x 8Voltage - Supply (vcc/vdd)4 V ~ 6 V
Data ConvertersA/D 8x8bOscillator TypeExternal
Operating Temperature0°C ~ 70°CPackage / Case44-PLCC
For Use WithDVA16XL441 - ADAPTER DEVICE ICE 44PLCCLead Free Status / RoHS StatusRequest inventory verification / Request inventory verification
Eeprom Size-  
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Download datasheet (3Mb)Embed
PrevNext
Figure 11-19 and Figure 11-20 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE
For 7-bit address:
S
Slave Address R/W A Data A Data A/A P
'0' (write)
data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
S = Start Condition
From slave to master
P = Stop Condition
FIGURE 11-20: MASTER-RECEIVER SEQUENCE
For 7-bit address:
S
Slave Address R/W A Data A Data A P
'1' (read)
data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
S = Start Condition
From slave to master
P = Stop Condition
FIGURE 11-21: COMBINED FORMAT
(read or write)
(n bytes + acknowledge)
S
Slave Address R/W A Data A/A Sr
(read)
Sr = repeated
Start Condition
Transfer direction of data and acknowledgment bits depends on R/W bits.
Combined format:
Sr
Slave Address
R/W A
Slave Address
First 7 bits
Second byte
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
S = Start Condition
From slave to master
P = Stop Condition
1997 Microchip Technology Inc.
Applicable Devices
72 73 73A 74 74A 76 77
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.
For 10-bit address:
S
Slave Address
First 7 bits
(write)
Data A
A master transmitter addresses a slave receiver
with a 10-bit address.
For 10-bit address:
S
Slave Address
R/W A1 Slave Address
First 7 bits
(write)
Sr
Slave Address
First 7 bits
A master transmitter addresses a slave receiver
with a 10-bit address.
Slave Address R/W A Data A/A
P
(write)
Direction of transfer
may change at this point
A
Data
A
Data A/A
Sr Slave Address
First 7 bits
PIC16C7X
R/W A1 Slave Address
A2
Second byte
Data
A/A
P
A2
Second byte
R/W A3
Data A
Data
A
P
(read)
R/W A Data A
Data
A P
(read)
DS30390E-page 91

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