AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet

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... PDIP and 32-pin TQFP • Operating Voltage – 2.7V - 6.0V (AT90LS2333 and AT90LS4433) – 4.0V - 6.0V (AT90S2333 and AT90S4433) • Speed Grades – MHz (AT90LS2333 and AT90LS4433) – MHz (AT90S2333 and AT90S4433) Pin Configurations TQFP Top View (INT1) PD3 1 24 ...

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... The AT90S2333/4433 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Table 1. Comparison Table Device Flash AT90S2333 2K AT90LS2333 2K AT90S4433 4K AT90LS4433 4K AT90S/LS2333 and AT90S/LS4433 2 ...

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Block Diagram Figure 1. The AT90S2333/4433 Block Diagram VCC GND AVCC ANALOG MUX AGND AREF PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES PROGRAMMING LOGIC DATA REGISTER PORTB AT90S/LS2333 and AT90S/LS4433 PC0 - PC5 PORTC DRIVERS DATA REGISTER ...

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Pin Descriptions VCC Supply voltage GND Ground Port B (PB5..PB0) Port 6-bit bi-directional I/O port with internal pullup resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled ...

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Clock Options Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an on- chip oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or ...

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Architectural Overview The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands ...

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The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D- converters, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the register file, ...

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General Purpose Register File Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Figure 7. AVR CPU General Purpose Working Registers 7 General Purpose Working Registers All the register operating instructions in the instruction ...

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ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are ...

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The 32 general purpose working registers, 64 I/O registers and the 128 bytes of internal data SRAM in the AT90S2333/4433 are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing ...

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I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word the destination or source register address. Data Direct Figure 13. Direct Data Addressing A 16-bit Data Address is contained in ...

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Data Indirect Figure 15. Data Indirect Addressing 15 Operand address is the contents of the the Z-register. Data Indirect with Pre-Decrement Figure 16. Data Indirect Addressing with Pre-Decrement 15 The the Z-register is decremented ...

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Constant Addressing Using the LPM Instruction Figure 18. Code Memory Constant Addressing Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K/2K), the LSB selects low byte if cleared (LSB = 0) ...

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EEPROM Data Memory The AT90S2333/4433 contains 128/256 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles ...

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Figure 23. On-Chip Data SRAM Access Cycles System Clock Ø Address I/O Memory The I/O space definition of the AT90S2333/4433 is shown in the following table: Table 2. AT90S2333/4433 I/O Space I/O Address (SRAM Address) Name $3F ($5F) SREG $3D ...

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Table 2. AT90S2333/4433 I/O Space (Continued) I/O Address (SRAM Address) Name $15 ($35) PORTC $14 ($34) DDRC $13 ($33) PINC $12 ($32) PORTD $11 ($31) DDRD $10 ($30) PIND $0F ($2F) SPDR $0E ($2E) SPSR $0D ($2D) SPCR $0C ($2C) ...

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Status Register - SREG The AVR status register - SREG - at I/O space location $3F ($5F) is defined as: Bit 7 6 $3F ($5F Read/Write R/W R/W Initial value 0 0 • Bit Global ...

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Stack with return from subroutine RET or return from interrupt RETI. Reset and Interrupt Handling The AT90S2333/4433 provides 13 different interrupt sources. These interrupts and the ...

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MAIN: $00f $010 … … Reset Sources The AT90S2333/4433 has four sources of reset: • Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V • External Reset. The MCU is reset ...

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Table 5. Reset Delay Selections CKSEL [2:0] Start-Up Time, t TOUT 000 001 6 CK 010 256 ms + 16K CK 011 16K CK 100 16K CK 101 256 ...

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Figure 26. MCU Start-Up, RESET Controlled Externally VCC RESET TIME-OUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the ...

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Figure 28. Brown-Out Reset During Operation RESET TIME-OUT INTERNAL RESET Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts ...

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To make use of the reset flags to identify a reset condition, the user should read and then clear the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of ...

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General Interrupt Flag Register - GIFR Bit 7 6 $3A ($5A) INTF1 INTF0 Read/Write R/W R/W Initial value 0 0 • Bit 7 - INTF1: External Interrupt Flag1 When an event on the INT1 pin triggers an interrupt request, INTF1 ...

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Timer/Counter Interrupt Flag Register - TIFR Bit 7 6 $38 ($58) TOV1 OCF1 Read/Write R/W R/W Initial value 0 0 • Bit 7 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 ...

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MCU Control Register - MCUCR The MCU Control Register contains control bits for general MCU functions. Bit 7 6 $35 ($55 Read/Write R R Initial value 0 0 • Bits Res: Reserved bit These bits ...

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The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If ...

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Timer / Counters The AT90S2333/4433 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters can either be used as a ...

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Figure 31. Timer/Counter0 Block Diagram Timer/Counter0 Control Register - TCCR0 Bit 7 6 $33 ($53 Read/Write R R Initial value 0 0 • Bits 7-3 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and ...

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Timer Counter 0 - TCNT0 Bit 7 6 $32 ($52) MSB Read/Write R/W R/W Initial value 0 0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is ...

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When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU ...

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Bits 5..2 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and always read zero. • Bits 1,0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in ...

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Table 12. Clock 1 Prescale Select CS12 CS11 CS10 The Stop condition provides a Timer Enable/Disable ...

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Timer/Counter1 Output Compare Register - OCR1H and OCR1L Bit 15 14 $2B ($4B) MSB $2A ($4A Read/Write R/W R/W R/W R/W Initial value The output compare register is a 16-bit read/write register. The Timer/Counter1 ...

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COM11 and COM10 bits in the Timer/Counter1 Control Register TCCR1. Refer to Table 14 for details. Table 13. Timer TOP Values and PWM Frequency PWM Timer TOP Resolution value 8-bit ...

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Table 15. PWM Outputs OCR = $0000 or TOP COM11 COM10 PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter changes direction at $0000. Timer Overflow Interrupt1 operates exactly as in normal ...

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Bit 3 - WDE: Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE ...

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EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V ware detect when the next byte can be written. A special ...

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Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into ...

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Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S2333/4433 and peripheral devices or between several AVR devices. The AT90S2333/4433 SPI features include the following: • Full-Duplex, 3-Wire Synchronous Data Transfer • ...

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Figure 37. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift ...

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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 38 and Figure 39. Figure 38. ...

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Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK ...

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UART The AT90S2333/4433 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud rate generator generates any baud rate • High baud rates at low XTAL frequencies • 8 ...

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A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. ...

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The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start ...

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Each slave MCU reads the UDR register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving ...

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Bit 3 - OR: OverRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift ...

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For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 19. UBR values which yield an actual baud rate differing less than 2% from the target baud rate, are bold ...

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UART Baud Rate Register - UBRR Bit 15 14 $03 ($23 $09 ($29) MSB 7 6 Read/Write R R R/W R/W Initial value This is a 12-bit register which contains the UART Baud Rate ...

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Bit 6 - AINBG: Analog Comparator Bandgap Select When this bit is set BOD is enabled and the BODEN is programmed, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive input (AIN0) of ...

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Analog to Digital Converter Feature list: • 10-bit Resolution • ± 2 LSB Absolute Accuracy • 0.5 LSB Integral Non-Linearity • 260 µs Conversion Time • kSPS • 6 Multiplexed Input Channels • Rail-to-Rail Input ...

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The ADC is enabled by writing a logical one to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started after enabling the ADC, will be preceded by a dummy conversion to initialize the ADC. To the ...

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Figure 46. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle number 1 2 ADC clock ADEN ADSC Hold strobe ADIF ADCH ADCL Dummy Conversion Table 21. ADC Conversion Time Condition Sample Cycle Number 1st Conversion, Free Run 1st Conversion, ...

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Figure 48. ADC Timing Diagram, Free Run Conversion ADC Noise Canceler Function The ADC features a noise canceler that enables conversion during idle mode to reduce noise induced from the CPU core. To make use of this feature, the following ...

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ADC Control and Status Register - ADCSR Bit 7 6 $06 ($26) ADEN ADSC Read/Write R/W R/W Initial value 0 0 • Bit 7 - ADEN: ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing ...

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ADC Data Register - ADCL AND ADCH Bit 15 14 $05 ($25 $04 ($26) ADC7 ADC6 7 6 Read/Write Initial value When an ADC conversion is complete, the result is ...

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Figure 49. ADC Power Connections Note that since AV feeds the Port C output drivers, the RC network shown should not be employed if any Port C serve as CC outputs. ADC Characteristics - ...

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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direc- tion of one port pin can be changed without unintentionally changing the direction of any other pin with the ...

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The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading ...

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Figure 50. Port B Schematic Diagram (Pin PB0) PB0 WP: WD: RL: RP: RD: ACIC: ACO: Figure 51. Port B Schematic Diagram (Pin PB1) PB1 AT90S/LS2333 and AT90S/LS4433 MOS PULL WRITE PORTB WRITE DDRB NOISE CANCELER ...

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Figure 52. Port B Schematic Diagram (Pin PB2) PB2 WP: WD: RL: RP: RD: MSTR: SPE: Figure 53. Port B Schematic Diagram (Pin PB3) PB3 WP: WD: RL: RP: RD: SPE: MSTR AT90S/LS2333 and AT90S/LS4433 62 MOS PULL ...

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Figure 54. Port B Schematic Diagram (Pin PB4) PB4 WP: WD: RL: RP: RD: SPE: MSTR Figure 55. Port B Schematic Diagram (Pin PB5) PB5 WP: WD: RL: RP: RD: SPE: MSTR AT90S/LS2333 and AT90S/LS4433 MOS PULL- UP WRITE PORTB ...

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Port C Port 6-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data Direction Register - DDRC, $14($34) and the Port C ...

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Table 25. DDCn Effects on Port C Pins DDCn PORTCn Note: n: 5…0, pin number Port C Schematics Note that all port pins are synchronized. The synchronization latch is however, not shown ...

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Table 26. Port D Pins Alternate Functions Port Pin Alternate Function PD0 RXD (UART Input line) PD1 TXD (UART Output line) PD2 INT0 (External interrupt 0 input) PD3 INT1 (External interrupt 1 input) PD4 T0 (Timer/Counter 0 external counter input) ...

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Table 27. DDDn Bits on Port D Pins DDDn PORTDn Note: n: 7,6…0, pin number. Alternate Functions Of Port D • AIN1 - Port D, Bit 7 AIN1, Analog Comparator Negative Input. ...

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Port D Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 57. Port D Schematic Diagram (Pin PD0) PD0 Figure 58. Port D Schematic Diagram (Pin PD1) PD1 AT90S/LS2333 and ...

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Figure 59. Port D Schematic Diagram (Pins PD2 and PD3) Figure 60. Port D Schematic Diagram (Pins PD4 and PD5) PDn AT90S/LS2333 and AT90S/LS4433 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ ...

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Figure 61. Port D Schematic Diagram (Pins PD6 and PD7) PDn PWRDN: POWER DOWN MODE AT90S/LS2333 and AT90S/LS4433 70 MOS PULL PWRDN RP WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: ...

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... CKSEL2..0: See Table 5, “Reset Delay Selections”, for which combination of CKSEL2..0 to use. Default value is ‘010’. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space. ...

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... For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the serial programming mode. During programming, the supply voltage must be in accordance with Table 29. Table 29. Supply voltage during programming Part Serial programming AT90LS2333 2.7 - 6.0 V AT90S2333 4.0 - 6.0 V AT90LS4433 2 ...

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Table 30. Pin Name Mapping Signal Name in Programming Mode RDY/BSY XA0 XA1 DATA Table 31. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low ...

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Set XA1, XA0 to ‘10’. This enables command loading. 2. Set BS to ‘0’. 3. Set DATA to ‘1000 0000’. This is the command for Chip erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give ...

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Address high byte needs only be loaded before programming a new 256 word page in the Flash. • Skip writing the data value $FF, that is the contents of the entire Flash and EEPROM after a Chip Erase. These ...

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Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to Programming the Flash for details on Command, Address and Data loading Load Command ‘0001 0001’ Load Address Low Byte ($00 ...

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Bit 5 = SPIEN Fuse bit Bit 4 = BODLEVEL Fuse bit Bit 3 = BODEN Fuse bit Bit 2 = CKSEL2 Fuse bit Bit 1 = CKSEL1 Fuse bit Bit 0 = CKSEL0 Fuse bit 3. Set BS to ...

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Table 33. Parallel Programming Characteristics T Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP t Data and Control Setup before XTAL1 High DVXH t XTAL1 Pulse Width High XHXL t Data and Control Hold after XTAL1 ...

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For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first exe- cute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the ...

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Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 34 for P1 and P2 ...

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Table 35. Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable 1010 1100 Chip Erase 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read EEPROM 1010 0000 Memory Write EEPROM 1100 0000 Memory 1010 1100 Write ...

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Serial Programming Characteristics Figure 68. Serial Programming Timing Table 36. Serial Programming Characteristics 2.7 - 6.0V (Unless otherwise noted Symbol Parameter 1/t Oscillator Frequency (V CLCL t Oscillator Period ...

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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. - +125 C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1. Voltage on RESET with respect to Ground......-1.0V to +13.0V ...

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DC Characteristics 2.7V to 6.0V (unless otherwise noted) (Continued Symbol Parameter Analog Comparator Input V ACIO Offset Voltage Analog Comparator Input I ACLK Leakage A Analog Comparator t ACPD ...

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External Clock Drive Waveforms Figure 69. External Clock VIH1 VIL1 Table 39. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time ...

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Typical Characteristics The following charts show typical behavior. These data are characterized, but not tested. All current consumption measure- ments are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail ...

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Figure 71. Active Supply Current vs Figure 72. Idle Supply Current vs. Frequency AT90S/LS2333 and AT90S/LS4433 CC ...

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Figure 73. Idle Supply Current vs 2.5 Figure 74. Power Down Supply Current vs 2.5 AT90S/LS2333 and AT90S/LS4433 88 CC IDLE SUPPLY CURRENT ...

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Figure 75. Power Down Supply Current vs. V 120 100 Figure 76. Power Down Supply Current vs. V AT90S/LS2333 and AT90S/LS4433 CC POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 2.5 3 3.5 ...

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Figure 77. Analog Comparator Current vs. V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 Analog comparator offset voltage is measured as absolute offset Figure 78. Analog Comparator Offset Voltage vs. Common Mode Voltage AT90S/LS2333 and AT90S/LS4433 ...

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Figure 79. Analog Comparator Offset Voltage vs. Common Mode Voltage Figure 80. Analog Comparator Input Leakage Current -10 0 0.5 AT90S/LS2333 and AT90S/LS4433 ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Common Mode ...

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Figure 81. Watchdog Oscillator Frequency vs. V AT90S/LS2333 and AT90S/LS4433 92 CC WATCHDOG OSCILLATOR FREQUENCY vs ( ˚ ˚ A ...

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Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 82. Pull-Up Resistor Current vs. Input Voltage Figure 83. Pull-Up Resistor Current vs. Input Voltage AT90S/LS2333 and AT90S/LS4433 PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...

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Figure 84. I/O Pin Sink Current vs. Output Voltage Figure 85. I/O Pin Source Current vs. Output Voltage AT90S/LS2333 and AT90S/LS4433 94 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ˚ ...

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Figure 86. I/O Pin Sink Current vs. Output Voltage Figure 87. I/O Pin Source Current vs. Output Voltage AT90S/LS2333 and AT90S/LS4433 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ˚ ...

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Figure 88. I/O Pin Input Threshold Voltage vs. V Figure 89. I/O Pin Input Hysteresis vs. V AT90S/LS2333 and AT90S/LS4433 96 CC I/O PIN INPUT THRESHOLD VOLTAGE vs ˚ I/O PIN ...

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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) Reserved - $3D ($5D) SP SP7 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 $3A ($5A) GIFR INTF1 $39 ($59) TIMSK TOIE1 $38 ($58) TIFR TOV1 $37 ($57) Reserved ...

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Register Summary (Continued) Address Name Bit 7 $02 ($22) Reserved $01 ($21) Reserved $00 ($20) Reserved Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. ...

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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

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Instruction Set Summary (Continued) Mnemonics Operands Description DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers LDI Rd, K Load Immediate LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-Inc Load Indirect and ...

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... Wide, Plastic Dual in Line Package (PDIP) 32A 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) AT90S/LS2333 and AT90S/LS4433 Ordering Code Package AT90LS2333-4AC 32A AT90LS2333-4PC 28P3 AT90LS2333-4AI 32A AT90LS2333-4PI 28P3 AT90S2333-8AC 32A AT90S2333-8PC 28P3 AT90S2333-8AI 32A AT90S2333-8PI ...

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Packaging Information 28P3, 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) AT90S/LS2333 and AT90S/LS4433 102 32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches) PIN 1 ID ...

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... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ...