IC MCU 128K 6MHZ A/D 64TQFP

ATMEGA103-6AC

Manufacturer Part NumberATMEGA103-6AC
DescriptionIC MCU 128K 6MHZ A/D 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AC datasheets
 


Specifications of ATMEGA103-6AC

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Features
®
Utilizes the AVR
RISC Architecture
AVR – High-performance and Low-power RISC Architecture
– 121 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Up to 6 MIPS Throughput at 6 MHz
Data and Nonvolatile Program Memory
– 128K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 4K Bytes Internal SRAM
– 4K Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
– SPI Interface for In-System Programming
Peripheral Features
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
– Real-time Counter (RTC) with Separate Oscillator
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Programmable Watchdog Timer with On-chip Oscillator
– 8-channel, 10-bit ADC
Special Microcontroller Features
– Low-power Idle, Power-save and Power-down Modes
– Software Selectable Clock Frequency
– External and Internal Interrupt Sources
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 5.5 mA
– Idle Mode: 1.6 mA
– Power-down Mode: < 1 µA
I/O and Packages
– 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
– 64-lead TQFP
Operating Voltages
– 2.7 - 3.6V for ATmega103L
– 4.0 - 5.5V for ATmega103
Speed Grades
– 0 - 4 MHz for ATmega103L
– 0 - 6 MHz for ATmega103
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega103
ATmega103L
Note:
Not recommended in new
designs.
Rev. 0945I–AVR–02/07
1

ATMEGA103-6AC Summary of contents

  • Page 1

    ... Programmable I/O Lines, 8 Output Lines, 8 Input Lines – 64-lead TQFP • Operating Voltages – 2.7 - 3.6V for ATmega103L – 4.0 - 5.5V for ATmega103 • Speed Grades – MHz for ATmega103L – MHz for ATmega103 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega103 ATmega103L ...

  • Page 2

    ... Pin Configuration ATmega103(L) 2 TQFP (AD2 (AD1 (AD0 VCC 52 GND 53 (ADC7 (ADC6 (ADC5 (ADC4 (ADC3 (ADC2 (ADC1 (ADC0 AREF INDEX CORNER AGND 63 63 AVCC (T2 (T1 (IC1 (INT3 (INT2 (INT1 (INT0) 24 XTAL1 23 XTAL2 22 GND VCC 21 20 RESET TOSC1 19 TOSC2 18 B7 (OC2/ WM2 0945I–AVR–02/07 ...

  • Page 3

    ... RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega103( powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATmega103(L) AVR is supported with a full suite of program and system develop- ment tools including: C compilers, macro assemblers, program debugger/simulators, In- Circuit Emulators and evaluation kits. ...

  • Page 4

    ... Block Diagram ATmega103(L) 4 Figure 1. The ATmega103(L) Block Diagram PF0 - PF7 VCC GND PORTF BUFFERS AVCC ANALOG MUX ADC AGND AREF PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER REGISTERS INSTRUCTION DECODER CONTROL LINES DATA REGISTER DATA DIR. PORTE REG. PORTE PORTE DRIVER/BUFFERS PE0 - PE7 ...

  • Page 5

    ... Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the inverting Oscillator amplifier. ATmega103(L) 5 ...

  • Page 6

    ... AVCC AREF AGND PEN Clock Options Crystal Oscillator ATmega103(L) 6 Input to the inverting Timer/Counter Oscillator amplifier. Output from the inverting Timer/Counter Oscillator amplifier. External SRAM write strobe External SRAM read strobe ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-order address (8 bits) into an address latch during the first access cycle, and the AD0 - 7 pins are used for data during the second access cycle ...

  • Page 7

    ... OSCILLATOR SIGNAL For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not recommended. ATmega103(L) XTAL2 NC XTAL1 GND 7 ...

  • Page 8

    ... Architectural Overview ATmega103(L) 8 Figure 4. The ATmega103(L) AVR RISC Architecture AVR ATmega103(L) Architecture Program 64K x 16 Counter Program Memory Instruction Register Instruction Decoder Control Lines The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is accessed with a single-level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory ...

  • Page 9

    ... Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. The 4K bytes of SRAM available for general data are implemented as addresses $0060 to $0FFF. ATmega103(L) 0 Addr. R0 $00 R1 ...

  • Page 10

    ... Constant tables can be allocated in the entire Program memory space (see the LPM – Load Program Memory and ELPM – Extended Load Program Memory instruction descriptions). The ATmega103(L) supports two different configurations for the SRAM Data memory as listed in Table 1. Table 1. Memory Configurations ...

  • Page 11

    ... Figure 7. Memory Configurations Memory Configuration A Program Memory Program Flash (32K/64K x 16) Memory Configuration B Program Memory Program Flash (32K/64K x 16) ATmega103(L) Data Memory $0000 32 Registers $0000 - $001F 64 I/O Registers $0020 - $005F $0060 Internal SRAM (4000 x 8) $0FFF $7FFF/$FFFF ...

  • Page 12

    ... Data SRAM. The first 96 locations address the Register File and I/O memory, and the next 4000 locations address the internal Data SRAM. An optional external Data SRAM can be used with the ATmega103(L). This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM ...

  • Page 13

    ... Figure 9. Direct Register Addressing, Two Registers Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 10. I/O Direct Addressing Operand address is contained in six bits of the instruction word the destination or source register address. ATmega103(L) REGISTER FILE REGISTER FILE I/O MEMORY 5 0 ...

  • Page 14

    ... Data Direct Data Indirect with Displacement Data Indirect ATmega103(L) 14 Figure 11. Direct Data Addressing LSBs 15 A 16-bit Data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register. Figure 12. Data Indirect with Displacement Z-REGISTER Operand address is the result of the Y- or Z-register contents added to the address con- tained in six bits of the instruction word ...

  • Page 15

    ... X-, Y-, or the Z-register prior to incrementing. Figure 16. Code Memory Constant Addressing Z-REGISTER Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 32K), LSB selects Low Byte if cleared (LSB = 0) or High Byte if set (LSB = ATmega103(L) Data Space 0 -1 Data Space 0 1 PROGRAM MEMORY ...

  • Page 16

    ... CALL Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL ATmega103(L) 16 1). If ELPM is used, LSB of the RAM Page Z register (RAMPZ) is used to select low or high memory page (RAMPZ0 = 0: Low Page, RAMPZ0 = 1: High Page). Figure 17. Direct Program Memory Addressing ...

  • Page 17

    ... Figure 21 shows the internal timing concept for the Register File single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 21. Single Cycle ALU Operation System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back ATmega103( ...

  • Page 18

    ... System Clock Ø Address Prev. Address Data WR Data RD See “Interface to External SRAM” on page 84. for a description of the access to the external SRAM. The I/O space definition of the ATmega103(L) is shown in Table 2. Table 2. ATmega103(L) I/O Space I/O Address (SRAM Address) Name $3F ($5F) SREG $3E ($5E) SPH ...

  • Page 19

    ... Table 2. ATmega103(L) I/O Space (Continued) I/O Address (SRAM Address) Name $2D ($4D) TCNT1H $2C ($4C) TCNT1L $2B ($4B) OCR1AH $2A ($4A) OCR1AL $29 ($49) OCR1BH $28 ($48) OCR1BL $27 ($47) ICR1H $26 ($46) ICR1L $25 ($45) TCCR2 $24 ($44) TCNT2 $23 ($43) OCR2 $21 ($41) WDTCR $1F ($3F) EEARH $1E ($3E) EEARL ...

  • Page 20

    ... Note: Reserved and unused locations are not shown in the table. All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The dif- ferent I/O locations are directly accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

  • Page 21

    ... This must be handled by software. The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega103(L) supports up to 64K bytes memory, all 16 bits are used. Bit ...

  • Page 22

    ... The RAMPZ Register is normally used to select which 64K RAM page is accessed by the Z pointer. As the ATmega103(L) does not support more than 64K of SRAM memory, this register is used only to select which page in the Program memory is accessed when the ELPM instruction is used. The different settings of the RAMPZ0 bit have the follow- ...

  • Page 23

    ... Bits 2..0 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. The XTAL Divide Control Register is used to divide the XTAL clock frequency by a num- ber in the range 1 - 129. This feature can be used to decrease power consumption when the requirement for processing power is low ...

  • Page 24

    ... ATmega103(L) 24 higher the priority level. RESET has the highest priority and next is INT0 (the External Interrupt Request 0), etc. Table 4. Reset and Interrupt Vectors Program Vector No. Address Source 1 $0000 RESET 2 $0002 INT0 3 $0004 INT1 4 $0006 INT2 5 $0008 INT3 6 $000A INT4 7 $000C INT5 ...

  • Page 25

    ... SPL,r16 $0034 <instr> xxx ... ... ... ... The ATmega103(L) has three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. ...

  • Page 26

    ... ATmega103(L) 26 Figure 23. Reset Logic Power-on Reset VCC Circuit RESET Reset Circuit Watchdog PEN D Q Timer E On-chip RC Oscillator XTAL1 POR 14-stage Ripple Counter Q8 Q11 Q13 Delay Unit 0945I–AVR–02/07 ...

  • Page 27

    ... If the built-in start-up delay is sufficient, RESET can be connected external pull-up resistor. By holding the pin low for a period after V applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing example of this. ATmega103(L) = 5.0V) CC Condition Min Typ 1 ...

  • Page 28

    ... External Reset ATmega103(L) 28 Figure 24. MCU Start-up, RESET Tied POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 25. MCU Start-up, RESET Controlled Externally V POT VCC RESET TIME-OUT INTERNAL RESET An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset even if the clock is not running. Shorter pulses are not guaranteed to generate a reset ...

  • Page 29

    ... Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. • Bit 1 – EXTRF: External Reset Flag After a Power-on Reset, this bit is undefined (X). It will be set by an external reset. A Watchdog reset will leave this bit unchanged. ...

  • Page 30

    ... Power-on Reset External Reset Power-on Reset The ATmega103(L) has two dedicated 8-bit Interrupt Mask Control Registers; EIMSK (External Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). In addition, other enable and mask bits can be found in the peripheral control registers. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled ...

  • Page 31

    ... Alternatively, the flag is cleared by writing a logical “1” to it. These flags are always cleared when INTF7 - INFT4 are configured as level interrupts. • Bits 3..0 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. Bit 7 ...

  • Page 32

    ... ATmega103(L) 32 cuting instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. 0945I–AVR–02/07 ...

  • Page 33

    ... When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at vector $001E) is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register. ATmega103( ...

  • Page 34

    ... ATmega103(L) 34 • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $0020) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register. 0945I– ...

  • Page 35

    ... Bit 2 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1 ATmega103( ...

  • Page 36

    ... Interrupt Response Time Sleep Modes Idle Mode ATmega103(L) 36 (Tim er/Co un ter1 Ove rflow Inte rrup t En able set (o ne Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000. • Bit 1 – OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data in OCR0 – ...

  • Page 37

    ... If the asynchronous timer is not clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be consid- ered undefined after wake-up in Power-save mode if AS0 is 0. ATmega103(L) 37 ...

  • Page 38

    ... Prescalers ATmega103(L) 38 The ATmega103(L) provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter0 optionally can be asynchronously clocked from an external Oscillator. This Oscillator is optimized for use with a 32.768 kHz crystal, enabling use of Timer/Counter0 as a Real Time Clock (RTC). Timer/Counter0 has its own prescaler ...

  • Page 39

    ... TIMER INT. MASK REGISTER (TIMSK TIMER/COUNTER0 (TCNT0 8-BIT COMPARATOR 7 0 OUTPUT COMPARE REGISTER0 (OCR0) CK TCK0 ATmega103(L) T/C0 OVER- T/C0 COMPARE FLOW IRQ MATCH IRQ TIMER INT. FLAG T/C0 CONTROL REGISTER (TIFR) REGISTER (TCCR0) T/C CLEAR T/C CLK SOURCE CONTROL UP/DOWN LOGIC ASYNCH. STATUS ...

  • Page 40

    ... ATmega103(L) 40 Figure 31. Timer/Counter2 Block Diagram T/C2 OVER- FLOW IRQ TIMER INT. MASK REGISTER (TIMSK TIMER/COUNTER2 (TCNT2 8-BIT COMPARATOR 7 0 OUTPUT COMPARE REGISTER2 (OCR2) The 8-bit Timer/Counter0 can select clock source from PCK0 or prescaled PCK0. The 8- bit Timer/Counter2 can select clock source from CK, prescaled external pin. ...

  • Page 41

    ... Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATmega103(L) and always reads as zero. • Bit 6 – PWM0/PWM2: Pulse Width Modulator Enable When set (one), this bit enables PWM mode for Timer/Counter0 or Timer/Counter2. This mode is described on page 43. ...

  • Page 42

    ... Timer/Counter0 – TCNT0 Timer/Counter2 – TCNT2 ATmega103( PWM mode, this bit has no effect. • Bits – CS02, CS01, CS00/CS22, CS21, CS20: Clock Select Bits 2, 1 and 0 The Clock Select2 bits 2, 1 and 0 define the prescaling source of the Timer/Counter. Table 11. Timer/Counter0 Prescale Select ...

  • Page 43

    ... Note that in PWM mode, the Output Compare Register is transferred to a temporary location when written. The value is latched when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsyn- chronized OCR0 or OCR2 write. See Figure 32 for an example. ATmega103( ...

  • Page 44

    ... Read/Write Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. Counter Value Compare Value PWM Output Counter Value Compare Value PWM Output Glitch OCRn Output PWMn $00 L $FF ...

  • Page 45

    ... The external clock signal should therefore be in the interval 256 kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower than one fourth of the CPU main clock frequency. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. ATmega103(L) 45 ...

  • Page 46

    ... ATmega103(L) 46 • When writing to one of the registers TCNT0, OCR0 or TCCR0, the value is transferred to a temporary register and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e ...

  • Page 47

    ... The Timer/Counter1 supports two Output Compare functions using the Output Compare Registers 1A and 1B (OCR1A and OCR1B) as the data sources to be compared to the Timer/Counter1 contents. The Output Compare functions include optional clearing of the counter on Compare A Match, and actions on the Output Compare pins on both compare matches. ATmega103(L) 47 ...

  • Page 48

    ... ATmega103(L) 48 Figure 33. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE MATCHA IRQ FLOW IRQ TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR T/C1 INPUT CAPTURE REGISTER (ICR1 TIMER/COUNTER1 (TCNT1 16-BIT COMPARATOR TIMER/COUNTER1 OUTPUT COMPARE REGISTER A Timer/Counter1 can also be used 10-bit Pulse Width Modulator. In this mode the counter and the OCR1A/OCR1B Registers serve as a dual glitch-free stand- alone PWM with centered pulses ...

  • Page 49

    ... In PWM mode, these bits have a different function. Refer to Table 16 for a detailed description. • Bits 3..2 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. • Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 18 on page 53 ...

  • Page 50

    ... Input Capture Register on the rising edge of the Input Capture pin – PD4(IC1). • Bits 5, 4 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a Compare A Match ...

  • Page 51

    ... High Byte TCNT1H is placed in the TEMP Register. When the CPU reads the data in the High Byte TCNT1H, the CPU receives the data in the TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a ATmega103(L) Description Stop, the Timer/Counter1 is stopped. ...

  • Page 52

    ... Compare Register – OCR1BH and OCR1BL Timer/Counter1 Input Capture Register – ICR1H and ICR1L ATmega103(L) 52 full 16-bit register read operation. When using Timer/Counter1 as an 8-bit Timer sufficient to read the Low Byte only. The Timer/Counter1 is realized up/down (in PWM mode) counter with read and write access ...

  • Page 53

    ... Cleared on compare match, up-counting. Set on compare match down-counting (non-inverted PWM). Cleared on compare match, down-counting. Set on compare match up-counting (inverted PWM). Note Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches ATmega103( ...

  • Page 54

    ... ATmega103(L) 54 the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example. Figure 35. Effects on Unsynchronized OCR1 Latching Compare Value changes Synchronized OCR1X Latch Compare Value changes Unsynchronized Note During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location ...

  • Page 55

    ... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared, Otherwise, the Watchdog will not be disabled ...

  • Page 56

    ... ATmega103( the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the Watchdog. • ...

  • Page 57

    ... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always be read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is enabled ...

  • Page 58

    ... ATmega103(L) 58 • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles ...

  • Page 59

    ... CPU from attempting to decode and execute instructions, effec- tively protecting the EEPROM Registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption. ATmega103(L) Reset Protection circuit, often CC . This CC ...

  • Page 60

    ... Serial Peripheral Interface – SPI ATmega103(L) 60 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega103(L) and peripheral devices or between several AVR devices. The ATmega103(L) SPI features include the following: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...

  • Page 61

    ... SPI is activated and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once ATmega103(L) LSB MSB ...

  • Page 62

    ... Data Modes SPI Control Register – SPCR ATmega103(L) 62 the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost. There are four combinations of SCK phase and polarity with respect to serial data that are determined by control bits CPHA and CPOL ...

  • Page 63

    ... The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg- ister with WCOL set (one), and then accessing the SPI Data Register. ATmega103(L) SCK Frequency f ...

  • Page 64

    ... ATmega103(L) 64 • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. 0945I–AVR–02/07 ...

  • Page 65

    ... X X The SPI Data Register is a read/write register used for data transfer between the Regis- ter File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. ATmega103( LSB ...

  • Page 66

    ... UART Data Transmission ATmega103(L) 66 The ATmega103(L) features a full duplex (separate Receive and Transmit Registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator that can Generate a large Number of Baud Rates (bps) • High Baud Rates at Low XTAL Frequencies • ...

  • Page 67

    ... The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is cleared (zero), the PE1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PE1, which is forced output pin regardless of the setting of the DDE1 bit in DDRE. ATmega103(L) /16 UART I/O DATA REGISTER (UDR) ...

  • Page 68

    ... Data Reception ATmega103(L) 68 Figure 42. UART Receiver XTAL BAUD X 16 BAUD RATE GENERATOR PIN CONTROL LOGIC DATA RECOVERY RXD LOGIC The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated ...

  • Page 69

    ... When the CHR9 bit in the UCR Register is set, transmitted and received characters are 9 bits long plus start and stop bits. The 9th data bit to be transmitted is the TXB8 bit in UCR Register. This bit must be set to the wanted value before a transmission is initated by writing to the UDR Register. ATmega103( ...

  • Page 70

    ... UART Control UART I/O Data Register – UDR UART Status Register – USR ATmega103(L) 70 Bit $0C ($2C) MSB Read/Write R/W R/W R/W Initial Value The UDR Register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. ...

  • Page 71

    ... Receiver Shift Register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. • Bits 2..0 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. Bit 7 6 ...

  • Page 72

    ... ATmega103(L) 72 • Bit 1 – RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. • Bit 0 – TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted. 0945I–AVR–02/07 ...

  • Page 73

    ... XTAL frequency if the XTAL divider is enabled. UBRR values that yield an actual baud rate differing less than 2% from the target baud rate are in boldface in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance. ATmega103( ...

  • Page 74

    ... UBRR= 47 14400 UBRR= 31 19200 UBRR= 23 28800 UBRR= 15 38400 UBRR= 11 57600 UBRR= 76800 UBRR= 115200 UBRR= UART Baud Rate Register – UBRR ATmega103(L) 74 1.8432 MHz %Error 0.2 UBRR= 0.0 UBRR= 47 0.2 UBRR= 0.0 UBRR 7.5 UBRR= 11 0.0 UBRR= 3 7.8 UBRR= 7 0.0 UBRR ...

  • Page 75

    ... ACIE bit in ACSR. Otherwise, an interrupt can occur when the bit is changed. • Bit 6 – Res: Reserved Bit This bit is a reserved bit in the ATmega103(L) and will always read as zero. • Bit 5 – ACO: Analog Comparator Output ACO is directly connected to the comparator output. ...

  • Page 76

    ... ATmega103(L) 76 ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical “1” to the flag. Observe, however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana- log Comparator interrupt is activated ...

  • Page 77

    ... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATmega103(L) features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer, which allows each pin of Port used as an input for the ADC. The ADC contains a Sample and Hold Amplifier, which ensures that the input voltage to the ADC is held at a constant level during conversion ...

  • Page 78

    ... Operation Prescaling ATmega103(L) 78 The ADC operates in Single Conversion mode, and each conversion will have to be ini- tiated by the user. The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started after enabling the ADC will be preceded by a dummy conversion to initialize the ADC ...

  • Page 79

    ... ADCH ADCL Dummy Conversion Table 26. ADC Conversion Time Sample Cycle Condition Number 1st Conversion 14 Single Conversion 1 Figure 48. ADC Timing Diagram Cycle number ADC clock ADSC Hold strobe ADIF ADCH ADCL ATmega103( Actual Conversion Result Ready Total (Cycle Conversion Number) Time (Cycles ...

  • Page 80

    ... Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. • Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits The value of these three bits selects which analog input connected to the ADC. ...

  • Page 81

    ... ADCH 0945I–AVR–02/07 • Bit 5 – Res: Reserved Bit This bit is reserved in the ATmega103(L). Warning: When writing ADCSR, a logical “0” must be written to this bit. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion is complete and the result is written to the ADC Data Registers are updated ...

  • Page 82

    ... If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATmega103(L) and all analog components in the applica- tion should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. ...

  • Page 83

    ... VREF > 2V Non-linearity Zero Error (Offset) Conversion Time Clock Frequency Analog AV Supply CC Voltage Reference V REF Voltage Reference R Input REF Resistance Analog Input R AIN Resistance Notes: 1. Minimum for AV is 2.7V Maximum for AV is 6.0V. CC ATmega103(L) Min Typ Max 0.5 0 280 50 200 ( 0 0 100 ...

  • Page 84

    ... Interface to External SRAM ATmega103(L) 84 The interface to the SRAM consists of: Port A: multiplexed low-order address bus and data bus Port C: high-order address bus The ALE pin: address latch enable The RD and WR pin: read and write strobes The external data SRAM is enabled by setting the external SRAM enable bit (SRE) of the MCU Control Register (MCUCR) and will override the setting of the Data Direction Register (DDRA) ...

  • Page 85

    ... Data / Address [7..0] Prev. Address RD Figure 52. External SRAM Access Cycle with Wait State T1 System Clock Ø ALE Address [15..8] Prev. Address Data / Address [7..0] Prev. Address WR Data / Address [7..0] Prev. Address RD ATmega103( Address Address Data Address Data T2 T3 Address Address Data Address ...

  • Page 86

    ... DDRA Port A Input Pins Address – PINA Port A as General Digital I/O ATmega103(L) 86 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input) ...

  • Page 87

    ... Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as ATmega103(L) Pull-up Comment No ...

  • Page 88

    ... DDRB Port B Input Pins Address – PINB Port B as General Digital I/O ATmega103(L) 88 inputs and are externally pulled low, they will source current if the internal pull-up resis- tors are activated. The Port B pins with alternate functions are shown in Table 29. ...

  • Page 89

    ... SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a Master, the data direction of this pin is controlled by ATmega103(L) Pull-up Comment ...

  • Page 90

    ... Port B Schematics ATmega103(L) 90 DDB1. When the pin is forced input, the pull-up can still be controlled by the PORTB1 bit. See the description of the SPI port for further details. • SS – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0 ...

  • Page 91

    ... Figure 55. Port B Schematic Diagram (Pin PB1) Figure 56. Port B Schematic Diagram (Pin PB2) ATmega103(L) 91 ...

  • Page 92

    ... ATmega103(L) 92 Figure 57. Port B Schematic Diagram (Pin PB3) Figure 58. Port B Schematic Diagram (Pin PB4) MOS PULL- UP PB4 WP: WRITE PORTB WD: WRITE DDRB READ PORTB LATCH RL: RP: READ PORTB PIN RD: READ DDRB RD RESET DDB4 C WD RESET PORTB4 COM01 COM01 OUTPUT COMP. MATCH 0 MODE SELECT ...

  • Page 93

    ... READ PORTB LATCH RL: READ PORTB PIN RP: READ DDRB RD Figure 60. Port B Schematic Diagram (Pin PB7) MOS PULL- UP PB7 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB ATmega103(L) RD RESET DDBn C WD RESET PORTBn COM1X0 COM1X1 OUTPUT COMP. MATCH 1X MODE SELECT RD RESET ...

  • Page 94

    ... Port C The Port C Data Register – PORTC Port C Schematics Port D ATmega103(L) 94 Port 8-bit output port. The Port C pins have alternate functions related to the optional external data SRAM. When using the device with external SRAM, Port C outputs the high-order address byte during accesses to external Data memory. When a reset condition becomes active, the port pins are not tri-stated, but the pins will assume their initial value after two stable clock cycles ...

  • Page 95

    ... INT0..INT3 – Port D, Bits 0..3 External Interrupt sources The PD0 - PD3 pins can serve as external active low interrupt sources to the MCU. The internal pull-up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the sources. ATmega103( ...

  • Page 96

    ... Port D Schematics ATmega103(L) 96 • IC1 – Port D, Bit 4 IC1, Input Capture pin for Timer/Counter1. When a positive or negative (selectable) edge is applied to this pin, the contents of Timer/Counter1 is transferred to the Timer/Counter1 Input Capture Register. The pin has to be configured as an input to serve this function. See the Timer/Counter1 description on how to operate this function. ...

  • Page 97

    ... READ PORTD PIN RD: READ DDRD ACIC: COMPARATOR IC ENABLE ACO: COMPARATOR OUTPUT Figure 64. Port D Schematic Diagram (Pin PD5) MOS PULL- UP PD5 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ATmega103(L) RD RESET DDD4 C WD RESET PORTD4 NOISE CANCELER EDGE SELECT 1 ...

  • Page 98

    ... Port E ATmega103(L) 98 Figure 65. Port D Schematic Diagram (Pins PD6 and PD7) MOS PULL- UP PDn WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD Port 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the Port E, one each for the Data Register – ...

  • Page 99

    ... PDI/RXD – Port E, Bit 0 PDI, Serial Programming Data Input. During Serial Program downloading, this pin is used as data input line for the ATmega103(L). RXD, UART Receive Pin. Receive Data (Data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input regardless of the value of DDRD0. ...

  • Page 100

    ... Port E Schematics ATmega103(L) 100 TXD, UART Transmit Pin. • AC+ – Port E, Bit 2 AC+, Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator. • AC- – Port E, Bit 3 AC-, Analog Comparator Negative Input. This pin is directly connected to the negative input of the analog comparator. • ...

  • Page 101

    ... Figure 67. Port E Schematic Diagram (Pin PE1) Figure 68. Port E Schematic Diagram (Pin PE2) MOS PULL- UP PE2 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE ATmega103(L) RD RESET Q D DDE2 C WD RESET Q D PORTE2 AC+ TO COMPARATOR 101 ...

  • Page 102

    ... ATmega103(L) 102 Figure 69. Port E Schematic Diagram (Pin PE3) MOS PULL- UP PE3 WP: WRITE PORTE WD: WRITE DDRE RL: READ PORTE LATCH RP: READ PORTE PIN RD: READ DDRE Figure 70. Port E Schematic Diagram (Pins PE4, PE5, PE6 and PE7) MOS PULL- UP PEn WP: WRITE PORTE WD: WRITE DDRE RL: ...

  • Page 103

    ... R R Initial Value N/A N/A N/A The Port F Input Pins address (PINF) is not a register; this address enables access to the physical value on each Port F pin. Figure 71. Port F Schematic Diagram (Pins PF7 - PF0) PFn RP: READ PORTF PIN ATmega103( PINF4 PINF3 PINF2 PINF1 N/A ...

  • Page 104

    ... EEPROM ATmega103(L) 104 The ATmega103(L) MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 35. The Lock bits can only be erased to “1” with the Chip Erase command. Table 35. Lock Bit Protection Modes ...

  • Page 105

    ... Parallel Programming Signal Names 0945I–AVR–02/07 The Flash Program memory array on the ATmega103(L) is organized as 512 pages of 256 bytes each. When programming the Flash, the Program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously in either Programming mode ...

  • Page 106

    ... ATmega103(L) 106 . Table 37. Pin Name Mapping Signal Name in Programming Mode Pin Name RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 BS2 PD7 PAGEL PA0 DATA PB7 - 0 Table 38. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) ...

  • Page 107

    ... Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data Low Byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the data byte. D: Latch Data Low Byte. 1. Give PAGEL a positive pulse. This latches the data Low Byte. (See Figure 73 for signal waveforms.) ATmega103(L) and GND. CC 3.6V 4. ...

  • Page 108

    ... ATmega103(L) 108 E: Load Data High Byte. 1. Set BS1 to “1”. This selects high data. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data High Byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the data High Byte. F: Latch Data High Byte. ...

  • Page 109

    ... Address High Byte needs only be loaded before programming a new 256-word page in the EEPROM. • Skip writing the data value $FF that is the contents of the entire EEPROM after a chip erase. These considerations also apply to Flash, EEPROM and signature bytes reading. ATmega103(L) 109 ...

  • Page 110

    ... Reading the Flash Reading the EEPROM Programming the Fuse Bits ATmega103(L) 110 Figure 75. Programming the EEPROM Waveforms DATA $11 ADDR. HIGH XA1 XA2 BS1 XTAL1 WR RDY/BSY +12V RESET OE BS2 PAGEL The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” ...

  • Page 111

    ... Flash” on page 107 for details on command and address loading Load Command “0000 1000” Load Address Low Byte ($00 - $02). Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA. 3. Set OE to “1”. ATmega103( WLWH_PFB 111 ...

  • Page 112

    ... Parallel Programming Characteristics ATmega103(L) 112 Figure 76. Parallel Programming Timing t XTAL1 XHXL t DVXH Data & Contol (DATA, XA0/1, BS1) t BVXH PAGEL t PHPL WR RDY/BSY OE DATA Table 41. Parallel Programming Characteristics T Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP t Data and Control Valid before XTAL1 High ...

  • Page 113

    ... SPI pin as usual. When writing serial data to the ATmega103(L), data is sampled by the ATmega 103/103L on the rising edge of SCK. When reading data from the ATmega103(L), data is clocked on the falling edge of SCK. See Figure 78 for an explanation. To program and verify the ATmega103(L) in the Serial Programming mode, the following sequence is recommended (See 4-byte instruction formats in Table 44 ...

  • Page 114

    ... Data Polling for the EEPROM ATmega103(L) 114 As an alternative to using the RESET signal, PEN can be held low during Power- on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is important crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin ...

  • Page 115

    ... Table 42. Minimum Wait Delay before Writing the Next Flash or EEPROM Location Symbol 3.2V (Note WD_FLASH WD_EEPROM Note: Per page. Table 43. Read Back Value during EEPROM Polling Part/Revision TBD Note: See Errata sheet for latest information. ATmega103(L) 3.6V 4.0V 5. TBD TBD 115 ...

  • Page 116

    ... – Low byte, 1 – High byte o = data out i = data don’t care 1 = Lock Bit Lock Bit SUT0 Fuse 4 = SUT1 Fuse 5 = SPIEN Fuse 6 = EESAVE Fuse ATmega103(L) 116 Instruction Format Byte 2 Byte 3 Byte 4 0101 0011 xxxx xxxx xxxx xxxx 100x xxxx xxxx xxxx ...

  • Page 117

    ... Figure 78. Serial Programming Waveforms SERIAL DATA INPUT MSB PE0(PDI/RXD) SERIAL DATA OUTPUT MSB PE1(PDO/TXD) SERIAL CLOCK INPUT PB1(SCK) SAMPLE ATmega103(L) LSB LSB 117 ...

  • Page 118

    ... V OH Ports Input Leakage IL Current I/O Pin I Input Leakage IH Current I/O Pin RRST Reset Pull-up R I/O Pin Pull-up I/O I Power Supply Current CC ATmega103(L) 118 *NOTICE: + .5V CC Condition Min Except (XTAL) -0.5 XTAL -0.5 Except (XTAL, RESET) 0.6 V XTAL 0.7 V RESET 0. mA, V ...

  • Page 119

    ... 2. 4.0V CC may exceed the related specification. Pins are not guaranteed to sink current greater OL may exceed the related specification. Pins are not guaranteed to source current OH ATmega103(L) Min Typ Max 40 -50 50 750 500 = 5V 3V) under steady-state 5V, 1 3V) under steady-state CC CC Units 119 ...

  • Page 120

    ... WLWH Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. ATmega103(L) 120 6 MHz Oscillator Variable Oscillator Min ...

  • Page 121

    ... CLCL 0.0 230.0 1.0 t CLCL 100.0 0.5 t CLCL 4 MHz Oscillator Min Max 460.0 480.0 2.0 t CLCL 480.0 2.0 t CLCL 350.0 1.5 t CLCL ATmega103(L) Variable Oscillator Min Max Unit 0.0 4.0 MHz (1) - 60.0 ns (1) - 50.0 ns (2) ns CLCL ns ( 45 ...

  • Page 122

    ... External Clock Drive Waveforms ATmega103(L) 122 Figure 79. External RAM Timing T1 0 System Clock Ø ALE 4 Address [15..8] Prev. Address Data / Address [7..0] Prev. Address 3a WR Data / Address [7..0] Prev. Address Address RD Note: Clock cycle T3 is only present when external SRAM Wait State is enabled. ...

  • Page 123

    ... The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif- ferential current drawn by the Watchdog Timer. Figure 81. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY ATmega103(L) = operating voltage and f = average switching 25˚ ...

  • Page 124

    ... ATmega103(L) 124 Figure 82. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 Figure 83. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY FREQUENCY = 4 MHz ˚ A 3.5 4 4.5 5 5 25˚ Frequency (MHz ˚ 5. 4. 0945I–AVR–02/07 ...

  • Page 125

    ... Figure 84. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 2.5 3 Figure 85. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 2.5 3 ATmega103( FREQUENCY = 4 MHz ˚ A 3 3.5 4 4.5 5 5 ˚ ˚ ˚ ˚ ˚ 125 ...

  • Page 126

    ... ATmega103(L) 126 Figure 86. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 250 200 150 100 2.5 3 Figure 87. Power-save Supply Current vs. V POWER SAVE SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 2 ˚ A 3.5 4 4.5 5 5 3.5 4 4.5 5 5 ˚ ˚ ...

  • Page 127

    ... Analog comparator offset voltage is measured as absolute offset. Figure 89. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 1.5 ATmega103( ˚ 3 ˚ 2.5 3 3.5 4 Common Mode Voltage (V) C ˚ ...

  • Page 128

    ... ATmega103(L) 128 Figure 90. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 91. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1 ˚ 1 ˚ 3 ...

  • Page 129

    ... Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 93. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 100 0.5 1 1.5 ATmega103( 3 ˚ C ˚ 2 2 ˚ ...

  • Page 130

    ... ATmega103(L) 130 Figure 94. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ˚ 0.5 1 Figure 95. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0 2.7V cc 1.5 2 2 ˚ ˚ A 1.5 2 2 0945I–AVR–02/07 ...

  • Page 131

    ... Figure 96. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 1.5 Figure 97. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 ATmega103( 2 ˚ ˚ 1.5 V ( 131 ...

  • Page 132

    ... ATmega103(L) 132 Figure 98. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 Figure 99. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0 2.7V cc 1.5 2 2 ˚ 0945I–AVR–02/ ...

  • Page 133

    ... Figure 100. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 ATmega103( ˚ 5.0 133 ...

  • Page 134

    ... Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instruc- tions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. ATmega103(L) 134 Bit6 ...

  • Page 135

    ... Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS ELPM Extended Load Program Memory MOV Rd, Rr Move between Registers LDI Rd, K Load Immediate 0945I–AVR–02/07 ATmega103(L) Operation Rd ← ← Rdh:Rdl ← Rdh:Rdl + K Rd ← ← ← ← Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • ← ...

  • Page 136

    ... Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset ATmega103(L) 136 Operation Rd ← (X) Rd ← (X), X ← ← ← (X) Rd ← (Y) Rd ← (Y), Y ← ← ← (Y) Rd ← ← (Z) Rd ← ...

  • Page 137

    ... Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 0945I–AVR–02/07 Ordering Code Package ATmega103L-4AC 64A ATmega103L-4AI 64A ATmega103-6AC 64A ATmega103-6AI 64A Package Type ATmega103(L) Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0° ...

  • Page 138

    ... JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega103(L) 138 B PIN 1 IDENTIFIER ...

  • Page 139

    ... Timer/Counter1......................................................................................... 47 Watchdog Timer.................................................................................. 55 EEPROM Read/Write Access............................................................. 57 Prevent EEPROM Corruption ............................................................................. 59 Serial Peripheral Interface – SPI........................................................ 60 Data Modes ........................................................................................................ 62 UART.................................................................................................... 66 Data Transmission.............................................................................................. 66 Data Reception ................................................................................................... 68 UART Control ..................................................................................................... 70 Analog Comparator ............................................................................ 75 Analog-to-Digital Converter............................................................... 77 Feature list: ......................................................................................................... 77 Operation ............................................................................................................ 78 Prescaling ........................................................................................................... 78 ADC Noise Canceler Function............................................................................ 80 ADC Noise Canceling Techniques ..................................................................... 82 ATmega103(L) i ...

  • Page 140

    ... ATmega103(L) ii ADC DC Characteristics ..................................................................................... 83 Interface to External SRAM................................................................ 84 I/O Ports............................................................................................... 86 Port A.................................................................................................................. 86 Port B.................................................................................................................. 87 Port C.................................................................................................................. 94 Port D.................................................................................................................. 94 Port E.................................................................................................................. 98 Port F ................................................................................................................ 103 Memory Programming...................................................................... 104 Program and Data Memory Lock Bits............................................................... 104 Fuse Bits........................................................................................................... 104 Signature Bytes ................................................................................................ 104 Programming the Flash and EEPROM............................................................. 104 Parallel Programming ...

  • Page 141

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...